HY27UG088G5M-TMS_技术文档

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

8Gb NAND FLASH

HY27UG088G5M

HY27UG088GDM

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.6 / Dec. 2006

1

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Document Title

8Gbit (1Gx8bit) NAND Flash Memory

Revision History

Revision

History

No.

Draft Date

Remark

0.0

Sep. 08. 2005

Initial

Initial Draft.

1) Add HY27UG088G5M & HY27UG088GDM Products.

- Texts & figures are added.

2) Change Ac Characteristics

tR

20

25

tAR

10

tREA

18

tRHZ

30

tCHZ

30

tCEA

25

Before

After

15

20

50

35

tCLS

tWP

tDS

12

tWC

tADL

tRP

tRC

25

Before

After

12

15

12

15

25

30

70

12

15

0.1

Oct. 23. 2005 Preliminary

15

100

30

3) Add tCRRH (100ns, Min)

- tCRRH: cache Read RE High

4) Change 3rd Read ID

- 3rd Read ID is changed to C1h

- 3rd Byte of Device Identifier Table is added.

5) Change NOP

- Number of Partial Program Cycle in the same page is changed to 4.

6) Delete Concurrent Operation.

1) Change AC Characteristics

tREA

20

tCEA

35

tCS

20

0.2

Nov. 16. 2005 Preliminary

Before

After

25

30

25

Rev. 0.6 / Dec. 2006

2

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Revision History

- Continued

Revision

No.

History

Draft Date Remark

1) Correct Read ID naming

2) Add ECC algorithm. (1bit/512bytes)

3) Change valid block number (max)

valid block number

Before

8092

8192

After

4) Change NOP

5) Change DC characterics

0.3

Jun. 20. 2006 Preliminary

ICC1

ICC2

ICC3

Typ Max Typ Max Typ Max

Before

After

25

15

45

30

25

15

45

30

25

15

45

30

6) Delete TSOP 1CE package dimension & figures.

1) Delete Preliminary.

0.4

0.5

Jul. 10. 2006

Oct. 02. 2006

1) Correct copy back function.

1) Delete PRE function.

0.6

2) Delete Lock & Unlock function.

3) Delete Auto Read function.

Dec. 26. 2006

Rev. 0.6 / Dec. 2006

3

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES

- Cost effective solutions for mass storage applications

STATUS REGISTER

ELECTRONIC SIGNATURE

NAND INTERFACE

- x8 width.

- Multiplexed Address/ Data

- 1st cycle: Manufacturer Code

- 2nd cycle: Device Code

- Pinout compatibility for all densities

CHIP ENABLE DON'T CARE

- Simple interface with microcontroller

SUPPLY VOLTAGE

- 3.3V device: VCC = 2.7 to 3.6V : HY27UG088G(5/D)M

SERIAL NUMBER OPTION

Memory Cell Array

HARDWARE DATA PROTECTION

- Program/Erase locked during Power transitions

= (2K+ 64) Bytes x 64 Pages x 8,192 Blocks

DATA INTEGRITY

- 100,000 Program/Erase cycles (with 1bit/512byte ECC)

- 10 years Data Retention

PAGE SIZE

- x8 device : (2K + 64 spare) Bytes

: HY27UG088G(5/D)M

PACKAGE

- HY27UG088G5M-T(P)

BLOCK SIZE

- x8 device: (128K + 4K spare) Bytes

: 48-Pin TSOP1 (12 x 20 x 1.2 mm)

- HY27UG088G5M-T (Lead)

- HY27UG088G5M-TP (Lead Free)

PAGE READ / PROGRAM

- Random access: 25us (max.)

- Sequential access: 30ns (min.)

- Page program time: 200us (typ.)

- HY27UG088GDM-UP

:52- ULGA (12 x 17 x 0.65 mm)

- HY27UG088GDM-DP (Lead Free)

COPY BACK PROGRAM MODE

- Fast page copy without external buffering

CACHE PROGRAM MODE

- Internal Cache Register to improve the program

throughput

FAST BLOCK ERASE

- Block erase time: 2ms (Typ.)

Rev. 0.6 / Dec. 2006

4

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

1. SUMMARY DESCRIPTION

The HYNIX HY27UG088G(5/D)M series is a 1Gx8bit with spare 32Mx8 bit capacity. The device is offered in 3.3V Vcc

Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old

data is erased.

The device contains 8192 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected

Flash cells.

A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in

typical 2ms on a 128K-byte(X8 device) block.

Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and

data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-

ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where

required, and internal verification and margining of data.

The modifying can be locked using the WP input pin.

The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-

ple memories the R/B pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27UG088G(2/5/D)M extended reliability of 100K pro-

gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

The chip could be offered with the CE don’t care function. This function allows the direct download of the code from

the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.

The copy back function allows the optimization of defective blocks management: when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is copied into the

flash array. This pipelined program operation improves the program throughput when long files are written inside the

memory.

A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-

secutive pages have to be streamed out.

This device includes also extra features like OTP/Unique ID area, Read ID2 extension.

The HYNIX HY27UG088G(5/D)M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.

1.1 Product List

PART NUMBER

HY27UG088G5M

HY27UG088GDM

ORIZATION

VCC RANGE

2.7V - 3.6 Volt

PACKAGE

48TSOP1

52-ULGA

x8

Rev. 0.6 / Dec. 2006

5

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

9&&

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Figure1: Logic Diagram

IO7 - IO0

CLE

ALE

CE

Data Input / Outputs

Command latch enable

Address latch enable

Chip Enable

RE

Read Enable

WE

Write Enable

WP

Write Protect

R/B

Vcc

Ready / Busy

Power Supply

Vss

Ground

NC

No Connection

Table 1: Signal Names

Rev. 0.6 / Dec. 2006

6

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

ꢂ

ꢆꢉ

1&

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9FF

9VV

1&

9FF

9VV

1&

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ꢂꢇ

ꢀꢁ

ꢀꢂ

1&

ꢂ[ꢃꢄ

&/(

$/(

:(

:3

1&

,ꢀ2ꢇ

,ꢀ2ꢁ

,ꢀ2ꢂ

,ꢀ2ꢈ

1&

ꢁꢆ

ꢁꢅ

Figure 2. 48TSOP1 Contactions, x8 Device (2CE)

Rev. 0.6 / Dec. 2006

7

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

$

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+

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Figure 3. 52-ULGA Contactions, x8 Device, Dual interface

(Top view through package)

Rev. 0.6 / Dec. 2006

8

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

1.2 PIN DESCRIPTION

Pin Name

Description

DATA INPUTS/OUTPUTS

The IO pins allow to input command, address and data and to output data during read / program

operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to

High-Z when the device is deselected or the outputs are disabled.

IO0-IO7

COMMAND LATCH ENABLE

CLE

ALE

This input activates the latching of the IO inputs inside the Command Register on the Rising edge of

Write Enable (WE).

ADDRESS LATCH ENABLE

This input activates the latching of the IO inputs inside the Address Register on the Rising edge of

Write Enable (WE).

CHIP ENABLE

CE1, CE2

WE

This input controls the selection of the device. When the device is busy CE1, CE2 low does not deselect

the memory.

WRITE ENABLE

This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise

edge of WE.

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is

valid tREA after the falling edge of RE which also increments the internal column address counter by

one.

RE

WRITE PROTECT

WP

The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)

operations.

READY BUSY

R/B1, R/B2

VCC

The Ready/Busy output is an Open Drain pin that signals the state of the memory.

SUPPLY VOLTAGE

The VCC supplies the power for all the operations (Read, Write, Erase).

VSS

NC

GROUND

NO CONNECTION

Table 2: Pin Description

NOTE:

1. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple

the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required

during program and erase operations.

Rev. 0.6 / Dec. 2006

9

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

IO0

A0

IO1

A1

IO2

A2

IO3

A3

IO4

IO5

IO6

IO7

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

A4

A5

A6

A7

L⁽¹⁾

A16

A24

L⁽¹⁾

A17

A25

L⁽¹⁾

A18

A26

L⁽¹⁾

A19

A27

A8

A9

A10

A14

A22

A11

A15

A23

A12

A20

A28

A13

A21

A29

L⁽¹⁾

Table 3: Address Cycle Map(2CE & Dual)

NOTE:

1. L must be set to Low.

Acceptable command

during busy

FUNCTION

1st CYCLE

2nd CYCLE

3rd CYCLE

00h

90h

FFh

80h

85h

80h

60h

70h

85h

05h

00h

34h

30h

35h

-

READ FOR COPY-BACK

READ ID

RESET

-

Yes

PAGE PROGRAM (start)

COPY BACK PGM (start)

CACHE PROGRAM

BLOCK ERASE

10h

15h

D0h

-

READ STATUS REGISTER

RANDOM DATA INPUT

RANDOM DATA OUTPUT

CACHE READ START

CACHE READ EXIT

-

E0h

31h

-

Table 4: Command Set

Rev. 0.6 / Dec. 2006

10

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

CLE

H

L

ALE

L

CE

L

WE

Rising

H

RE

WP

MODE

H

X

Command Input

Read Mode

H

L

H

X

Address Input(5 cycles)

H

L

H

Command Input

Write Mode

H

L

H

Address Input(5 cycles)

L

H

Data Input

L⁽¹⁾

L

Falling

X

Sequential Read and Data Output

During Read (Busy)

During Program (Busy)

During Erase (Busy)

Write Protect

L

H

X

H

X

H

L

X

H

X

0V/Vcc

Stand By

Table 5: Mode Selection

NOTE:

1. With the CE high during latency time does not stop the read operation

Rev. 0.6 / Dec. 2006

11

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

2. BUS OPERATION

There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,

Data Output, Write Protect, and Standby.

Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not

affect bus operations.

2.1 Command Input.

Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip

Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising

edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin

must be high. See figure 5 and table 12 for details of the timings requirements. Command codes are always applied on

IO7:0, disregarding the bus configuration (X8).

2.2 Address Input.

Address Input bus operation allows the insertion of the memory address. To insert the 30⁽¹⁾addresses needed to

access the 8Gbit 5 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High,

Command Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for com-

mands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 12 for

details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8).

2.3 Data Input.

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and

timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command

Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure

7 and table 12 for details of the timings requirements.

2.4 Data Output.

Data Output bus operation allows to read data from the memory array and to check the status register content, the ID

data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address

Latch Enable low, and Command Latch Enable low. See figures 8,10,11 and table 12 for details of the timings require-

ments.

2.5 Write Protect.

Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not

start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-

tection even during the power up.

2.6 Standby.

In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.

NOTE:

1. 29 addresses are needed to access HY27UG088G5M & HY27UG088GDM.

Rev. 0.6 / Dec. 2006

12

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3. DEVICE OPERATION

3.1 Page Read.

Page read operation is initiated by writing 00h and 30h to the command register along with five address cycles. In two

consecutive read operations, the second one doesn’t’ need 00h command, which five address cycles and 30h com-

mand initiates that operation. Two types of operations are available : random read, serial page read. The random read

mode is enabled when the page address is changed. The 2112 bytes (X8 device) of data within the selected page are

transferred to the data registers in less than 25us(tR). The system controller may detect the completion of this data

transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be

read out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the

device output the data starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data out-

put command.

The column address of next data, which is going to be out, may be changed to the address which follows random data

output command.

Random data output can be operated multiple times regardless of how many times it is done in a page.

3.2 Page Program.

The device is programmed basically by page, but it does allow multiple partial page programming of a word or consec-

utive bytes up to 2112 (X8 device) , in a single page program cycle. The number of consecutive partial page program-

ming operation within the same page without an intervening erase operation must not exceed 4 times for main array

(X8 device:1time/512byte) and 4 times for spare array (X8 device:1time/16byte).

The addressing should be done in sequential order in a block ¹. A page program cycle consists of a serial data

loading period in which up to 2112bytes (X8 device) or 1056words (X16 device) of data may be loaded into the data

register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate

cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle

address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The

device supports random data input in a page. The column address of next data, which will be entered, may be

changed to the address which follows random data input command (85h). Random data input may be operated multi-

ple times regardless of how many times it is done in a page.

The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously

entering the serial data will not initiate the programming process. The internal write state controller automatically exe-

cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other

tasks. Once the program process starts, the Read Status Register command may be entered to read the status register.

The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/

O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in

progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify

detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Sta-

tus command mode until another valid command is written to the command register. Figure 14 details the sequence.

Rev. 0.6 / Dec. 2006

13

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3.3 Block Erase.

The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an

Erase Setup command (60h). Only address A18 to A29 (X8) is valid while A12 to A17 (X8) is ignored. The Erase Con-

firm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence

of setup followed by execution command ensures that memory contents are not accidentally erased due to external

noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles

erase and erase-verify. Once the erase process starts, the Read Status Register command may be entered to read the

status register. The system controller can detect the completion of an erase by monitoring the R/B output, or the Sta-

tus bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while erasing is in

progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked.

Figure 19 details the sequence.

Rev. 0.6 / Dec. 2006

14

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3.4 Copy-Back Program.

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an

external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system per-

formance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block

also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a

sequential execution of page-read without serial access and copying-program with the address of destination page. A

read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) data

into the internal data buffer. As soon as the device returns to Ready state, Copy Back command (85h) with the address

cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin the pro-

gramming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed

as shown in Figure 16.

"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if

Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external

error detection/correction scheme. For this reason, two bit error correction is recommended for the use

of Copy-Back operation."

Figure 16 shows the command sequence for the copy-back operation.

The Copy Back Program operation requires three steps:

1. The source page must be read using the Read A command (one bus write cycle to setup the command and then

5 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page

Buffer.

2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is

given with the 5bus cycles to input the target page address. A29 must be the same for the Source and Target Pages.

3. Then the confirm command is issued to start the P/E/R Controller.

NOTE:

1. Copy-Back Program operation is allowed only within the same memory plane.

2. On the same plane, It’s prohibited to operate copy-back program from an odd address page (source page) to an

even address page (target page) or from an even address page (source page) to an odd address page (target page).

Therefore, the copy-back program is permitted just between odd address pages or even address pages.

Rev. 0.6 / Dec. 2006

15

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3.5 Read Status Register.

The device contains a Status Register which may be read to find out whether read, program or erase operation is com-

pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-

mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,

whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory

connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer

to table 13 for specific Status Register definitions. The command register remains in Status Read mode until further

commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command

(00h) should be given before starting read cycles. See figure 10 for details of the Read Status operation.

3.6 Read ID.

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an

address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd

cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued

to it. Figure 20 shows the operation sequence, while tables 15 explain the byte meaning.

3.7 Reset.

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state

during random read, program or erase mode, the reset operation will abort these operations. The contents of memory

cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is

cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to table

13 for device status after reset operation. If the device is already in reset state a new reset command will not be

accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer

to figure 25.

Rev. 0.6 / Dec. 2006

16

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3.8 Cache Program.

Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) data registers, and is

available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while

data stored in data register are programmed into memory cell. After writing the first set of data up to 2112byte (X8

device) or 1056word (X16 device) into the selected cache registers, Cache Program command (15h) instead of actual

Page Program (10h) is input to make cache registers free and to start internal program operation. To transfer data

from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its

cache registers ready for the next data-input while the internal programming gets started with the data loaded into

data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling

the Cache-Busy status bit (I/O 6). Pass/fail status of only the previous page is available upon the return to Ready

state. When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of

pending internal programming. The programming of the cache registers is initiated only when the pending program

cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5)

for internal Ready/Busy may be polled to identify the completion of internal programming.

If the system monitors the progress of programming only with R/B, the last page of the target programming sequence

must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used

instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting

other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous

page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready

(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is

checked. See figure 18 for more details.

NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program.

However, if the previous program cycle with the cache data has not finished, the actual program cycle of the

last page is initiated only after completion of the previous cycle, which can be expressed as the following

formula.

tPROG= Program time for the last page+ Program time for the ( last -1 )th page -

(Program command cycle time + Last page data loading time)

The value for A29 from second to the last page address must be same as the value given to A29 in first address.

Rev. 0.6 / Dec. 2006

17

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3.9 Cache Read

Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st

latency end, while user can start reading out data, device internally starts reading following page.

Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will

be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device.

Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache

read) user can check operation status using :

- R/B ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device

internally is active on n+1 page

- Status register (SR<6> behave like R/B, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)

To exit cache read operation a cache read exit command (34h) must be issued. this command can be given any time

(both device idle and reading).

If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time

shorter then tRBSY before becoming again idle and ready to accept any further commands.

If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command.

Random data output is not available in cache read.

Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.

Rev. 0.6 / Dec. 2006

18

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

4. OTHER FEATURES

4.1 Data Protection & Power on/off Sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal

voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware pro-

tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is

required before internal circuit gets ready for any command sequences as shown in Figure 26. The two-step command

sequence for program/erase provides additional software protection.

If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed

the data. Power protection function is only available during the power on/off sequence.

4.2 Ready/Busy.

The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,

copy-back, cache program and random read completion. The R/B pin is normally high and goes to low when the device

is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has finished the

operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up

resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with

the following reference chart (Fig 27). Its value can be determined by the following guidance.

Rev. 0.6 / Dec. 2006

19

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Parameter

Symbol

Min

Typ

Max

Unit

Valid Block Number

NVB

8032

8192

Blocks

Table 6: Valid Blocks Number

NOTE:

1. The 1st block is guaranteed to be a valid block up to 1K cycles with ECC. (1bit/512bytes)

Value

3.3V

Symbol

Parameter

Unit

Ambient Operating Temperature (Commercial Temperature Range)

Ambient Operating Temperature (Extended Temperature Range)

Ambient Operating Temperature (Industry Temperature Range)

Temperature Under Bias

0 to 70

℃

V

TA

-25 to 85

-40 to 85

-50 to 125

-65 to 150

-0.6 to 4.6

TBIAS

TSTG

Storage Temperature

(2)

Input or Output Voltage

VIO

Vcc

Supply Voltage

V

Table 7: Absolute maximum ratings

NOTE:

1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute

Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of

the device at these or any other conditions above those indicated in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.

Rev. 0.6 / Dec. 2006

20

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

$ꢀꢅꢄaꢄ$ꢅ

$''5(66

5(*,67(5ꢃ

&2817(5

352*5$0

(5$6(

;

&21752//(5

+9ꢄ*(1(5$7,21

ꢃꢄꢅꢆꢇ0ELWꢇꢈꢇꢆꢉꢊ0ELW

'

(

1$1'ꢇ)ODVK

0(025<ꢇ$55$<

&

2

'

(

$/(

&/(

:(

5

&(

:3

&200$1'

,17(5)$&(

/2*,&

5(

3$*(ꢄ%8))(5

<ꢄ'(&2'(5

&200$1'

5(*,67(5

'$7$

5(*,67(5

%8))(56

,2

Figure 4: Block Diagram

Rev. 0.6 / Dec. 2006

21

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3.3Volt

Unit

Parameter

Sequential

Symbol

Test Conditions

Min

Typ

Max

tRC=30ns

CE=VIL, IOUT=0mA

ICC1

-

15

30

mA

Read

Operating

Current

Program

Erase

ICC2

ICC3

-

15

30

mA

CE=VIH,

WP=0V/Vcc

Stand-by Current (TTL)

Stand-by Current (CMOS)

ICC4

ICC5

-

1

mA

uA

CE=Vcc-0.2,

WP=0V/Vcc

20

100

Single & 2CE

-

uA

V

± 20

± 10

± 20

± 10

Vcc+0.3

Vccx0.2

-

VIN=0 to Vcc

Input Leakage Current

Output Leakage Current

ILI

(max)

Dual

Single & 2CE

Dual

-

VOUT =0 to Vcc

(max)

ILO

-

Vccx0.8

-0.3

2.4

Input High Voltage

VIH

VIL

-

Input Low Voltage

V

Output High Voltage Level

Output Low Voltage Level

VOH

VOL

IOH=-400uA

V

IOL=2.1mA

VOL=0.4V

-

0.4

V

IOL

(R/B)

Output Low Current (R/B)

8

10

-

mA

Table 8: DC and Operating Characteristics

Value

Parameter

3.3Volt

0V to Vcc

5ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

Output Load (2.7V - 3.3V)

Output Load (3.0 - 3.6V)

Vcc/2

1 TTL GATE and CL=50pF

1 TTLGATE and CL=100pF

Table 9: AC Conditions

Rev. 0.6 / Dec. 2006

22

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Max

HY27UG088G5M-T(P)

Test

Condition

Item

Symbol

Min

Unit

HY27UG088GDM-UP

Input / Output

Capacitance

CI/O

CIN

VIL=0V

VIN=0V

-

20

15

pF

Input Capacitance

Table 10: Pin Capacitance (TA=25C, F=1.0MHz)

Parameter

Symbol

tPROG

tCBSY

tRBSY

NOP

Min

Typ Max

Unit

us

Program Time

-

200

700

-

Dummy Busy Time for Cache Program

Dummy Busy Time for Cache Read

3

5

-

us

Main Array

Spare Array

4

Cycles

ms

Number of partial Program Cycles in the same page

Block Erase Time

NOP

-

4

tBERS

2

3

Table 11: Program / Erase Characteristics

Rev. 0.6 / Dec. 2006

23

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

3.3Volt

Unit

Parameter

Symbol

Min

15

5

Max

CLE Setup time

CLE Hold time

CE setup time

CE hold time

tCLS

tCLH

tCS

ns

us

ns

25

5

tCH

WE pulse width

ALE setup time

ALE hold time

Data setup time

Data hold time

Write Cycle time

WE High hold time

tWP

15

5

tALS

tALH

tDS

15

5

tDH

tWC

tWH

tADL⁽²⁾

tR

30

10

100

Address to Data Loading Time

Data Transfer from Cell to register

ALE to RE Delay

25

tAR

15

20

15

CLE to RE Delay

tCLR

tRR

Ready to RE Low

RE Pulse Width

tRP

WE High to Busy

tWB

tRC

100

Read Cycle Time

30

RE Access Time

tREA

tRHZ

tCHZ

tCRRH

tRHOH

tRLOH

tCOH

tREH

tIR

25

50

RE High to Output High Z

CE High to Output High Z

Cache read RE High

RE High to Output Hold

RE Low to Output Hold

CE High to Output Hold

RE High Hold Time

100

15

5

15

10

0

Output High Z to RE low

CE Access Time

tCEA

tWHR

30

WE High to RE low

60

Device Resetting Time

(Read / Program / Copy-Back Program / Erase)

5/10/40/500⁽¹⁾

tRST

us

ns

tWW⁽³⁾

Write Protection time

100

Table 12: AC Timing Characteristics

NOTE:

1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us

2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

3. Program / Erase Enable Operation : WP high to WE High.

Program / Erase Disable Operation : WP Low to WE High.

Rev. 0.6 / Dec. 2006

24

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Page

Program

Block

Erase

Cache

Program

Cache

CODING

Read

IO

Read

0

Pass / Fail

Pass / Fail (N)

NA

Pass: ‘0’ Fail: ‘1’

(Only for Cache Program,

else Don’t care)

1

NA

Pass / Fail (N-1)

NA

2

3

4

NA

-

P/E/R

Controller Bit

P/E/R

5

6

7

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Active: ‘0’ Idle: ‘1’

Controller Bit

Cache Register

Free

Ready/Busy

Busy: ‘0’ Ready’: ‘1’

Protected: ‘0’

Not Protected: ‘1’

Write Protect

Table 13: Status Register Coding

DEVICE IDENTIFIER CYCLE

DESCRIPTION

1st

2nd

3rd

4th

Manufacturer Code

Device Identifier

Internal chip number, cell Type, Number of Simultaneously Programmed pages.

Page Size, Block Size, Spare Size, Organization

Table 14: Device Identifier Coding

Bus

Width

1st cycle

2nd cycle

Part Number

Voltage

3rd Cycle 4th Cycle

(Manufacture Code) (Device Code)

HY27UG088G5M

HY27UG088GDM

3.3V

x8

ADh

DCh

80h

95h

Table 15: Read ID Data Table

Rev. 0.6 / Dec. 2006

25

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Description

IO7

IO6

IO5 IO4

IO3 IO2

IO1 IO0

1

2

4

8

0 0

0 1

1 0

1 1

Internal Chip Number

Cell Type

2 Level Cell

4 Level Cell

8 Level Cell

16 Level Cell

0 0

0 1

1 0

1 1

1

2

4

8

0 0

0 1

1 0

1 1

Number of

Simultaneously

Programmed Pages

Interleave Program

Between multiple chips

Not Support

Support

0

1

Not Support

Support

0

1

Cache Program

Table 16: 3rd Byte of Device Idendifier Description

Description

IO7

IO6

IO5-4

IO3

IO2

IO1-0

1K

2K

Reserved

0 0

0 1

1 0

1 1

Page Size

(Without Spare Area)

Spare Area Size

(Byte / 512Byte)

8

16

0

1

50ns/30ns

25ns

Reserved

0

1

0

1

0

1

Serial Access Time

64K

128K

256K

Reserved

0 0

0 1

1 0

1 1

Block Size

(Without Spare Area)

X8

X16

0

1

Organization

Table 17: 4th Byte of Device Identifier Description

Rev. 0.6 / Dec. 2006

26

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

W&/

6

W&/+

W&+

&/(

W&6

&(

W:3

:(

W$/6

W$/+

$/(

W'6

W'+

,ꢃ2ꢄ[

&RPPDQG

Figure 5: Command Latch Cycle

W&/6

W&6

&/(

W:&

&(

W:3

:(

W:+

W$/6

W$/+

W$/6

W$/+

W'+

$/(

W'+

W'6

,ꢂ2[

&ROꢆꢄ$GGꢇ

&ROꢆꢄ$GGꢈ

5RZꢄ$GGꢇ

5RZꢄ$GGꢈ

5RZꢄ$GGꢀ

Figure 6: Address Latch Cycle

Rev. 0.6 / Dec. 2006

27

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

W&/+

W&+

&/(

&(

W:&

$/(

W$/6

W:3

:(

W:+

W'+

',1ꢀꢂ

W'6

',1ꢀꢁ

,ꢅ2[

',1ꢀILQDOꢃ

1RWHVꢆꢀ',1ꢋILQDOꢋPHDQVꢋꢁꢌꢂꢂꢁ

Figure 7. Input Data Latch Cycle

Rev. 0.6 / Dec. 2006

28

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

W5&

&(

5(

W&+=

W5(+

W5($

W&2+

W5+=

W5+2+

,ꢃ2[

5ꢃ%

'RXW

W55

1RWHVꢉꢄ7UDQVLWLRQꢄLVꢄPHDVXUHGꢄꢊꢃꢋꢈꢅꢅP9ꢄIURPꢄVWHDG\ꢄVWDWHꢄYROWDJHꢄZLWKꢄORDGꢆ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ7KLVꢄSDUDPHWHUꢄLVꢄVDPSOHGꢄDQGꢄQRWꢄꢇꢅꢅꢌꢄWHVWHGꢆꢄꢍW&+=ꢎꢄW5+=ꢏ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5/2+ꢄLVꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄKLJKHUꢄWKDQꢄꢀꢀ0+]ꢆ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5+2+ꢄVWDUWVꢄWRꢄEHꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄORZHUꢄWKDQꢄꢀꢀ0+]ꢆ

Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)

&(

5(

W5&

W&+=

W&2+

W53

W5(+

W5+=

W5($

W&($

W5($

W5/2+

W5+2+

,ꢃ2[

5ꢃ%

'RXW

W55

1RWHVꢉꢄ7UDQVLWLRQꢄLVꢄPHDVXUHGꢄꢊꢃꢋꢈꢅꢅP9ꢄIURPꢄVWHDG\ꢄVWDWHꢄYROWDJHꢄZLWKꢄORDGꢆ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ7KLVꢄSDUDPHWHUꢄLVꢄVDPSOHGꢄDQGꢄQRWꢄꢇꢅꢅꢌꢄWHVWHGꢆꢄꢍW&+=ꢎꢄW5+=ꢏ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5/2+ꢄLVꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄKLJKHUꢄWKDQꢄꢀꢀ0+]ꢆ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5+2+ꢄVWDUWVꢄWRꢄEHꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄORZHUꢄWKDQꢄꢀꢀ0+]ꢆ

Figure 9: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L)

Rev. 0.6 / Dec. 2006

29

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

W&/5

&/(

&(

W&/6

W&6

W&/+

W&+

W:3

:(

W&+=

W&2+

W&($

W:+5

5(

W5+=

W5+2+

W'+

W5($

W'6

W,5

,ꢅ2[

ꢄꢁKꢀRUꢀꢄ%K

6WDWXVꢀ2XWSXW

Figure 10: Status Read Cycle

W

&/5

&/(

&(

W

:&

:(

$/(

W

:%

W

$5

W

5+=

W

5

W

5&

5(

W

55

ꢅꢅK

&ROꢆ$GGꢇ

&ROꢆ$GGꢈ 5RZꢄ$GGꢇ 5RZꢄ$GGꢈ 5RZꢄ$GGꢀ

ꢀꢅK

'RXWꢀ1

'RXWꢀ1ꢅꢂ

'RXWꢀ0

,ꢅ2[

&ROXPQꢋ$GGUHVV

5RZꢋ$GGUHVV

%XV\

5ꢅ%

Figure 11: Read1 Operation (Read One Page)

Rev. 0.6 / Dec. 2006

30

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

:(

W:%

W&+=

W$5

W&2+

$/(

5(

W5

W5&

W55

'RXW

1

'RXW

1ꢊꢇ

'RXW

1ꢊꢈ

&ROꢆ

5RZ

ꢅꢅK

ꢀꢅK

,ꢃ2[

5ꢃ%

$GGꢇ

$GGꢈ

$GGꢇ

$GGꢈ

$GGꢀ

&ROXPQꢄ$GGUHVV

5RZꢄ$GGUHVV

%XV\

Figure 12: Read1 Operation intercepted by CE

Rev. 0.6 / Dec. 2006

31

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Figure 13 : Random Data output

Rev. 0.6 / Dec. 2006

32

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

W:&

:(

W$'/

W:%

W352*

$/(

5(

&ROꢇ

5RZ

'LQ

1

'LQ

0

,ꢂ2[

ꢂꢁK

ꢄꢁK

,ꢊ2R

ꢆꢁK

$GGꢂ

$GGꢈ

$GGꢂ

$GGꢈ

$GGꢉ

6HULDOꢋ'DWD

3URJUDP

5HDGꢋ6WDWXV

&RPPDQG

ꢂꢋXSꢋWRꢋPꢋ%\WH

&ROXPQꢋ$GGUHVV

5RZꢋ$GGUHVV

,QSXWꢋ&RPPDQG

6HULDOꢋ,QSXW

&RPPDQG

5ꢂ%

,ꢀ2R ꢈꢋ6XFFHVVIXOꢋ3URJUDP

,ꢀ2R ꢂꢋ(UURUꢋLQꢋ3URJUDP

Figure 14: Page Program Operation

Rev. 0.6 / Dec. 2006

33

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Figure 15 : Random Data In

Rev. 0.6 / Dec. 2006

34

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Figure 16 : Copy Back Program

Rev. 0.6 / Dec. 2006

35

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

&/(

$/(

:(

ꢈꢈK

$GGꢂ $GGꢁ $GGꢇ $GGꢆ $GGꢅ

ꢇꢂK

'ꢈ

'ꢂ

'ꢁ

'ꢇ

'ꢆ

'ꢁꢂꢂꢈ

'ꢁꢂꢂꢂ

'ꢈ

'ꢂ

'ꢁ

,ꢀ2;

5ꢀ%

W&55+

5(

5HDGꢋꢂVWꢋSDJH

5HDGꢋꢁQGꢋSDJH

Figure 17: Cache Read RE high

Rev. 0.6 / Dec. 2006

36

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Figure 18 : Cache Program

Rev. 0.6 / Dec. 2006

37

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

W:&

:(

W:%

W%(56

$/(

5(

5RZ

,ꢂ2

[

ꢂꢅK

'ꢅK

ꢁꢅK

,ꢃ2ꢅ

$GGꢇ

$GGꢈ $GGꢀ

5RZꢄ$GGUHVV

5ꢂ%

%86<

(UDVHꢄ&RPPDQG

5HDGꢄ6WDWXV ,ꢃ2ꢅ ꢅꢄ6XFFHVVIXOꢄ(UDVH

$XWRꢄ%ORFNꢄ(UDVH

6HWXSꢄ&RPPDQG

&RPPDQG

,ꢃ2ꢅ ꢇꢄ(UURUꢄLQꢄ(UDVH

Figure19: Block Erase Operation (Erase One Block)

&/(

&(

:(

W$5ꢄꢄ

$/(

5(

W5($ꢄꢄ

'ꢀK

&ꢇK

ꢓꢐK

ꢓꢅK

ꢅꢅK

$'K

,ꢃ2ꢄ[

5HDGꢄ,'ꢄ&RPPDQG $GGUHVVꢄꢇꢄF\FOH

0DNHUꢄ&RGH 'HYLFHꢄ&RGH

ꢀUGꢄ&\FOH

ꢔWKꢄ&\FOH

Figure 20: Read ID Operation

Rev. 0.6 / Dec. 2006

38

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

&/(

$/(

:(ꢍ

'ꢅ

'ꢇ 'ꢈ 'ꢀ 'ꢔ

'ꢁK $GGꢂ $GGꢈ $GGꢉ $GGꢋ $GGꢌ ꢉꢂK

ꢈꢇꢇꢇ

'ꢅ 'ꢇ 'ꢈ 'ꢀ 'ꢔ

ꢈꢇꢇꢇ

'ꢅ

'ꢇ 'ꢈ

ꢀꢂV

5(ꢋ

5HDGꢄꢀUGꢄSDJH

5HDGꢄꢔWKꢄSDJH

5HDGꢄꢇVWꢄSDJH 5HDGꢄꢈQGꢄSDJH

,GOH

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ꢀꢁV

ꢃꢂꢂV

6WDWXVꢋ5HJLVWHU

65ꢋꢎꢋꢅꢏꢄꢋ!

ꢈꢈ

ꢈꢂ

ꢂꢂ

ꢈꢂ

ꢂꢂ

ꢈꢂ

Figure 21: start address at page start :after 1st latency uninterrupted data flow

&/(

8VHUꢋFDQ

$/(

KHUHꢋILQLVK

UHDGLQJꢋ1

SDJH

:(ꢋꢋ

'ꢁ 'ꢂ 'ꢈ 'ꢉ 'ꢋ

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1ꢐꢁꢋSDJH

FDQQRWꢋEH

UHDG

QꢅꢂꢀSDJH

QꢀSDJH

5(ꢋꢋꢋ

ꢌVꢀꢍW5%6<

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5HDGꢀQꢅꢂꢀSDJH

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65ꢋꢎꢋꢅꢏꢄꢋ!

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ꢂꢂ

Figure 22: exit from cache read in 5us when device internally is reading

Rev. 0.6 / Dec. 2006

39

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

System Interface Using CE don’t care

To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.

So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND

Flash to make CE don’t care read operation was disabling of the automatic sequential read function.

&/(

&(ꢄGRQ¶WꢋFDUH

&(

:(

$/(

ꢑꢅK

6WDUWꢄ$GGꢆꢍꢐ&\FOHꢏ

'DWDꢄ,QSXW

ꢇꢅK

,ꢂ2[

Figure 23: Program Operation with CE don’t-care.

&/(

&(

,IꢄVHTXHQWLDOꢄURZꢄUHDGꢄHQDEOHGꢎ

&(ꢄPXVWꢄEHꢄKHOGꢄORZꢄGXULQJꢄW5ꢆ

&(ꢄGRQ¶WꢋFDUH

5(

$/(

5ꢃ%

W5

:(

,ꢃ2[

ꢅꢅK

6WDUWꢄ$GGꢆꢍꢐ&\FOHꢏ

ꢀꢅK

'DWDꢄ2XWSXWꢍVHTXHQWLDOꢏ

Figure 24: Read Operation with CE don’t-care.

Rev. 0.6 / Dec. 2006

40

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

:(

$/(

&/(

5(

,2[

5%

))K

W

567

Figure 25: Reset Operation

9FF

97+

W

:3

:(

ꢁꢈXV

Figure 26: Power On and Data Protection Timing

VTH = 2.5 Volt for 3.3 Volt Supply devices

Rev. 0.6 / Dec. 2006

41

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

5S

LEXV\

9FF

5HDG\

9FF

5ꢀ%

RSHQꢋGUDLQꢋRXWSXW

92+

&/

92/

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/

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/

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5SꢍPD[ꢏꢄLVꢄGHWHUPLQHGꢄE\ꢄPD[LPXPꢄSHUPLVVLEOHꢄOLPLWꢄRIꢄWU

Figure 27: Ready/Busy Pin electrical specifications

Rev. 0.6 / Dec. 2006

42

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

wG]Z

wGZX

wG]Z

wGZX

O][P

a

OZYP

a

OXP

a

wGY

wGX

wGW

wGY

wGX

wGW

OZP

OYP

OXP

OZP

OZYP

OXP

kG

mGGsziGGGtziG

kh{hGpuGaGkGOXP kGO][P

lUPGyGGGOwP

kh{hGpuGaGkGOXP kGO][P

Figure 28 : page programming within a block

Rev. 0.6 / Dec. 2006

43

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Bad Block Management

Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the

blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and

common source line by a select transistor. The devices are supplied with all the locations inside valid blocks

erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of

the 1st or 2nd page(if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be

read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-

nize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flow-

chart shown in Figure 29. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.

Bad Replacement

Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying

the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give

errors in the Status Register.

As the failure of a page program operation does not affect the data in other pages in the same block, the block can be

replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.

The Copy Back Program command can be used to copy the data to a valid block.

See the “Copy Back Program” section for more details.

Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation.

Operation

Erase

Recommended Procedure

Block Replacement

Program

Read

Block Replacement or ECC (with 1bit/512byte)

ECC (with 1bit/512byte)

Table 18: Block Failure

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1R

<HV

/DVW

EORFN"

<HV

(1'

Figure 29: Bad Block Management Flowchart

Rev. 0.6 / Dec. 2006

44

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

Write Protect Operation

The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations

are enabled and disabled as follows (Figure 30~33)

:(

W

::

ꢉꢈK

,ꢀ2[

ꢂꢈK

5ꢀ%

Figure 30: Enable Programming

:(

W

::

ꢉꢈK

ꢂꢈK

,ꢀ2[

5ꢀ%

Figure 31: Disable Programming

Rev. 0.6 / Dec. 2006

45

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

:(

W

::

ꢄꢈK

'ꢈK

,ꢀ2[

5ꢀ%

Figure 32: Enable Erasing

:(

W

::

ꢄꢈK

,ꢀ2[

'ꢈK

5ꢀ%

Figure 33: Disable Erasing

Rev. 0.6 / Dec. 2006

46

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

5. APPENDIX : Extra Features

5.1 Addressing for program operation

Within a block, the pages must be programmed consecutively from LSB (least significant bit) page of the block to MSB

(most significant bit) page of the block. Random address programming is prohibited. See Fig. 34.

5.2 Stacked Devices Access

A small logic inside the devices allows the possibility to stack up to 2 devices in a single package without changing the

pinout of the memory. To do this the internal address register can store up to 30⁽¹⁾addresses(512Mbyte addressing

field) and basing on the 2 MSB pattern each device inside the package can decide if remain active (1 over 4 ) or “hang

up” the connection entering the Stand-By.

Rev. 0.6 / Dec. 2006

47

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

ꢆꢉ

H

$ꢁ

$

'

%

/

Į

$ꢂ

ꢁꢆ

ꢁꢅ

',(

(ꢂ

(

&

&3

Figure 34. 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

millimeters

Symbol

Min

Typ

Max

1.200

0.150

1.030

0.250

0.200

0.100

12.120

20.100

18.500

A

A1

A2

B

0.050

0.980

0.170

0.100

C

CP

D

11.910

19.900

18.300

12.000

20.000

18.400

0.500

E

E1

e

L

0.500

0

0.680

5

alpha

Table 19: 48-TSOP1 - 48-lead Plastic Thin Small Outline,

12 x 20mm, Package Mechanical Data

Rev. 0.6 / Dec. 2006

48

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

%

%ꢂ

%ꢁ

' 'ꢂ

&ꢁ

&ꢂ

&

$ꢁ $ꢂ

$

FSꢂ

ꢈꢑꢂ

FSꢁ

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0

&

$%

0

&

$%

(

Figure 35. 51-ULGA, 12 x 17mm, Package Outline

(Top view through package)

millimeters

Symbol

Min

Typ

17.00

13.00

12.00

10.00

6.00

Max

A

A1

A2

B

16.90

17.10

11.90

12.10

B1

B2

C

1.00

C1

C2

D

1.50

2.00

1.00

D1

E

1.00

0.55

0.65

0.95

0.60

0.65

0.75

1.05

CP1

CP2

0.70

1.00

Table 20: 52-ULGA, 12 x 17mm, Package Mechanical Data

Rev. 0.6 / Dec. 2006

49

HY27UG088G(5/D)M Series

8Gbit (1Gx8bit) NAND Flash

MARKING INFORMATION- TSOP1/ULGA

Packag

Marking Exam ple

K

G

O

x

R

TSOP1

H

x

Y

x

2

x

7

x

G

x

8

M

/

ULGA

Y

W

x

- hynix

- KOR

: Hynix Symbol

: Origin Country

: Part Number

- HY27xGxx8GxM xxxx

HY: Hynix

27: NAND Flash

x: Power Supply

G: Classification

xx: Bit Organization

8G: Density

: U(2.7V~3.6V)

: Single Level Cell+Double Die+Large Block

: 08(x8)

: 8Gbit

: 5(2nCE & 2R/nB; Sequential Row Read Disable)

: D(Dual interface; Sequential Row Read Disable)

: 1st Generation

x: Mode

M: Version

: T(48-TSOP1), U(52-ULGA)

: Blank(Normal), P(Lead Free)

: C(0℃ ~70℃ ), E(-25℃ ~85℃ )

M(-30℃ ~85℃ ), I(-40℃ ~85℃ )

: B(Included Bad Block), S(1~5 Bad Block),

P(All Good Block)

x: Package Type

x: Package Material

x: Operating Temperature

x: Bad Block

- Y: Year (ex: 5=year 2005, 06= year 2006)

- ww: Work Week (ex: 12= work week 12)

- xx: Process Code

Note

: Fixed Item

- Capital Letter

- Sm all Letter

: Non-fixed Item

Rev. 0.6 / Dec. 2006

50


型号：	HY27UG088G5M-TMS
厂家：	HYNIX SEMICONDUCTOR
描述：	Flash, 1GX8, 25ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, PLASTIC, TSOP1-48 光电二极管
文件：	总50页 (文件大小：338K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY27UG088G5M-TMS [HYNIX]

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