HY27UG088GDB-UPIB_技术文档

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

8Gb NAND FLASH

HY27UG088G(5/D)B

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.2 / Jan. 2008

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Document Title

8Gbit (1Gx8bit) NAND Flash Memory

Revision History

Revision No.

History

Draft Date

Remark

0.0

Jun. 22. 2007 Preliminary

Jun. 27. 2007 Preliminary

Jan. 15. 2008

Initial Draft.

1) Correct Read Cache figure

2) Add ULGA package

0.1

0.2

3) Correct Block erase

1) Delete Preliminary

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES

STATUS REGISTER

- Cost effective solutions for mass storage applications

- Normal Status Register (Read/Program/Erase)

- Extended Status Register (EDC)

MULTIPLANE ARCHITECTURE

- Array is split into two independent planes. Parallel

Operations on both planes are available, halving

Program and erase time.

ELECTRONIC SIGNATURE

- 1st cycle : Manufacturer Code

- 2nd cycle : Device Code

- 3rd cycle : Internal chip number, Cell Type, Number of

Simultaneously Programmed Pages.

- 4th cycle : Page size, Block size, Organization, Spare

size

NAND INTERFACE

- x8 bus width.

- Address/ Data Multiplexing

- Pinout compatiblity for all densities

- 5th cycle : Multiplane information

SUPPLY VOLTAGE

CHIP ENABLE DON’T CARE

- 3.3V device : Vcc = 2.7 V ~3.6 V

- Simple interface with microcontroller

MEMORY CELL ARRAY

HARDWARE DATA PROTECTION

- x8 : (2K + 64) bytes x 64 pages x 8192 blocks

- Program/Erase locked during Power transitions.

PAGE SIZE

DATA RETENTION

- (2K + 64 spare) Bytes

- 100,000 Program/Erase cycles (with 1bit/528byte ECC)

- 10 years Data Retention

BLOCK SIZE

- (128K + 4Kspare) Bytes

PACKAGE

- HY27UG088G5B-T(P)

PAGE READ / PROGRAM

: 48-Pin TSOP1 (12 x 20 x 1.2 mm)

- HY27UG088G5B-T (Lead)

- HY27UG088G5B-TP (Lead Free)

- Random access : 25us (max.)

- Sequential access : 25ns (min.)

- Page program time : 200us (typ.)

- Multi-page program time (2 pages) : 200us (Typ)

- HY27UG088GDB-UP

: 52-ULGA (12 x 17 x 0.65 mm)

- HY27UG088GDB-UP (Lead Free)

COPY BACK PROGRAM

- Automatic block download without latency time

FAST BLOCK ERASE

- Block erase time: 1.5ms (Typ)

- Multi-block erase time (2 blocks) : 1.5ms (Typ)

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

1.SUMMARY DESCRIPTION

Hynix NAND HY27UG088G(5/D)B Series have 1024Mx8bit with spare 32Mx8 bit capacity. The device is offered in 3.3 Vcc

Power Supply, and with x8 I/O interface Its NAND cell provides the most cost-effective solution for the solid state mass

storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data

while old data is erased.

The device contains 8192 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typi-

cal 200us and an erase operation can be performed in typical 1.5ms on a 128K-byte block.

Data in the page can be read out at 25ns cycle time per byte(x8). The I/O pins serve as the ports for address and data

input/output as well as command input.

This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of

footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE ALE and CLE input pin. The

on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where

required, and internal verification and margining of data. The modify operations can be locked using the WP input. The

output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple mem-

ories the R/B pins can be connected all together to provide a global status signal.

The copy back function allows the optimization of defective blocks management. when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase. Copy back operation automatically executes embedded error detection operation: 1 bit error

every 528byte (x8) can be detected. Due to this feature, it is no more nor necessary nor recommended to use external 2-

bit ECC to detect copy back operation errors. Data read out after copy back read (both for single and multiplane cases) is

allowed.

Even the write-intensive systems can take advantage of the HY27UG088G(5/D)B Series extended reliability of 100K pro-

gram/erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE

don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a micro-

controller, since the CE transitions do not stop the read operation.

This device includes also extra features like OTP/Unique ID area, Read ID2 extension.

The HY27UG088G(5/D)B Series are available in 48-TSOP1 12 x 20 mm, 52-ULGA 12 x 17mm.

1.1 Product List

PART NUMBER

HY27UG088G5B

HY27UG088GDB

ORGANIZATION

Vcc RANGE

PACKAGE

48-TSOP1

52-ULGA

x8

2.7V ~ 3.6V

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

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Figure1: Logic Diagram

IO7 - IO0

CLE

Data Input / Outputs

Command latch enable

Address latch enable

Chip Enable

ALE

CE1, CE2

RE

Read Enable

WE

Write Enable

WP

Write Protect

R/B1, R/B2

Vcc

Ready / Busy

Power Supply

Vss

Ground

NC

No Connection

Table 1: Signal Names

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

ꢂ

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Figure 2. 48TSOP1 Contact, x8 Device

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

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Figure 3: 52-ULGA Contactions, x8 Device, Dual interface

(Top view through package)

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

1.2 PIN DESCRIPTION

Pin Name

Description

DATA INPUTS/OUTPUTS

The IO pins allow to input command, address and data and to output data during read / program

operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to

High-Z when the device is deselected or the outputs are disabled.

IO0-IO7

COMMAND LATCH ENABLE

CLE

ALE

This input activates the latching of the IO inputs inside the Command Register on the Rising edge of

Write Enable (WE).

ADDRESS LATCH ENABLE

This input activates the latching of the IO inputs inside the Address Register on the Rising edge of

Write Enable (WE).

CHIP ENABLE

CE1, CE2

WE

This input controls the selection of the device. When the device is busy CE1, CE2 low does not deselect

the memory.

WRITE ENABLE

This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise

edge of WE.

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is

valid tREA after the falling edge of RE which also increments the internal column address counter by

one.

RE

WRITE PROTECT

WP

The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)

operations.

READY BUSY

R/B1,R/B2

Vcc

The Ready/Busy output is an Open Drain pin that signals the state of the memory.

SUPPLY VOLTAGE

The Vcc supplies the power for all the operations (Read, Write, Erase).

Vss

NC

GROUND

NO CONNECTION

Table 2: Pin Description

NOTE:

1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple

the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required

during program and erase operations.

2. An internal voltage detector disables all functions whenever VCC is below 1.8V (3.3V version) or 1.1V (1.8V)

version to protect the device from any involuntary program/erase during power transitions.

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

IO0

A0

IO1

A1

IO2

A2

IO3

A3

IO4

IO5

IO6

IO7

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

A4

A5

A6

A7

L⁽¹⁾

A16

A24

L⁽¹⁾

A17

A25

L⁽¹⁾

A18

A26

L⁽¹⁾

A19

A27

A8

A9

A10

A14

A22

A11

A15

A23

A12

A20

A28

A13

A21

A29

L⁽¹⁾

Table 3: Address Cycle Map(x8)

NOTE:

1. L must be set to Low.

Acceptable command

during busy

FUNCTION

1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE

00h

90h

FFh

80h

85h

80h

30h

35h

-

READ FOR COPY-BACK

READ ID

-

RESET

-

Yes

PAGE PROGRAM

COPY BACK PGM

MULTI PLANE PROGRAM

MULTI PLANE COPYBACK

PROGRAM

BLOCK ERASE

10h

11h

-

81h

10h

85h

60h

11h

D0h

60h

81h

-

10h

-

MULTI PLANE

BLOCK ERASE

D0h

READ STATUS REGISTER

RANDOM DATA INPUT

RANDOM DATA OUTPUT

READ CACHE (RANDOM)

70h

85h

05h

00h

31h

3Fh

7Bh

-

Yes

-

E0h

31h

-

READ CACHE (SEQUENTIAL)

READ CACHE END

-

READ EDC STATUS REGISTER

-

Table 4: Command Set

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

CLE

H

L

ALE

L

CE

L

WE

Rising

H

RE

WP

MODE

H

X

Command Input

Read Mode

H

L

H

X

Address Input(5 cycles)

H

L

H

Command Input

Write Mode

H

L

H

Address Input(5 cycles)

L

H

Data Input

L⁽¹⁾

L

Falling

X

Sequential Read and Data Output

During Read (Busy)

During Program (Busy)

During Erase (Busy)

Write Protect

L

H

X

H

X

H

L

X

H

X

0V/Vcc

Stand By

Table 5: Mode Selection

NOTE:

1. With the CE high during latency time does not stop the read operation

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

2. BUS OPERATION

There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,

Data Output, Write Protect, and Standby.

Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not

affect bus operations.

2.1 Command Input.

Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip

Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising

edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be

high. See Figure 5 and Table 12 for details of the timings requirements. Command codes are always applied on IO7:0

regardless of the bus configuration. (x8)

2.2 Address Input.

Address Input bus operation allows the insertion of the memory address. Five cycles are required to input the addresses

for the 8Gbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable

low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify-

ing operation (write/erase) the Write Protect pin must be high. See Figure 6 and Table 12 for details of the timings

requirements. Addresses are always applied on IO7:0 regardless of the bus configuration (x8).

2.3 Data Input.

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serial and timed

by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch

Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 7 and

Table 12 for details of the timings requirements.

2.4 Data Output.

Data Output bus operation allows to read data from the memory array and to check the status register content, the EDC

register content and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low,

Write Enable High, Address Latch Enable low, and Command Latch Enable low. See Figure 8,9,11,12,13 and Table 12

for details of the timings requirements.

2.5 Write Protect.

Hardware Write Protection is activated when the Write Protect pin is low. In this condition modifying operation does not

start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protec-

tion even during the power up.

2.6 Standby

In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

3. DEVICE OPERATION

3.1 Page Read.

This operation is operated by writing 00h and 30h to the command register along with five address cycles.

Two types of operations are available: random read, serial page read. The random read mode is enabled when the

page address is changed. The 2112 bytes (x8) of data within the selected page are transferred to the data registers in

less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output

of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by

sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting

from the selected column address up to the last column address.

The device may output random data in a page instead of the sequential data by writing random data output command.

The column address of next data, which is going to be out, may be changed to the address which follows random data

output command. Random data output can be operated multiple times regardless of how many times it is done in a

page.

3.2 Page Program.

The device is programmed by page. The number of consecutive partial page programming operation within the same

page without an intervening erase operation must not exceed 8 times. The addressing should be done on each pages

in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes of data may be

loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed

into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), fol-

lowed by the five cycle address inputs and then serial data. The bytes other than those to be programmed do not need

to be loaded. The device supports random data input in a page.

The column address of next data, which will be entered, may be changed to the address which follows random data

input command (85h). Random data input may be operated multiple times regardless of how many times it is done in

a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without pre-

viously entering the serial data will not initiate the programming process. The internal write state controller automati-

cally executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for

other tasks. Once the program process starts, the Read Status Register command may be entered to read the status

register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Sta-

tus bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming

is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write

verify detects only errors for "1"s that are not successfully programmed to "0"s.

The command register remains in Read Status command mode until another valid command is written to the com-

mand register. Figure 15 details the sequence.

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

3.3 Multi Plane Program.

Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane.

A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may be

loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed

into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), fol-

lowed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st

plane (A<18>=0). The data of 1st page other than those to be programmed do not need to be loaded. The device

supports random data input exactly like page program operation. The Dummy Page Program Confirm command (11h)

stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h

command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page

must be within 2nd plane (A<18>=1). The data of 2nd page other than those to be programmed do not need to be

loaded. Program Confirm command (10h) makes parallel programming of both pages start. User can check operation

status by R/B pin or read status register command, as if it were a normal page program; status register command is

also available during Dummy Busy time (tDBSY). In case of fail in 1st or 2nd page program, fail bit of status register

will be set: Device supports pass/fail status of each plane. Figure 20 details the sequence.

3.4 Block Erase.

The Erase operation is done on a block basis. Block address loading is accomplished in there cycles initiated by an

Erase Setup command (60h). Only address A18 to A29 is valid while A12 to A17 is ignored (x8). The Erase Confirm

command (D0h) following the block address loading initiates the internal erasing process. This two step sequence of

setup followed by execution command ensures that memory contents are not accidentally erased due to external noise

conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase

and erase verify.

Once the erase process starts, the Read Status Register command may be entered to read the status register.

The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of

the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When

the erase operation is completed, the Write Status Bit (I/O 0) may be checked.

Figure 19 details the sequence.

3.5 Multi Plane Erase.

Multiple plane erase, allows parallel erase of two blocks, one per each memory plane.

Block erase setup command (60h) must be repeated two times, each time followed by 1st block and 2nd block address

respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multiplane erase

does not need any Dummy Busy Time between 1st and 2nd block address insertion. Address limitation required for

multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for mul-

tiple plane program. Figure 21 details the sequence

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

3.6 Copy-back Program

Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page

without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are

removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated

and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequen-

tial execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation

with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data

buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do

not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input com-

mand (85h) with destination page address. Actual programming operation begins after Program Confirm command

(10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read

the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output,

or the Status bit(I/O 6) of the Status Register.

When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 17 & Figure 18). The

command register remains in Read Status command mode until another valid command is written to the command

register. During copy-back program, data modification is possible using random data input command (85h) as shown

in Figure18.

Copy-back program operation is allowed only within same plane.

3.7 Multi-Plane Copy-Back Program

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an

external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system

performance is greatly improved. The benefit is especially obvious when a portion of a block needs to be updated and

the rest of the block also need to be copied to the newly assigned free block.

The operation for performing a copy-back program is a sequential execution of page-read without serial access and

copying-program with the address of destination page. A read operation with "35h" command and the address of the

source page moves the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready

state, optional data read-out is allowed by toggling RE (See Figure 21), or Copy Back command (85h) with the

address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin

the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is

allowed as shown in Figure 22.

Most NAND devices require 2 bit external ECC only due to copy back operation while 1 bit ECC can be enough for all

other operation. Reason is that during read for copy back + copy back program sequence a bit error due to charge

loss is not checked by external error detection/correction scheme. On the contrary, 8Gbit NAND includes automatic

Error Detection Code during copy back operation: thanks to this, 2 bit external ECC is no more required, with signifi-

cant advantage for customers that can always use single bit ECC. More details on EDC operation are available in sec-

tion 3.8.

Rev 0.2 / Jan. 2008

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HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

3.8 EDC Operation

Error Detection Code check automatically starts immediately after device becomes busy for a copy back program opera-

tion (both single and multiple plane). In the x8 version EDC allows detection of 1 single bit error every 528 bytes, where

each 528byte group is compdsed by 512 bytes of main array and 16 bytes of spare area (see Table 20) So described

528byte area is called “EDC unit”.

To Properly use EDC, some limitations apply:

- Random data input can be used only once in copy back program or page program or multiple page program, unless

user inputs data for a whole EDC unit (or more whole EDC units).

- Any page program operation must be done on whole page basis, or on whole EDC unit (s).

EDC result can be checked only during copy back program through 7Bh (specific Read EDC register command, Table 21)

3.9 Read Status Register.

The device contains a Status Register which may be read to find out whether, program or erase operation is completed,

and whether the program or erase operation is completed successfully. After writing 70h command to the command

register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, which-

ever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connec-

tions even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 13

for specific Status Register definitions. The command register remains in Status Read mode until further commands are

issued to it. Therefore, if the status register is read during a random data output, the read command (00h) should be

given before starting read cycles.

3.10 Read EDC Status Register

The operation is available only in copy back program and it allows the detection of errors occurred during read for copy

back. In case of multiple plane copy back, it is not possible to know which of the two read operation caused the error.

After writing 7Bh command to the command register, a read cycle outputs the content of the EDC Register to the I/O

pins on the falling edge of CE or RE, whichever occurs last.

Operation is same read status register command. Refer to below Table 21 for specific EDC Register definitions.

3.11 Read ID.

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an

address input of 00h. Five read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd,

4th, 5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to

it. Figure 23 shows the operation sequence, while tables 14 explain the byte meaning.

3.12 Reset.

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state

during random read, program or erase mode, the reset operation will abort these operations. The contents of memory

cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is

cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table

13 for device status after reset operation. If the device is already in reset state a new reset command will not be

accepted by the command register. The R/B pin goes low for tRST after the Reset command is written. Refer to Figure

26.

Rev 0.2 / Jan. 2008

15

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

3.13 Cache Read

Cache read operation allows automatic download of consecutive pages. Immediately after 1st latency end, while user

can start reading out data, device internally starts reading following page.

Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will

be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device. (50us for

x16device).

The Cache Read function may be issued after the Read function is complete (SR[6] is set to one). The host may enter

the address of the next page to be read from the Flash array. Data output always begins at column address 00h. If

the host does not enter an address to retrieve, the next sequential page is read. When the Cache Read function is

issued, SR[6] is cleared to zero (busy). After the operation is begun SR[6] is set to one (ready) and the host may

begin to read the data from the previous Read or Cache Read function. Issuing an additional Cache Read function

copies the data most recently read from the array into the page register. When no more pages are to be read, the

final page is copied into the page register by issuing the 3Fh command. The host may begin to read data from the

page register when SR[6]is set to one (ready). When the 31h and 3Fh commands are issued, SR[6] shall be cleared

to zero (busy) until the page has finished being copied from the Flash array.

The host shall not issue a sequential Read Cache (31h) command after the last page of the device is read.

Refer to Figure 14.

Cache Read operation must be done only block by block if system needs to avoid reading also reading from invalid

blocks.

Rev 0.2 / Jan. 2008

16

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

4. OTHER FEATURES

4.1 Data Protection & Power On/Off Sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal

voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides hardware pro-

tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is

required before internal circuit gets ready for any command sequences as shown in Figure 26. The two-step command

sequence for program/erase provides additional software protection.

4.2 Ready/Busy.

The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,

copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a

reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The

pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied.

Because pull-up resistor value is related to tR(R/B) and current drain during busy (Ibusy), an appropriate value can be

obtained with the following reference chart (Fig 27). Its value can be determined by the following guidance.

Rev 0.2 / Jan. 2008

17

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Parameter

Symbol

Min

Typ

Max

Unit

Valid Block

Number

NVB

8032

-

8192

Blocks

Table 6 : Valid Blocks Numbers

NOTE:

1. The 1st block is guaranteed to be a valid block at the time of shipment.

2. The number of valid blocks is for single plane & multi-plane operations.

3. Each chip has maximum 80 invalid blocks.

Symbol

Parameter

Value

0 to 70

Unit

℃

Ambient Operating Temperature (Commercial Temperature Range)

Ambient Operating Temperature (Industrial Temperature Range)

Temperature Under Bias

T_A

-40 to 85

-50 to 125

℃

T_BIAS

T_STG

℃

Storage Temperature

Input or Output Voltage

Supply Voltage

-65 to 150

-0.6 to 4.6

V

VIO⁽²⁾

Vcc

V

Table 7: Absolute maximum ratings

NOTE:

1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute

Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of

the device at these or any other conditions above those indicated in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Refer also to the Hynix SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.

Rev 0.2 / Jan. 2008

18

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

$ꢅꢆꢄaꢄ$ꢇ

$''5(66

5(*,67(5ꢃ

&2817(5

352*5$0

(5$6(

;

&21752//(5

+9ꢄ*(1(5$7,21

ꢅꢄꢆꢀꢇ0ELWꢇꢈꢇꢀꢉꢊꢇ0ELW

'

(

1$1'ꢇ)ODVK

0(025<ꢇ$55$<

&

2

'

(

$/(

&/(

:(

5

&(

:3

&200$1'

,17(5)$&(

/2*,&

5(

3$*(ꢄ%8))(5

<ꢄ'(&2'(5

&200$1'

5(*,67(5

'$7$

5(*,67(5

%8))(56

,2

Figure 4: Block Diagram

Rev 0.2 / Jan. 2008

19

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

3.3Volt

Unit

Parameter

Sequential

Symbol

Test Conditions

Min

Typ

Max

tRC=25ns

CE=VIL, IOUT=0mA

ICC1

-

15

30

mA

Read

Operating

Current

Program

Erase

ICC2

ICC3

-

15

30

mA

CE=VIH,

WP=0V/Vcc

Stand-by Current (TTL)

Stand-by Current (CMOS)

ICC4

-

1

mA

uA

CE=Vcc-0.2,

WP=0V/Vcc

ICC5

ILI

20

100

Input Leakage Current

Output Leakage Current

Input High Voltage

VIN=0 to Vcc (max)

-

uA

V

± 20

Vcc+0.3

0.2xVcc

-

ILO

VIH

VIL

VOUT =0 to Vcc (max)

-

0.8xVcc

-0.3

2.4

-

Input Low Voltage

-

V

Output High Voltage Level

Output Low Voltage Level

VOH

VOL

IOH=-400uA

IOL=2.1mA

V

-

0.4

V

IOL

(R/B)

Output Low Current (R/B)

VOL=0.4V

8

10

-

mA

Table 8: DC and Operating Characteristics

Value

3.3Volt

0V to VCC

5ns

Parameter

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

Output Load (2.7V - 3.6V)

VCC/2

1 TTL GATE and CL=50pF

Table 9: AC Conditions

Rev 0.2 / Jan. 2008

20

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Item

Input / Output Capacitance

Input Capacitance

Symbol

CI/O

Test Condition

VIL=0V

Min

Max

20

Unit

pF

-

CIN

VIN=0V

pF

20

Table 10: Pin Capacitance (TA=25C, F=1.0MHz)

Parameter

Symbol

tPROG

tDBSY

Min

Typ

Max

700

1

Unit

Program Time / Multi-Plane Program Time

Dummy Busy Time for Two Plane Program

Number of partial Program Cycles in the same page

Block Erase Time / Multi-Plane Block Erase Time

Read Cache Busy Time

-

200

0.5

-

us

NOP

8

Cycles

ms

tBERS

1.5

3

2

tRCBSY

tR

us

Table 11: Program / Erase Characteristics

Rev 0.2 / Jan. 2008

21

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

3.3V

Parameter

Symbol

Unit

Min

12

5

Max

CLE Setup time

CLE Hold time

CE setup time

CE hold time

tCLS

tCLH

tCS

ns

us

ns

us

20

5

tCH

WE pulse width

ALE setup time

ALE hold time

Data setup time

Data hold time

Write Cycle time

WE High hold time

tWP

tALS

tALH

tDS

12

5

12

5

tDH

tWC

tWH

tR

25

10

Data Transfer from Cell to register

ALE to RE Delay

25

tAR

10

20

12

CLE to RE Delay

tCLR

tRR

Ready to RE Low

RE Pulse Width

tRP

WE High to Busy

tWB

tRC

100

Read Cycle Time

25

RE Access Time

tREA

tRHZ

tCHZ

tCOH

tRHOH

tRLOH

tREH

tIR

20

100

50

RE High to Output High Z

CE High to Output High Z

CE High to Output hold

RE High to Output Hold

RE Low to Output Hold

RE High Hold Time

15

5

10

0

Output High Z to RE low

CE Low to RE Low

tCR

10

70

80

100

tADL

tWHR

tRHW

Address to data loading time

WE High to RE low

RE High to WE low

5/10/500⁽¹⁾

Device Resetting Time (Read / Program / Erase)

tRST

(2)

Write Protection time

tWW

100

ns

Table 12: AC Timing Characteristics

NOTE:

1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us

2. Program / Erase Enable Operation : WP high to WE High.

Program / Erase Disable Operation : WP Low to WE High.

Rev 0.2 / Jan. 2008

22

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

IO

0

Page Program

Block Erase

Read

NA

Cache Read

CODING

Pass / Fail

NA

Pass: ‘0’ Fail: ‘1’

1

NA

-

2

NA

3

NA

4

NA

Ready /

Busy

P/E/R

Controller Bit

5

6

7

Ready / Busy

Write Protect

Ready / Busy

Write Protect

Active: ‘0’ Idle:’1’

Busy: ‘0’ Ready:’1’

Ready /

Busy

Ready/Busy

NA

Protected: ‘0’

Write

Protect

Not Protected: ‘1’

Table 13 : Status Register Coding

DEVICE IDENTIFIER CYCLE

DESCRIPTION

Manufacturer Code

1st

2nd

3rd

4th

5th

Device Identifier

Internal chip number, cell Type, etc.

Page Size, Block Size, Spare Size, Organization

Multiplane information

Table 14: Device Identifier Coding

Bus

1st cycle

2nd cycle

3rd

cycle

4th

cycle

5th

cycle

Part Number

Voltage

Width (Manufacture Code) (Device Code)

HY27UG088G(5/D)B

3.3V

x8 ADh DCh

10h

95h

54h

Table 15: Read ID Data Table

Rev 0.2 / Jan. 2008

23

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Description

IO7

IO6

IO5 IO4

IO3 IO2

IO1 IO0

1

2

4

8

0 0

0 1

1 0

1 1

Die / Package

Cell Type

2 Level Cell

4 Level Cell

0 0

0 1

1 0

1 1

8 Level Cell

16 Level Cell

1

2

4

8

0 0

0 1

1 0

1 1

Number of

Simultaneously

Programmed Pages

Interleave Program

Between Multiple chips

Not

Supported

0

1

Not

Supported

0

1

Write Cache

Table 16: 3rd Byte of Device Idendifier Description

Description

1KB

2KB

4KB

8KB

IO7

IO6

IO5-4

IO3

IO2

IO1-0

0 0

0 1

1 0

1 1

Page Size

(Without Spare Area)

Spare Area Size

(Byte / 512Byte)

8

16

0

1

50ns

30ns

25ns

Reserved

0

1

0

1

0

1

Serial Access Time

64K

0 0

0 1

1 0

1 1

Block Size

(Without Spare Area)

128K

256K

512KB

X8

X16

0

1

Organization

Table 17: 4th Byte of Device Identifier Description

Rev 0.2 / Jan. 2008

24

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Description

IO7

IO6 IO5 IO4

IO3 IO2

IO1

IO0

1

2

4

8

0

1

0

1

0

1

Plane Number

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64Mb

128Mb

256Mb

512Mb

1Gb

Plane Size

(w/o redundant Area)

2Gb

4Gb

8Gb

Reserved

0

Table 18: 5rd Byte of Device Idendifier Description

Rev 0.2 / Jan. 2008

25

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Table 19: Page organization in EDC units (x8)

IO

0

Copy back Program

Pass/Fail

CODING

Pass: Fail: ‘1’

1

EDC status

EDC Validity

NA

NO error: ‘0’

2

Invalid: ‘0’ Valid: ‘1’

-

3

4

NA

-

5

Ready/Busy

Write Protect

Busy: ‘0’ Ready: ‘1’

Protected: ‘0’ Not Protected: ‘1’

6

7

Table 20: EDC Register Coding

Rev 0.2 / Jan. 2008

26

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

W&/

6

W&/+

W&+

&/(

W&6

&(

W:3

:(

W$/6

W$/+

$/(

W'6

W'+

,ꢃ2ꢄ[

&RPPDQG

Figure 5: Command Latch Cycle

W&/6

W&6

&/(

W:&

&(

W:3

:(

W:+

W$/+

W:+

W$/+

W:+

W$/+

W:+

W$/+

W$/6

W$/+

W'+

$/(

W'+

W'6

&ROꢈ$GGꢉ

&ROꢈ$GGꢅ

5RZꢄ$GGꢉ

5RZꢄ$GGꢅ

5RZꢄ$GGꢀ

,ꢃ2[

Figure 6: Address Latch Cycle

Rev 0.2 / Jan. 2008

27

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

W&/+

W&+

&/(

&(

W:&

W$/6

$/(

W:3

:(

W:+

W'+

W:+

W'+

W'6

',1ꢀꢂ

W'6

',1ꢀILQDO

W'6

',1ꢀꢁ

,ꢅ2[

Figure 7: Input Data Latch Cycle

Rev 0.2 / Jan. 2008

28

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

W5&

&(

5(

W&+=

W5(+

W5($

W&2+

W5+=

W5+2+

,ꢃ2[

5ꢃ%

'RXW

W55

1RWHVꢊꢄ7UDQVLWLRQꢄLVꢄPHDVXUHGꢄDWꢄꢋꢃꢌꢅꢇꢇP9ꢄIURPꢄVWHDG\ꢄVWDWHꢄYROWDJHꢄZLWKꢄORDGꢈ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ7KLVꢄSDUDPHWHUꢄLVꢄVDPSOHGꢄDQGꢄQRWꢄꢉꢇꢇꢍꢄWHVWHGꢈꢄꢎW&+=ꢏꢄW5+=ꢐ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5/2+ꢄLVꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄKLJKHUꢄWKDQꢄꢀꢀ0+]ꢈ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5+2+ꢄVWDUWVꢄWRꢄEHꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄORZHUꢄWKDQꢄꢀꢀ0+]ꢈ

Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)

W&5

&(

W5&

W&+=

W&2+

W53

W5(+

5(

W5+=

W5($

W5/2+

W5+2+

,ꢃ2[

5ꢃ%

'RXW

W55

1RWHVꢊꢄ7UDQVLWLRQꢄLVꢄPHDVXUHGꢄꢄDWꢄꢋꢃꢌꢅꢇꢇP9ꢄIURPꢄVWHDG\ꢄVWDWHꢄYROWDJHꢄZLWKꢄORDGꢈ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ7KLVꢄSDUDPHWHUꢄLVꢄVDPSOHGꢄDQGꢄQRWꢄꢉꢇꢇꢍꢄWHVWHGꢈꢄꢎW&+=ꢏꢄW5+=ꢐ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5/2+ꢄLVꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄKLJKHUꢄWKDQꢄꢀꢀ0+]ꢈ

ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄW5+2+ꢄVWDUWVꢄWRꢄEHꢄYDOLGꢄZKHQꢄIUHTXHQF\ꢄLVꢄORZHUꢄWKDQꢄꢀꢀ0+]ꢈ

Figure 9: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L)

Rev 0.2 / Jan. 2008

29

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

W&/5

&/(

&(

W&/6

W&6

W&/+

W&+

W:3

:(

W&+=

W&2+

W&5

W:+5

5(

W5+=

W5($

W'+

W'6

ꢃꢁK

W,5

W5+2+

,ꢅ2[

6WDWXVꢀ2XWSXW

Figure 10: Status Read Cycle

W

&/5

&/(

&(

W

:&

:(

$/(

W

:%

W

$5

W

5+=

W

5

W

5&

5(

W

55

ꢁꢁK

&ROꢅ$GGꢂ

5RZꢀ$GGꢂ

ꢄꢁK

'RXWꢀ1

'RXWꢀ1ꢇ

'RXWꢀ0

&ROꢅ$GGꢆ

5RZꢀ$GGꢆ 5RZꢀ$GGꢄ

,ꢅ2[

&ROXPQꢋ$GGUHVV

5RZꢋ$GGUHVV

%XV\

5ꢅ'

Figure 11: Read1 Operation (Read One Page)

Rev 0.2 / Jan. 2008

30

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

:(

W:%

W&+=

W$5

W&2+

$/(

5(

W5

W5&

W55

'RXW

1

'RXW

1ꢋꢉ

'RXW

1ꢋꢅ

&ROꢈ

5RZ

ꢇꢇK

ꢀꢇK

,ꢃ2[

5ꢃ%

$GGꢉ

$GGꢅ

$GGꢉ

$GGꢅ

$GGꢀ

&ROXPQꢄ$GGUHVV

5RZꢄ$GGUHVV

%XV\

Figure 12: Read1 Operation intercepted by CE

Rev 0.2 / Jan. 2008

31

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Figure 13: Random Data output

Rev 0.2 / Jan. 2008

32

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

$

&/(

&(

:(

$/(

5(

ꢋ&ROꢌ

5RZꢌ

$GGꢇ

ꢋ&ROꢌ

5RZꢌ

$GGꢇ

5RZꢌ 5RZꢌ

$GGꢂ $GGꢁ

5RZꢌ 5RZꢌ

$GGꢂ $GGꢁ

,ꢀ2[

5ꢀ%

$

ꢈꢈK

ꢇꢈK

ꢈꢈK

ꢇꢂK

'RXWꢋ1 'RXWꢋ1ꢍ

'RXWꢋ0

$GGꢂ $GGꢁ

W5&%6<

W5

yhukvt

ꢇꢂK

ꢇ)K

'RXWꢋ1

'RXWꢋ1ꢍ

'RXWꢋ0

'RXWꢋ1

'RXWꢋ1ꢍ

'RXWꢋ0

'RXWꢋ1

'RXWꢋ1ꢍ

'RXWꢋ0

W5&%6<

zlx|lu{phs

Figure 14: Read Operation with Read Cache

Rev 0.2 / Jan. 2008

33

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

W:&

:(

W$'/

W:%

W352*

W:+5

$/(

5(

&ROꢅ

5RZ

'LQ

1

'LQ

,ꢃ2[

ꢃꢁK

ꢂꢁK

,ꢉ2R

ꢈꢁK

0

$GGꢂ

$GGꢆ

$GGꢂ

$GGꢆ

$GGꢄ

6HULDOꢋ'DWD

ꢂꢋXSꢋWRꢋPꢋ%\WH

3URJUDP

5HDGꢋ6WDWXV

&RPPDQG

&ROXPQꢋ$GGUHVV

5RZꢋ$GGUHVV

,QSXWꢋ&RPPDQG

6HULDOꢋ,QSXW

&RPPDQG

5ꢃ%

,ꢀ2ꢈ ꢈꢋ6XFFHVVIXOꢋ3URJUDP

,ꢀ2ꢈ ꢂꢋ(UURUꢋLQꢋ3URJUDP

127(6ꢋꢎꢋꢋW$'/ꢋLVꢋWKHꢋWLPHꢋIURPꢋWKHꢋ:(ꢋULVLQJꢋHGJHꢋRIꢋILQDOꢋDGGUHVVꢋF\FOHꢋWRꢋWKHꢋ:(ꢋULVLQJꢋHGJHꢋRIꢋILUVWꢋGDWDꢋF\FOHꢌ

Figure 15: Page Program Operation

Rev 0.2 / Jan. 2008

34

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Figure 16: Random Data In

Rev 0.2 / Jan. 2008

35

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Figure 17: Copy Back Program Operation

Rev 0.2 / Jan. 2008

36

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Figure 18: Copy Back Program Operation with Random Data Input

Rev 0.2 / Jan. 2008

37

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

W:&

:(

W:%

W%(56

$/(

5(

,ꢃ2

[

ꢂꢇK 5RZꢄ$GGꢉ 5RZꢄ$GGꢅ 5RZꢄ$GGꢀ 'ꢇK

ꢁꢇK

,ꢃ2ꢇ

3DJHꢎ5RZꢐꢄ$GGUHVV

5ꢃ%

%86<

%ORFNꢄ(UDVHꢄ6HWXSꢄ&RPPDQG

5HDGꢄ6WDWXV ,ꢃ2ꢇ ꢇꢄ6XFFHVVIXOꢄ(UDVH

&RPPDQG ,ꢃ2ꢇ ꢉꢄ(UURUꢄLQꢄ(UDVH

(UDVHꢄ&RPPDQG

Figure 19: Block Erase Operation (Erase One Block)

Rev 0.2 / Jan. 2008

38

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Figure 20: Multiple plane page program

Rev 0.2 / Jan. 2008

39

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

W:&

:(

$/(

5(

W:+5

W:%

W%(56

5RZꢋ$GGꢇ

ꢄꢈK

5RZꢋ$GGꢂ 5RZꢋ$GGꢁ

ꢄꢈK

5RZꢋ$GGꢂ 5RZꢋ$GGꢁ

'ꢈK

ꢃꢈK

,ꢀ2ꢋꢈ

,ꢅ2[

5ꢅ%

5RZꢋ$GGUHVV

%XV\

,ꢀ2ꢋꢈꢋ ꢋꢈꢋ6XFFHVVIXOꢋ(UDVH

,ꢀ2ꢋꢈꢋ ꢋꢂꢋ(UURUꢋLQꢋ(UDVH

%ORFNꢋ(UDVHꢋ6HWXSꢋ&RPPDQGꢂ

%ORFNꢋ(UDVHꢋ6HWXSꢋ&RPPDQGꢁ

(UDVHꢋ&RQILUPꢋ&RPPDQG

5HDGꢋ6WDWXVꢋ&RPPDQG

([ꢌꢑꢋ$GGUHVVꢋ5HVWULFWLRQꢋIRUꢋ7ZRꢊ3ODQHꢋ%ORFNꢋ(UDVHꢋ2SHUDWLRQ

5ꢅ%

W%(56

$GGUHVV

,ꢅ2ꢇaꢈ

ꢄꢈK

'RK

ꢃꢈK

5RZꢋ$GGꢂꢏꢁꢏꢇ

$ꢂꢁꢋaꢋ$ꢂꢉꢋꢎꢋ)L[HGꢋµ/RZ¶

$ꢂꢒꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢎꢋ)L[HGꢋµ/RZ¶

$ꢁꢈꢋaꢋ$ꢁꢒꢋꢎꢋ)L[HGꢋµ/RZ¶

$ꢂꢁꢋaꢋ$ꢂꢉꢋꢎꢋ)L[HGꢋµ/RZ¶

$ꢂꢒꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢎꢋ)L[HGꢋµ+LJK¶

$ꢁꢈꢋaꢋ$ꢁꢒꢋꢎꢋ9DOLG

Figure 21: Multiple plane erase operation

Rev 0.2 / Jan. 2008

40

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Figure 22: Multi plane copyback program Operation

Rev 0.2 / Jan. 2008

41

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

&/(

&(

:(

W$5ꢄꢄ

$/(

5(

W5($ꢄꢄ

'&K

ꢉꢇK

ꢆꢑK

ꢑꢓK

ꢆꢇK

ꢇꢇK

$'K

,ꢃ2ꢄ[

5HDGꢄ,'ꢄ&RPPDQG $GGUHVVꢄꢉꢄF\FOH

0DNHUꢄ&RGH 'HYLFHꢄ&RGH

ꢀUGꢄ&\FOH

ꢓWKꢄ&\FOH ꢑWKꢄ&\FOH

Figure 23: Read ID Operation

Rev 0.2 / Jan. 2008

42

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

System Interface Using CE don’t care

To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.

So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND

Flash to make CE don’t care read operation was disabling of the automatic sequential read function.

&/(

&(ꢄGRQ¶WꢌFDUH

&(

:(

$/(

ꢒꢇK

6WDUWꢄ$GGꢈꢎꢑ&\FOHꢐ

'DWDꢄ,QSXW

ꢉꢇK

,ꢃ2[

Figure 24: Program Operation with CE don’t-care.

&/(

&(

,IꢄVHTXHQWLDOꢄURZꢄUHDGꢄHQDEOHGꢏ

&(ꢄPXVWꢄEHꢄKHOGꢄORZꢄGXULQJꢄW5ꢈ

&(ꢄGRQ¶WꢌFDUH

5(

$/(

5ꢃ%

W5

:(

,ꢃ2[

ꢇꢇK

6WDUWꢄ$GGꢈꢎꢑ&\FOHꢐ

ꢀꢇK

'DWDꢄ2XWSXWꢎVHTXHQWLDOꢐ

Figure 25: Read Operation with CE don’t-care.

Rev 0.2 / Jan. 2008

43

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

:(

$/(

&/(

5(

,2ꢂꢋꢁ

5ꢃ%

))K

W

567

Figure 26: Reset Operation

ꢁꢌꢃ9

ꢁꢌꢅ9

ꢁꢌꢃ9

ꢁꢌꢅ9

9&&

ꢈ9

GRQ¶W

ꢋFDUH

GRQ¶W

ꢋFDUH

&(

9

,+

2SHUDWLRQ

ꢂPVꢋPD[

9

,/

9

,/

:3

ꢂꢈꢈXꢋVPD[

,QYDOLG

GRQ¶W

ꢋFDUH

5HDG\%XV\

Figure 27: Power On and Data Protection Timing

VTH = 2.5 Volt for 3.3 Volt Supply devices

Rev 0.2 / Jan. 2008

44

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

5S

LEXV\

9FF

5HDG\

9FF

5ꢀ%

92+

92/ꢄꢊꢄꢇꢈꢓ9ꢏꢄꢄ92+ꢄꢊꢄꢅꢈꢓ9

RSHQꢋGUDLQꢋRXWSXW

92/

%XV\

WI

WU

*1'

'HYLFH

ꢄꢄ)LJꢈꢄ5SꢄYVꢄWUꢏꢄWIꢄꢔꢄ5SꢄYVꢄLEXV\

#ꢋ9FFꢋ ꢋꢇꢌꢇ9ꢏꢋ7Dꢋ ꢋꢁꢅ&ꢏꢋ& ꢅꢈS)

/

ꢀꢈꢀ

ꢀꢒꢉ

LEXV\

ꢅꢆꢇ

ꢉꢈꢉ

ꢀꢇꢇQ

ꢅꢇꢇQ

ꢉꢇꢇQ

ꢀP

ꢉꢈꢂꢑ

ꢉꢒꢆ

ꢅP

ꢉP

ꢆꢂ

ꢇꢈꢒꢅꢑ

ꢓꢈꢅ

ꢉN

ꢓꢈꢅ

ꢅN

ꢓꢈꢅ

WI

ꢀN

ꢓN

5SꢄꢎRKPꢐ

5SꢄYDOXHꢄJXLGHQFH

9FFꢄꢎ0D[ꢈꢐꢄꢌꢄ92/ꢄꢎ0D[ꢈꢐ

ꢀꢈꢅ9

5SꢄꢎPLQꢐꢄ

,2/ꢄꢋꢄ,

/

ꢒP$ꢄꢋꢄ,

/

ZKHUHꢄ,/ꢄLVꢄWKHꢄVXPꢄRIꢄWKHꢄLQSXWꢄFXUUQWVꢄRIꢄDOOꢄGHYLFHVꢄWLHGꢄWRꢄWKHꢄ5ꢃ%ꢄSLQꢈ

5SꢎPD[ꢐꢄLVꢄGHWHUPLQHGꢄE\ꢄPD[LPXPꢄSHUPLVVLEOHꢄOLPLWꢄRIꢄWU

Figure 28: Ready/Busy Pin electrical specifications

Rev 0.2 / Jan. 2008

45

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

wG]Z

wGZX

wG]Z

wGZX

O][P

a

OZYP

a

OXP

a

wGY

wGX

wGW

wGY

wGX

wGW

OZP

OYP

OXP

OZP

OZYP

OXP

kG

mGGsziGGGtziG

kh{hGpuGaGkGOXP kGO][P

lUPGyGGGOwP

kh{hGpuGaGkGOXP kGO][P

Figure 29: page programming within a block

Rev 0.2 / Jan. 2008

46

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Bad Block Management

Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the

blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and

common source line by a select transistor. The devices are supplied with all the locations inside valid blocks

erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of

the 1st or 2nd th page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be

read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-

nize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flow-

chart shown in Figure 30. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.

67$57

%ORFNꢄ$GGUHVV

%ORFNꢄꢇ

,QFUHPHQW

%ORFNꢄ$GGUHVV

'DWD^ꢎꢉꢐ

))K"

8SGDWH

%DGꢄ%ORFNꢄWDEOH

1R

<HV

/DVW

EORFN"

<HV

(1'

Figure 30: Bad Block Management Flowchart

NOTE :

1. Make sure that FFh at the column address 2048 of the 1st page and 2nd page.

Rev 0.2 / Jan. 2008

47

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Bad Block Replacement

Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying

the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give

errors in the Status Register.

Unlike the case of odd page which carries a possibility of affecting previous page, the failure of a page program oper-

ation does not affect the data in other pages in the same block, the block can be replaced by re-programming the cur-

rent data and copying the rest of the replaced block to an available valid block.

Refer to Table 21 and Figure 31 for the recommended procedure to follow if an error occurs during an operation.

Operation

Erase

Recommended Procedure

Block Replacement

Program

Read

Block Replacement

ECC (with 1bit/528byte)

Table 21: Block Failure

%ORFNꢋ$

'DWD

%ORFNꢋ%

'DWD

ꢓꢁꢑ

ꢓꢇꢑ

WK

)DLOXUH^ꢓꢂꢑ

))K

QꢋꢋꢋꢋSDJH

))K

%XIIHUꢋPHPRU\ꢋRIꢋWKHꢋFRQWUROOHU

Figure 31: Bad Block Replacement

NOTE :

1. An error occurs on n^thpage of the Block A during program or erase operation.

2. Data in Block A is copied to same location in Block B which is valid block.

3. N^thdata of block A which is in controller buffer memory is copied into n^thpage of Block B

4. Bad block table should be updated to prevent from eraseing or programming Block A

Rev 0.2 / Jan. 2008

48

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

Write Protect Operation

The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations

are enabled and disabled as follows (Figure 32~35)

:(

W

::

ꢉꢈK

,ꢀ2[

ꢂꢈK

5ꢀ%

Figure 32: Enable Programming

:(

W

::

ꢂꢈK

ꢉꢈK

,ꢀ2[

5ꢀ%

Figure 33: Disable Programming

Rev 0.2 / Jan. 2008

49

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

:(

W

::

ꢄꢈK

'ꢈK

,ꢀ2[

5ꢀ%

Figure 34: Enable Erasing

:(

W

::

ꢄꢈK

,ꢀ2[

'ꢈK

5ꢀ%

Figure 35: Disable Erasing

Rev 0.2 / Jan. 2008

50

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

ꢆꢉ

H

$ꢁ

$

'

%

/

Į

$ꢂ

ꢁꢆ

ꢁꢅ

',(

(ꢂ

(

&

&3

Figure 36: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

millimeters

Symbol

Min

Typ

Max

1.200

0.150

1.030

0.250

0.200

0.100

12.120

20.100

18.500

A

A1

A2

B

0.050

0.980

0.170

0.100

C

CP

D

11.910

19.900

18.300

12.000

20.000

18.400

0.500

E

E1

e

L

0.500

0

0.680

5

alpha

Table 22: 48-TSOP1 - 48-lead Plastic Thin Small Outline,

12 x 20mm, Package Mechanical Data

Rev 0.2 / Jan. 2008

51

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

%

%ꢂ

%ꢁ

'ꢂ

'

&ꢁ

&ꢂ

&

$ꢁ $ꢂ

$

FSꢂ

FSꢁ

ꢈꢌꢂ

0

ꢈꢌꢂ

&

$%

0

&

$%

(

Figure 37. 51-ULGA, 12 x 17mm, Package Outline

(Top view through package)

millimeters

Symbol

Min

Typ

17.00

13.00

12.00

10.00

6.00

1.00

1.50

2.00

1.00

Max

A

A1

A2

B

16.90

17.10

11.90

12.10

B1

B2

C

C1

C2

D

D1

E

0.55

0.65

0.95

0.60

0.65

0.75

1.05

CP1

CP2

0.70

1.00

Table 23: 52-ULGA, 12 x 17mm, Package Mechanical Data

Rev 0.2 / Jan. 2008

52

1

HY27UG088G(5/D)B Series

8Gbit (1Gx8bit) NAND Flash

MARKING INFORMATION - TSOP1 / ULGA

Packag

Marking Exam ple

K

G

O

x

R

B

TSOP1

H

x

Y

x

2

x

7

x

U

G

0

8

/

ULGA

Y

W

x

- hynix

- KOR

: Hynix Symbol

: Origin Country

- HY27UG088GxB xxxx

HY: Hynix

: Part Number

27: NAND Flash

U: Power Supply

G: Classification

08 : Bit Organization

8G: Density

: U(2.7V~3.6V)

: Single Level Cell+Double Die+Large Block

: 08(x8)

: 8Gbit

: 5(2nCE & 2R/nB; Sequential Row Read Disable)

: D(Dual interface; Sequential Row Read Disable)

: 3rd Generation

x: Mode

B: Version

: T(48-TSOP1), U(52-ULGA)

: Blank(Normal), P(Lead Free)

: C(0℃ ~70℃ ), I(-40℃ ~85℃ )

: B(Included Bad Block), S(1~5 Bad Block),

P(All Good Block)

x: Package Type

x: Package Material

x: Operating Temperature

x: Bad Block

- Y: Year (ex: 5=year 2005, 6= year 2006)

- ww: Work Week (ex: 12= work week 12)

- xx: Process Code

Note

- Capital Letter

- Sm all Letter

: Fixed Item

: Non-fixed Item

Rev 0.2 / Jan. 2008

53


型号：	HY27UG088GDB-UPIB
厂家：	HYNIX SEMICONDUCTOR
描述：	Flash, 1GX8, 20ns, PBGA52,
文件：	总53页 (文件大小：375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY27UG088GDB-UPIB [HYNIX]

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