HY27US16122B-TIB [HYNIX]
Flash, 32MX16, 18ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48;
| 型号： | HY27US16122B-TIB |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Flash, 32MX16, 18ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48 光电二极管 |
| 文件： | 总40页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
512Mb NAND FLASH
HY27US(08/16)12(1/2)B
HY27US0812(1/2)B
HY27US1612(1/2)B
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.5 / Jul. 2007
1
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
Revision
History
No.
Draft Date
Remark
0.0
0.1
Oct. 19. 2006 Preliminary
Mar. 07. 2007
Initial Draft.
1) Correct Figure 14 & 15
1) Add AC Characteristics
- tRB : Last RE High to busy (at sequential read)
- tCRY : CE High to Ready (in case of interception by CE at read)
- tCEH : CE High Hold Time (at the last serial read)
0.2
0.3
0.4
Mar. 26. 2007
Apr. 27. 2007
May. 29. 2007
1) Add sequential row read feature and figure
2) Modify Block Replacement
1) Add x16 Characteristics
2) Modify read2 operation (sequential row read)
3) Add AC Characteristics
- tOH : RE or CE High to Output Hold
1) Correct Read ID Table 16
0.5
Jul. 20. 2007
2) Correct System Interface Using CE don’t care operation
3) Correct Command Set Table 5
Rev 0.5 / Jul. 2007
2
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
- Cost effective solutions for mass storage applications
STATUS REGISTER
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
SUPPLY VOLTAGE
- VCC = 2.7 to 3.6V : HY27US(08/16)12(1/2)B
CHIP ENABLE DON’T CARE
- Simple interface with microcontroller
Memory Cell Array
x8 : (512+16) Bytes x 32 Pages x 4,096 Blocks
x16 : (256+8) Words x 32 Pages x 4,096 Blocks
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
PAGE SIZE
CE DON’t CARD OPTION ONLY
- x8 device : (512+16) Bytes
: HY27US0812(1/2)B
- x16 device : (256+8) Words
: HY27US1612(1/2)B
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27US(08/16)12(1/2)B-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27US(08/16)12(1/2)B-T (Lead)
- HY27US(08/16)12(1/2)B-TP (Lead Free)
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- HY27US0812(1/2)B-S(P)
- Random access: 12us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27US0812(1/2)B-S (Lead)
- HY27US0812(1/2)B-SP (Lead Free)
- HY27US0812(1/2)B-F(P)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- HY27US0812(1/2)B-F (Lead)
- HY27US0812(1/2)B-FP (Lead Free)
Rev 0.5 / Jul. 2007
3
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The Hynix HY27US(08/16)12(1/2)B series is a 64Mx8bit with spare 2Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Their NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is
erased.
The memory contains 4096 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash
cells.
A program operation allows to write the 512-byte (x8 device) or 256-word (x16 device) page in typical 200us and an erase
operation can be performed in typical 2ms on a 16K-byte (X8 device) block.
Data in the page can be read out at 30ns cycle time (3.3V device) per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards differ-
ent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modify operations can be locked using the WP input pin .
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple
memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27US(08/16)12(1/2)B extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip is offered with the CE don’t care function. This option allows the direct download of the code from the NAND Flash
memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails the
data can be directly programmed in another page inside the same array section without the time consuming serial data
insertion phase.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27US(08/16)12(1/2)B is available in 48 - TSOP1 12 x 20 mm package, 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm.
1.1 Product List
PART NUMBER
HY27US0812(1/2)B
HY27US1612(1/2)B
ORIZATION
VCC RANGE
PACKAGE
48TSOP1/ 48USOP1/ 63FBGA
48TSOP1
x8
2.7V - 3.6 Volt
x16
Rev 0.5 / Jul. 2007
4
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
9&&
,2ꢀa,2ꢁ
&(
,2ꢂa,2ꢃꢄꢅꢆ[ꢃꢇꢅRQO\ꢈ
:(
5ꢉ%
5(
$/(
&/(
:3
966
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
Data Input / Outputs (x16 only)
Data Inputs / Outputs
Command latch enable
Address latch enable
Chip Enable
ALE
CE
RE
Read Enable
WE
Write Enable
WP
Write Protect
R/B
Ready / Busy
Vcc
Power Supply
Vss
Ground
NC
No Connection
Table 1: Signal Names
Rev 0.5 / Jul. 2007
5
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
ꢇ
ꢄꢉ
1&
1&
1&
1&
1&
1&
5ꢀ%
5(
9VV
ꢇ
ꢄꢉ
1&
1&
1&
1&
1&
1&
5ꢀ%
5(
1&
1&
1&
1&
,ꢀ2ꢁ
,ꢀ2ꢂ
,ꢀ2ꢃ
,ꢀ2ꢄ
1&
1&
1&
9FF
9VV
1&
1&
1&
,ꢀ2ꢅ
,ꢀ2ꢆ
,ꢀ2ꢇ
,ꢀ2ꢈ
1&
1&
1&
1&
,ꢀ2ꢇꢃ
,ꢀ2ꢁ
,ꢀ2ꢇꢄ
,ꢀ2ꢂ
,ꢀ2ꢇꢅ
,ꢀ2ꢃ
,ꢀ2ꢇꢆ
,ꢀ2ꢄ
1&
1&
9FF
1&
1&
&(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1$1'ꢅ)ODVK
7623ꢃ
1$1'ꢅ)ODVK
7623ꢃ
ꢇꢆ
ꢇꢅ
ꢅꢁ
ꢅꢂ
ꢇꢆ
ꢇꢅ
ꢅꢁ
ꢅꢂ
1&
ꢆ[ꢃꢇꢈ
ꢆ[ꢂꢈ
,ꢀ2ꢇꢇ
,ꢀ2ꢅ
,ꢀ2ꢇꢈ
,ꢀ2ꢆ
,ꢀ2ꢊ
,ꢀ2ꢇ
,ꢀ2ꢉ
,ꢀ2ꢈ
9VV
ꢆꢄ
ꢆꢃ
ꢆꢄ
ꢆꢃ
Figure 2. 48TSOP1 Contactions, x8 and x16 Device
ꢇ
ꢄꢉ
1&
1&
1&
1&
1&
1&
5ꢀ%
5(
1&
1&
1&
1&
,ꢀ2ꢁ
,ꢀ2ꢂ
,ꢀ2ꢃ
,ꢀ2ꢄ
1&
&(
1&
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1&
1$1'ꢅ)ODVK
8623ꢃ
9FF
9VV
1&
1&
1&
,ꢀ2ꢅ
,ꢀ2ꢆ
,ꢀ2ꢇ
,ꢀ2ꢈ
1&
ꢇꢆ
ꢇꢅ
ꢅꢁ
ꢅꢂ
ꢆ[ꢂꢈ
1&
1&
1&
ꢆꢄ
ꢆꢃ
Figure 3. 48USOP1 Contactions, x8
Rev 0.5 / Jul. 2007
6
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
ꢃꢅꢅꢅꢅꢅꢅꢅꢅꢊꢅꢅꢅꢅꢅꢅꢅꢋꢅꢅꢅꢅꢅꢅꢅꢌꢅꢅꢅꢅꢅꢅꢅꢄꢅꢅꢅꢅꢅꢅꢇꢅꢅꢅꢅꢅꢅꢅꢅꢁꢅꢅꢅꢅꢅꢅꢅꢂꢅꢅꢅꢅꢅꢅꢅꢍꢅꢅꢅꢅꢅꢅꢃꢀ
$
%
1&
1&
1&
1&
1&
1&
1&
&
$/( 9VV
:3
1&
1&
&(
1&
:(
1&
5%
1&
'
&/(
5(
1&
1&
1&
1&
1&
1&
1&
1&
1&
1&
1&
9FF
1&
1&
1&
1&
1&
1&
1&
9FF
(
)
1&
1&
1&
1&
9VV
1&
*
+
-
,ꢀ2ꢈ
,ꢀ2ꢇ
,ꢀ2ꢆ
,ꢀ2ꢃ ,ꢀ2ꢁ
9VV
,ꢀ2ꢅ ,ꢀ2ꢄ
,ꢀ2ꢂ
.
/
1&
1&
1&
1&
1&
1&
1&
1&
0
Figure 4. 63FBGA Contactions, x8 Device (Top view through package)
Rev 0.5 / Jul. 2007
7
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name
Description
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
IO0-IO7
IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE).
The I/O buffer float to High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
CLE
ALE
CE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
This input controls the selection of the device. When the device is busy CE low does not deselect the
memory.
WRITE ENABLE
WE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
RE
WRITE PROTECT
WP
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
R/B
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
VCC
VSS
NC
GROUND
NO CONNECTION
Table 2: Pin Description
NOTE:
1. For x16 Version Only
2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Rev 0.5 / Jul. 2007
8
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
IO0
A0
IO1
A1
IO2
A2
IO3
A3
IO4
A4
IO5
A5
IO6
A6
IO7
A7
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A9
A10
A18
A11
A19
A12
A20
A13
A21
A14
A22
A15
A23
A16
A24
A17
A25
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
Table 3: Address Cycle Map(x8)
NOTE:
1. L must be set to Low.
2. A8 is set to LOW or High by the 00h or 01h Command.
IO0
A0
IO1
A1
IO2
A2
IO3
IO4
IO5
IO6
IO7
IO8-IO15
L(1)
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A3
A4
A5
A6
A7
A12
A20
A13
A21
A14
A22
A15
A23
A16
A24
L(1)
A9
A10
A18
A11
A19
L(1)
A17
A25
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
Acceptable command
during busy
FUNCTION
1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE
READ 1
READ 2
READ ID
RESET
00h/01h
50h
-
-
-
-
-
-
-
-
-
-
-
-
90h
FFh
Yes
Yes
PAGE PROGRAM
(start)
80h
00h
10h
8Ah
-
-
-
-
COPY BACK PGM
(start)
BLOCK ERASE
60h
70h
D0h
-
-
-
-
-
READ STATUS REGISTER
Table 5: Command Set
Rev 0.5 / Jul. 2007
9
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
H
L
ALE
L
CE
L
WE
Rising
Rising
Rising
Rising
Rising
H
RE
WP
MODE
H
X
Command Input
Address Input(4 cycles)
Command Input
Address Input(4 cycles)
Read Mode
H
L
L
H
X
H
L
L
H
H
Write Mode
Data Input
H
L
L
H
H
L
L
H
H
L(1)
L
L
L
Falling
X
Sequential Read and Data Output
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
L
L
H
H
X
X
X
X
X
X
X
X
X
H
X
X
X
X
H
L
X
X
X
X
X
X
H
X
0V/Vcc
Stand By
Table 6: Mode Selection
NOTE:
1. With the CE high during latency time does not stop the read operation
Rev 0.5 / Jul. 2007
10
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must
be high. See figure 6 and table 13 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. To insert the 25 addresses needed to access
the 512Mbit 4 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch
Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. More-
over for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 7 and
table 13 for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configu-
ration (X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure
8 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 9 to 15 and table 13 for details of
the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.5 / Jul. 2007
11
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Three types of operations are available: random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) or 264 words (x16
device) of data within the selected page are transferred to the data registers in less than access random read time tR
(12us). The system controller can detect the completion of this data transfer tR (12us) by analyzing the output of R/B
pin. Once the data in a page is loaded into the registers, they may be read out in 30ns cycle time by sequentially puls-
ing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last
column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting tR again allows reading the selected page. The sequential row read operation is terminated by bringing CE
high.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Writing
the Read2 command user may selectively access the spare area of bytes 512 to 527 (x8 device) or words 256 to 263
(x16 device). Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored.
Unless the operation is aborted, the page address is automatically incremented for sequential row
Read as in Read1 operation and spare sixteen bytes of each page (x8 device) or eight words of each page (x16 device)
may be sequentially read. The Read1 command (00h/01h) is needed to move the pointer back to the main area.
The Read2 command (50h) is needed to move the pointer back to the spare area.
Figure_11 to 14 show typical sequence and timings for each read operation.
3.2 Page Program.
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or
consecutive bytes up to 528 (x8 device), in a single page program cycle. The number of consecutive partial page pro-
gramming operations within the same page without an intervening erase operation must not exceed 1 for main array
and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a
serial data loading period in which up to 528 bytes (x8 device) or 264 word (x16 device) of data may be loaded into
the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation,
please refer to Figure 24 The data-loading sequence begins by inputting the Serial Data Input command (80h), fol-
lowed by the four address input cycles and then serial data loading. The Page Program confirm command (10h) starts
the programming process. Writing 10h alone without previously entering the serial data will not initiate the program-
ming process. The internal Program Erase Controller automatically executes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered, with RE and CE low, to read the status register. The system controller can
detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register.
Only the Read Status command and Reset command are valid while programming is in progress. When the Page Pro-
gram is complete, the Write Status Bit (I/O 0) may be checked in Figure 15 The internal write verify detects only errors
for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode
until another valid command is written to the command register.
Rev 0.5 / Jul. 2007
12
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block
address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution com-
mand ensures that memory contents are not accidentally erased due to external noise conditions.
The block address loading is accomplished three cycles. Only block addresses (A14 to A25 , highest address depending
on the device density) are needed while A9 to A13 is ignored.
At the rising edge of WE after the erase confirm command input, the internal Program Erase Controller handles erase
and erase-verify. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 17
details the sequence.
3.4 Copy-Back Program.
The copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to
another page within the same plane without using an external memory. Since the time-consuming sequential reading
and its reloading cycles are removed, the system performance is improved. The benefit is especially
obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-
reading cycle and copying-program with the address of destination page. A normal read operation with "00h" com-
mand and the address of the source page moves the whole 528byte data into the internal buffer.
As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of desti-
nation page followed may be written. The Program Confirm command (10h) is not needed to actually begin the pro-
gramming operation. For backward-compatibility, issuing Program Confirm command during copy-back does not affect
correct device operation.
Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished,
any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the
same between source and target page.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back oper-
ations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction
scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."
Figure 16 shows the command sequence for the copy-back operation.
The Copy Back Program operation requires three steps:
1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
4 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page
Buffer.
2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
given with the 4bus cycles to input the target page address. The value for A25 from second to the last page address
must be same as the value given to A25 in first address.
3. Then the confirm command is issued to start the P/E/R Controller.
Rev 0.5 / Jul. 2007
13
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operatio is com-
pleted, and whether the read, program or erase operation is completed successfully. After writing 70h command to the
command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or
RE, whichever occurs last. This two-line control allows the system to poll the progress of each device in multiple mem-
ory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status.
Refer to Table 14 for specific Status Register definitions. The command register remains in Status Read mode until fur-
ther commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command
(00h or 50h) should be given before sequential page read cycle.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Four read cycles sequentially output the 1st cycle (ADh), and 2nd cycle (the device code) and
3rd cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are
issued to it. Figure 18 shows the operation sequence, while Tables 16 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased.
The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when
WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset
command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset com-
mand is written. Refer to Figure 21 below.
Rev 0.5 / Jul. 2007
14
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection for Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 2.0V(3.0V device). WP pin provides hardware pro-
tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is
required before internal circuit gets ready for any command sequences as shown in Figure 22. The two-step command
sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a
reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied.
Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be
obtained with the following reference chart in Figure 23. Its value can be determined by the following guidance.
Rev 0.5 / Jul. 2007
15
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Parameter
Symbol
Min
Typ
Max
Unit
Valid Block Number
NVB
4016
4096
Blocks
Table 7: Valid Blocks Number
NOTE:
1. The 1st block is guaranteed to be a valid block up to 1K cycles with ECC. (1bit/528bytes)
Value
3.3V
Symbol
Parameter
Unit
Ambient Operating Temperature (Temperature Range Option 1)
Ambient Operating Temperature (Industrial Temperature Range)
Temperature Under Bias
0 to 70
℃
℃
℃
V
TA
-40 to 85
-50 to 125
-65 to 150
TBIAS
TSTG
Storage Temperature
(2)
Input or Output Voltage
Supply Voltage
-0.6 to 4.6
-0.6 to 4.6
V
VIO
Vcc
V
Table 8: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Rev 0.5 / Jul. 2007
16
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
$ꢆꢃꢋaꢋ$ꢈ
$''5(66
5(*,67(5ꢀ
&2817(5
352*5$0
(5$6(
;
&21752//(5
+9ꢋ*(1(5$7,21
ꢄꢃꢊꢅ0ELWꢅꢎꢅꢃꢇ0ELW
1$1'ꢅ)ODVK
0(025<ꢅ$55$<
'
(
&
2
'
(
5
$/(
&/(
:(
&(
:3
&200$1'
,17(5)$&(
/2*,&
5(
3$*(ꢋ%8))(5
<ꢋ'(&2'(5
&200$1'
5(*,67(5
'$7$
5(*,67(5
%8))(56
,2
Figure 5: Block Diagram
Rev 0.5 / Jul. 2007
17
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.3Volt
Parameter
Symbol
Test Conditions
Unit
Min
Typ
Max
tRC=30ns
CE=VIL,
IOUT=0mA
Sequential
Read
ICC1
-
15
30
mA
Operating
Current
Program
Erase
ICC2
ICC3
-
-
-
-
15
15
30
30
mA
mA
CE=VIH,
WP=0V/Vcc
Stand-by Current (TTL)
Stand-by Current (CMOS)
ICC4
-
-
-
1
mA
uA
CE=Vcc-0.2,
WP=0V/Vcc
ICC5
ILI
10
50
Input Leakage Current
Output Leakage Current
Input High Voltage
VIN=0 to Vcc (max)
-
-
-
-
-
-
uA
uA
V
± 10
± 10
Vcc+0.3
Vccx0.2
-
ILO
VIH
VIL
VOUT =0 to Vcc (max)
-
Vccx0.8
-0.3
2.4
-
Input Low Voltage
-
V
Output High Voltage Level
Output Low Voltage Leve
VOH
VOL
IOH=-400uA
IOL=2.1mA
V
-
0.4
V
IOL
(R/B)
Output Low Current (R/B)
VOL=0.4V
8
10
-
mA
Table 9: DC and Operating Characteristics
Value
3.3Volt
0V to Vcc
5ns
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (2.7V - 3.6V)
Vcc / 2
1 TTL GATE and CL=50pF
Table 10: AC Conditions
Rev 0.5 / Jul. 2007
18
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Item
Input / Output Capacitance
Input Capacitance
Symbol
CI/O
Test Condition
VIL=0V
Min
Max
10
Unit
pF
-
-
CIN
VIN=0V
10
pF
Table 11: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter
Symbol
tPROG
NOP
Min
Typ
Max
700
1
Unit
Program Time
-
-
-
-
200
us
Main Array
Spare Array
-
-
Cycles
Cycles
ms
Number of partial Program Cycles in the same page
Block Erase Time
NOP
2
tBERS
2
3
Table 12: Program / Erase Characteristics
Rev 0.5 / Jul. 2007
19
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.3Volt
Parameter
Symbol
Unit
Min
15
5
Max
CLE Setup time
tCLS
tCLH
tCS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE Hold time
CE setup time
20
5
CE hold time
tCH
WE pulse width
tWP
tALS
tALH
tDS
15
15
5
ALE setup time
ALE hold time
Data setup time
15
5
Data hold time
tDH
tWC
tWH
tR
Write Cycle time
30
10
WE High hold time
Data Transfer from Cell to register
ALE to RE Delay
12
tAR
10
10
20
15
CLE to RE Delay
tCLR
tRR
Ready to RE Low
RE Pulse Width
tRP
WE High to Busy
Read Cycle Time
RE Access Time
tWB
tRC
100
30
tREA
tRHZ
tCHZ
tOH
tREH
tIR
18
50
50
RE High to Output High Z
CE High to Output High Z
RE or CE high to Output hold
RE High Hold Time
Output High Z to RE low
CE Access Time
10
10
0
tCEA
tWHR
tRB
25
WE High to RE low
60
Last RE High to busy (at sequential read)
CE High to Ready (in case of interception by CE at read)
CE High Hold Time (at the last serial read)(3)
Device Resetting Time (Read / Program / Erase)
Write Protection time
100
(4)
ns
ns
us
ns
tCRY
tCEH
tRST
60+tr(R/B#)
100
100
(1,2)
5/10/500
(5)
tWW
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.ting time.
3. To break the sequential read cycle, CE must be held for longer time than tCEH.
4. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
5. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
Rev 0.5 / Jul. 2007
20
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Pagae
Program
Block
Erase
Cache
Read
IO
Read
CODING
0
Pass / Fail
Pass / Fail
NA
Pass: ‘0’ Fail: ‘1’
Pass: ‘0’ Fail: ‘1’ (Only for
Cache Program, else Don’t
care)
1
NA
NA
NA
2
3
4
NA
NA
NA
NA
NA
NA
NA
NA
NA
-
-
-
P/E/R
Controller Bit
5
6
7
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Active: ‘0’ Idle: ‘1’
Busy: ‘0’ Ready’: ‘1’
Ready/Busy
Protected: ‘0’
Not Protected: ‘1’
Table 14: Status Register Coding
DEVIIDENTIFIER CYCLE
DESCRIPTION
1st
Manufacturer Code
Device Identifier
2nd
Table 15: Device Identifier Coding
1st cycle
(Manufacture Code)
2nd cycle
(Device Code)
Part Number
Voltage
Bus Width
HY27US0812(1/2)B
HY27US1612(1/2)B
3.3V
3.3V
x8
ADh
ADh
76h
56h
x16
Table 16: Read ID Data Table
Rev 0.5 / Jul. 2007
21
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
W&/
6
W&/+
W&+
&/(
W&6
&(
W:3
:(
W$/6
W$/+
$/(
W'6
W'+
,ꢀ2ꢋ[
&RPPDQG
Figure 6: Command Latch Cycle
W&/6
W&6
&/(
&(
W:&
W:&
W:&
W:3
W:3
W:3
W:3
:(
W:+
W:+
W:+
W$/6
W$/6
W$/6
W$/+
W$/+
W$/+
W$/+
W'+
W$/6
$/(
W'+
W'+
W'+
W'6
W'6
W'6
W'6
,ꢉ2[
&ROꢌꢋ$GGꢇ
&ROꢌꢋ$GGꢆ
5RZꢋ$GGꢇ
5RZꢋ$GGꢆ
Figure 7: Address Latch Cycle
Rev 0.5 / Jul. 2007
22
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
W&/+
W&+
&/(
&(
W:&
$/(
W$/6
W:3
W:3
W:3
:(
W:+
W'+
W'+
W'+
',1ꢀꢂ
W'6
W'6
',1ꢀILQDOꢃ
W'6
',1ꢀꢁ
,ꢀ2[
Figure 8. Input Data Latch Cycle
t
CEA
CE
t
CHZ*
t
REH
t
REA
t
REA
tREA
t
OH
t
RP
RE
t
RHZ
t
RHZ*
OH
t
I/Ox
Dout
Dout
Dout
t
RR
t
RC
R/B
Notes : Transition is measured ±±22mꢀ from steady state voltage with load.
This parameter is sampled and not 122% tested.
Figure 9: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
Rev 0.5 / Jul. 2007
23
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
t2H
tCHZ
tWHR
RE
t2H
tDH
tREA
tDS
72h
tIR
tRH=
I/Ox
Status Output
Figure 10: Status Read Cycle
&/(
&(
W&(+
W&+=
W:&
:(
$/(
5(
W:%
W$5
W&5<
W5+=
W5
W5&
W53
ꢈꢈKꢋRUꢋꢈꢇK &ROꢌꢋ$GGꢇ 5RZꢋ$GGꢇ 5RZꢋ$GGꢆ 5RZꢋ$GGꢅ
'RXWꢋ1
'RXWꢋ1ꢍꢇ
'RXWꢋ1ꢍꢆ
'RXWꢋꢃꢆꢁ
,ꢀ2[
&ROXPQ
W5%
3DJHꢎ5RZꢏꢋ$GGUHVV
$GGUHVV
%XV\
5ꢀ%
Figure 11: Read1 Operation (Read One Page)
Rev 0.5 / Jul. 2007
24
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
&/(
&(
:(
W:%
W&+=
W$5
$/(
W5
W5&
5(
W55
ꢈꢈKꢋRUꢋꢈꢇK &ROꢌꢋ$GGꢇ 5RZꢋ$GGꢇ 5RZꢋ$GGꢆ 5RZꢋ$GGꢅ
'RXWꢋ1
'RXWꢋ1ꢍꢇ
'RXWꢋ1ꢍꢆ
,ꢀ2[
5ꢀ%
&ROꢌꢋ$GG
5RZꢋ$GG
%XV\
Figure 12: Read1 Operation intercepted by CE
&/(
&(
:(
$/(
5(
'RXW
'RXW
'RXW
ꢃꢆꢁ
'RXW
ꢃꢆꢁ
ꢃꢈK &ROꢌꢋ$GGꢇ 5RZꢋ$GGꢇ 5RZꢋ$GGꢆ 5RZꢋ$GGꢅ
ꢃꢇꢆꢍ1
ꢃꢇꢆꢍ1
,ꢀ2[
5ꢀ%
5HDG\
%XV\
%XV\
0
0ꢍꢇ
1
2XWSXW
2XWSXW
Figure 13: Read2 Operation (Sequential Row Read)
Rev 0.5 / Jul. 2007
25
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
&/(
&(
:(
$/(
5(
'RXW
1
'RXW
ꢃꢆꢁ
'RXW
ꢇ
'RXW
1ꢍꢇ
'RXW
ꢃꢆꢁ
'RXW
ꢈ
ꢈꢈK &ROꢌꢋ$GGꢇ 5RZꢋ$GGꢇ 5RZꢋ$GGꢆ 5RZꢋ$GGꢅ
,ꢀ2[
5ꢀ%
5HDG\
%XV\
%XV\
0
0ꢍꢇ
1
2XWSXW
2XWSXW
Figure 14: Sequential Row Read Operation Within a Block
&/(
&(
W:&
W:&
W:&
:(
W:%
W352*
$/(
5(
'LQ
1
'LQ
0
,ꢉ2[
&ROꢅꢀ$GGꢂ
ꢂꢁK
ꢇꢁK
,ꢈ2R
ꢄꢁK
5RZꢀ$GGꢂ 5RZꢀ$GGꢆ 5RZꢀ$GGꢉ
6HULDOꢀ'DWD
3URJUDP
5HDGꢀ6WDWXV
&RPPDQG
&ROXPQ
$GGUHVV
5RZꢀ$GGUHVV
[ꢄꢀꢅꢃꢀXSꢀWRꢀꢆꢃꢇꢀ%\WH
[ꢃꢈꢀꢅꢀꢃꢀXSꢀWSꢀꢇꢆꢈꢀ:RUG
6HULDOꢀ,QSXW
,QSXWꢀ&RPPDQG
&RPPDQG
5ꢉ%
,ꢁ2R ꢂꢀ6XFFHVVIXOꢀ3URJUDP
,ꢁ2R ꢃꢀ(UURUꢀLQꢀ3URJUDP
Figure 15: Page Program Operation
Rev 0.5 / Jul. 2007
26
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 16 : Copy Back Program
Rev 0.5 / Jul. 2007
27
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
&/(
&(
W:&
:(
W:%
W%(56
$/(
5(
,ꢉ2
[
ꢂꢈK 5RZꢋ$GGꢇ 5RZꢋ$GGꢆ 5RZꢋ$GGꢅ 'ꢈK
ꢁꢈK
,ꢀ2ꢈ
5RZꢋ$GGUHVV
5ꢉ%
%86<
$XWRꢋ%ORFNꢋ(UDVHꢋ6HWXSꢋ&RPPDQG
5HDGꢋ6WDWXV ,ꢀ2ꢈ ꢈꢋ6XFFHVVIXOꢋ(UDVH
&RPPDQG ,ꢀ2ꢈ ꢇꢋ(UURUꢋLQꢋ(UDVH
(UDVHꢋ&RPPDQG
Figure 17: Block Erase Operation (Erase One Block)
CLE
CE
WE
tAR
ALE
RE
tREA
90h
00h
ADh
ꢁꢂK
I/O x
Read ID Command Address 1 cycle
Maker Code Device Code
Figure 18: Read ID Operation
Rev 0.5 / Jul. 2007
28
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.
So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND
Flash to make CE don’t care read operation was disabling of the automatic sequential read function. (HY27US(08/16)122B)
&/(
&(ꢋGRQ¶WꢐFDUH
&(
:(
$/(
ꢉꢈK
6WDUWꢋ$GGꢌꢎꢄ&\FOHꢏ
'DWDꢋ,QSXW
'DWDꢋ,QSXW
ꢇꢈK
,ꢉ2[
Figure 19: Program Operation with CE don’t-care.
&/(
,IꢋVHTXHQWLDOꢋURZꢋUHDGꢋHQDEOHGꢑ
&(ꢋPXVWꢋEHꢋKHOGꢋORZꢋGXULQJꢋW5ꢌ
&(ꢋGRQ¶WꢐFDUH
&(
5(
$/(
5ꢀ%
W5
:(
,ꢀ2[
ꢈꢈK
6WDUWꢋ$GGꢌꢎꢄ&\FOHꢏ
ꢅꢈK
'DWDꢋ2XWSXWꢎVHTXHQWLDOꢏ
Figure 20: Read Operation with CE don’t-care.
Rev 0.5 / Jul. 2007
29
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
:(
$/(
&/(
5(
,2ꢁꢏꢀ
5ꢉ%
))K
W
567
Figure 21: Reset Operation
9FF
97+
W
:3
:(
ꢃꢂXV
Figure 22: Power On and Data Protection Timing
VTH = 2.5 Volt for 3.3 Volt Supply devices
Rev 0.5 / Jul. 2007
30
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
5S
LEXV\
9FF
5HDG\
9FF
5ꢁ%
92+
RSHQꢀGUDLQꢀRXWSXW
92/ꢓꢋ ꢈꢌꢄ9ꢑꢋ92+ꢓꢋꢆꢌꢄ9
92/
%XV\
WI
WU
*1'
'HYLFH
ꢋꢋ)LJꢌꢋ5SꢋYVꢋWUꢑꢋWIꢋꢒꢋ5SꢋYVꢋLEXV\
#ꢀ9FFꢀ ꢀꢉꢊꢉ9ꢋꢀ7Dꢀ ꢀꢇꢆ&ꢋꢀ& ꢆꢂS)
/
ꢅꢌꢅ
ꢅꢉꢇ
LEXV\
ꢆꢊꢈ
ꢇꢌꢇ
ꢅꢈꢈQ
ꢆꢈꢈQ
ꢇꢈꢈQ
ꢅP
ꢇꢌꢂꢃ
ꢇꢉꢊ
ꢆP
ꢇP
ꢊꢂ
ꢈꢌꢉꢆꢃ
ꢄꢌꢆ
ꢄꢌꢆ
ꢇN
ꢄꢌꢆ
ꢆN
ꢄꢌꢆ
WI
ꢅN
ꢄN
5SꢋꢎRKPꢏ
5SꢋYDOXHꢋJXLGHQFH
9FFꢋꢎ0D[ꢌꢏꢋꢐꢋ92/ꢋꢎ0D[ꢌꢏ
ꢅꢌꢆ9
5SꢋꢎPLQꢏꢋ
,2/ꢋꢍꢋ,
/
ꢉP$ꢋꢍꢋ,
/
ZKHUHꢋ,/ꢋLVꢋWKHꢋVXPꢋRIꢋWKHꢋLQSXWꢋFXUUQWVꢋRIꢋDOOꢋGHYLFHVꢋWLHGꢋWRꢋWKHꢋ5ꢀ%ꢋSLQꢌ
5SꢎPD[ꢏꢋLVꢋGHWHUPLQHGꢋE\ꢋPD[LPXPꢋSHUPLVVLEOHꢋOLPLWꢋRIꢋWU
Figure 23: Ready/Busy Pin electrical specifications
Rev 0.5 / Jul. 2007
31
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
[ꢇꢂꢋ'HYLFHV
[ꢉꢋ'HYLFHV
$UHDꢋ$
ꢎꢈꢈKꢏ
$UHDꢋ&
ꢎꢃꢈKꢏ
$UHDꢋ$
ꢎꢈꢈKꢏ
$UHDꢋ%
ꢎꢈꢇKꢏ
$UHDꢋ&
ꢎꢃꢈKꢏ
%\WHVꢋꢈꢐꢆꢃꢃ
%\WHVꢋꢆꢃꢂꢐꢆꢂꢅ
%\WHVꢋꢈꢐꢆꢃꢃ
%\WHVꢋꢆꢃꢂꢐꢃꢇꢇ
%\WHVꢋꢃꢇꢆꢐꢃꢆꢁ
3DJHꢋ%XIIHU
3DJHꢋ%XIIHU
$
&
$
%
&
3RLQWHU
3RLQWHU
ꢎꢈꢈKꢑꢃꢈKꢏ
ꢎꢈꢈKꢑꢈꢇKꢑꢃꢈKꢏ
Figure 24: Pointer operations
$5($ꢋ$
$GGUHVV
,QSXWV
$GGUHVV
,QSXWV
,ꢀ2
,ꢀ2
ꢈꢈK
ꢉꢈK
'DWDꢋ,QSXW
ꢇꢈK
ꢈꢈK
ꢉꢈK
'DWDꢋ,QSXW
ꢇꢈK
$UHDVꢋ$ꢑꢋ%ꢑꢋ&ꢋFDQꢋEHꢋSURJUDPPHGꢋGHSHQGLQJꢋRQꢋKRZꢋPXFKꢋGDWDꢋLVꢋLQSXWꢌꢋ6XEVHTXHQWꢋꢈꢈKꢋFRPPDQGVꢋFDQꢋEHꢋRPLWWHGꢌ
$5($ꢋ%
$GGUHVV
,QSXWV
$GGUHVV
,QSXWV
ꢈꢇK
ꢉꢈK
'DWDꢋ,QSXW
ꢇꢈK
ꢈꢇK
ꢉꢈK
'DWDꢋ,QSXW
ꢇꢈK
$UHDVꢋ%ꢑꢋ&ꢋFDQꢋEHꢋSURJUDPPHGꢋGHSHQGLQJꢋRQꢋKRZꢋPXFKꢋGDWDꢋLVꢋLQSXWꢌꢋ7KHꢋꢈꢇKꢋFRPPDQGꢋPXVWꢋEHꢋUHꢐLVVXHGꢋEHIRUHꢋHDFKꢋSURJUDPꢌ
$5($ꢋ&
$GGUHVV
,QSXWV
$GGUHVV
,QSXWV
,ꢀ2
ꢃꢈK
ꢉꢈK
'DWDꢋ,QSXW
ꢇꢈK
ꢃꢈK
ꢉꢈK
'DWDꢋ,QSXW
ꢇꢈK
2QO\ꢋ$UHDVꢋ&ꢋFDQꢋEHꢋSURJUDPPHGꢌꢋ6XEVHTXHQWꢋꢃꢈKꢋFRPPDQGꢋFDQꢋEHꢋRPLWWHGꢌ
Figure 25: Pointer Operations for porgramming
Rev 0.5 / Jul. 2007
32
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks
erased(FFh).
The Bad Block Information is written prior to shipping. Any block where the 6th Byte/ 3rd Word in the spare area of
the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be
read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-
nize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flow-
chart shown in Figure 26. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give
errors in the Status Register.
As the failure of a page program operation does not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation.
Operation
Erase
Recommended Procedure
Block Replacement
Program
Read
Block Replacement
ECC (with 1bit/528byte)
Table 18: Block Failure
67$57
%ORFNꢋ$GGUHVV
%ORFNꢋꢈ
,QFUHPHQW
%ORFNꢋ$GGUHVV
8SGDWH
%DGꢋ%ORFNꢋWDEOH
'DWD
))K"
1R
1R
<HV
/DVW
EORFN"
<HV
(1'
Figure 26: Bad Block Management Flowchart
Rev 0.5 / Jul. 2007
33
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 27~30)
:(
W
::
ꢄꢂK
,ꢁ2[
ꢃꢂK
5ꢁ%
Figure 27: Enable Programming
:(
W
::
ꢄꢂK
ꢃꢂK
,ꢁ2[
5ꢁ%
Figure 28: Disable Programming
Rev 0.5 / Jul. 2007
34
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
:(
W
::
ꢈꢂK
'ꢂK
,ꢁ2[
5ꢁ%
Figure 29: Enable Erasing
:(
W
::
ꢈꢂK
,ꢁ2[
'ꢂK
5ꢁ%
Figure 30: Disable Erasing
Rev 0.5 / Jul. 2007
35
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
ꢌꢄ
H
$ꢇ
$
'
%
/
Į
$ꢃ
ꢇꢌ
ꢇꢆ
',(
(ꢃ
(
&
&3
Figure 31: 48pin-TSOP1, 12 x 20mm, Package Outline
millimeters
Symbol
Min
Typ
Max
1.200
0.150
1.030
0.250
0.200
0.100
12.120
20.100
18.500
A
A1
A2
B
0.050
0.980
0.170
0.100
C
CP
D
11.910
19.900
18.300
12.000
20.000
18.400
0.500
E
E1
e
L
0.500
0
0.680
5
alpha
Table 19: 48pin-TSOP1, 12 x 20mm, Package Mechanical Data
Rev 0.5 / Jul. 2007
36
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
$
$ꢊ
(
$ꢃ
'
Į
&3
&ꢃ
Figure 32. 48pin-USOP1, 12 x 17mm, Package Outline
millimeters
Symbol
Min
Typ
Max
0.650
0.080
0.570
0.230
0.175
0.750
0.100
17.100
12.120
15.500
A
A1
A2
B
0
0.050
0.520
0.160
0.100
0.650
0.470
0.130
0.065
0.450
C
C1
CP
D
16.900
11.910
15.300
17.000
12.000
15.400
0.500
D1
E
e
alpha
0
8
Table 20: 48pin-USOP1, 12 x 17mm, Package Mechanical Data
Rev 0.5 / Jul. 2007
37
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
'
'ꢇ
'ꢃ
6'
)'ꢃ
)'
H
H
6(
(
(ꢇ (ꢃ
)(
)(ꢃ
%$//ꢀ³FS
$
´
H
E
$ꢇ
$ꢃ
Figure 33. 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline
NOTE: Drawing is not to scale.
Millimeters
Typ
Symbol
Min
0.80
0.25
0.55
0.40
8.90
Max
1.00
0.35
0.65
0.50
9.10
A
A1
A2
b
0.90
0.30
0.60
0.45
D
9.00
D1
D2
E
E1
E2
e
4.00
7.20
11.00
5.60
8.80
10.90
11.10
0.80
FD
FD1
FE
FE1
SD
SE
2.50
0.90
2.70
1.10
0.40
0.40
Rev 0.5 / Jul. 2007
38
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
MARKING INFORMATION - TSOP1/USOP
Packag
Marking Exam ple
K
2
O
x
R
B
TSOP1
/
H
x
Y
x
2
x
7
x
U
S
x
x
1
USOP
Y
W
W
x
x
- hynix
- KOR
: Hynix Symbol
: Origin Country
- HY27USxx12xB xxxx
HY: Hynix
: Part Number
27: NAND Flash
U: Power Supply
S: Classification
xx: Bit Organization
12: Density
: U(2.7V~3.6V)
: Single Level Cell+Single Die+Small Block
: 08(x8), 16(x16)
: 512Mbit
: 1nCE & 1R/nB; Sequential Row Read Enable
: 1nCE & 1R/nB; Sequential Row Read Disable
: 3rd Generation
x: Mode
B: Version
x: Package Type
x: Package Material
: T(48-TSOP1), S(48-USOP)
: Blank(Normal), P(Lead Free)
: C(0℃ ~70℃ ), I(-40℃ ~85℃ )
: B(Included Bad Block), S(1~5 Bad Block),
P(All Good Block)
x: Operating Temperature
x: Bad Block
- Y: Year (ex: 5=year 2005, 06= year 2006)
- ww: Work Week (ex: 12= work week 12)
- xx: Process Code
Note
: Fixed Item
- Capital Letter
: Non-fixed Item
- Sm all Letter
Rev 0.5 / Jul. 2007
39
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
MARKING INFORMATION - FBGA
Packag
Marking Exam ple
K
2
O
x
R
B
H
x
Y
x
2
x
7
x
U
S
0
8
1
FBGA
Y
W
W
x
x
- hynix
- KOR
: Hynix Symbol
: Origin Country
- HY27U0812xB xxxx
HY: Hynix
: Part Number
27: NAND Flash
U: Power Supply
S: Classification
08: Bit Organization
12: Density
: U(2.7V~3.6V)
: Single Level Cell+Single Die+Small Block
: 08(x8)
: 512Mbit
: 1nCE & 1R/nB; Sequential Row Read Enable
: 1nCE & 1R/nB; Sequential Row Read Disable
: 3rd Generation
x: Mode
B: Version
x: Package Type
x: Package Material
: F(63FBGA)
: Blank(Normal), P(Lead Free)
: C(0℃ ~70℃ ), I(-40℃ ~85℃ )
: B(Included Bad Block), S(1~5 Bad Block),
P(All Good Block)
x: Operating Temperature
x: Bad Block
- Y: Year (ex: 5=year 2005, 06= year 2006)
- ww: Work Week (ex: 12= work week 12)
- xx: Process Code
Note
: Fixed Item
- Capital Letter
: Non-fixed Item
- Sm all Letter
Rev 0.5 / Jul. 2007
40
相关型号：
HY27US16122B-TPCP
Flash, 32MX16, 18ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, TSOP1-48
HYNIX
HY27US16122B-TPIP
Flash, 32MX16, 18ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, TSOP1-48
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