HY29F040AR-12 [HYNIX]
512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory; 512K ×8位CMOS 5.0伏只，扇区擦除闪存
| 型号： | HY29F040AR-12 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory |
| 文件： | 总40页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY29F040A Series
512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory
KEY FEATURES
·
·
·
Internal Erase Algorithms
·
·
·
5.0 V ± 10% Read, Program, and Erase
Minimizes system-level power requirements
High performance
55 ns access time
Compatible with JEDEC-Standard Commands
-
Automatically erases a sector, any combination
of sectors, or the entire chip
-
Internal Programming Algorithms
-
-
Automatically programs and verifies data at a
specified address.
-
Uses software commands, pinouts, and
packages following industry standards for
single power supply Flash memory
Low Power Consumption
-
-
-
40 mA maximum active read current
60 mA maximum program/erase current
5 mA maximum standby current
·
·
Minimum 100,000 Program/Erase Cycles
Sector Erase Architecture
-
-
Eight equal size sectors of 64K bytes each
Any combination of sectors can be erased
concurrently; also supports full chip erase
·
Sector Protection
-
Hardware method disables any combination
of sectors from a program or erase operation
·
Erase Suspend/Resume
-
Suspend a sector erase operation to allow a
data read or programming in a sector not
being erased within the same device
DESCRIPTION
The HY29F040A is programmed by executing the
program command sequence. This will start the
internal byte programming algorithm that
automatically times the program pulse width and
also verifies the proper cell margin. Erase is
accomplished by executing either sector erase or
chip erase command sequence. This will start the
internal erasing algorithm that automatically times
the erase pulse width and also verifies the proper
cell margin. No preprogramming is required prior to
execution of the internal erase algorithm. Sectors
of the HY29F040A Flash memory array are electri-
cally erased via Fowler-Nordheim tunneling. Bytes
are programmed one byte at a time using a hot
electron injection mechanism.
The HY29F040A is a 4 Megabit, 5.0 volt-only CMOS
Flash memory device organized as a 512K bytes
of 8 bits each. The device is offered in standard
32-pin PDIP, 32-pin PLCC and 32-pin TSOP pack-
ages. It is designed to be programmed and
erased in-system with a 5.0 volt power-supply and
can also be reprogrammed in standard PROM
programmers.
The HY29F040A offers access times of 55 ns, 70
ns, 90 ns, 120 ns and 150 ns. The device has sepa-
rate chip enable (/CE), write enable (/WE) and out-
put enable (/OE) controls. Hyundai Flash memory
devices reliably store memory data even after
100,000 program/erase cycles.
The HY29F040A features a sector erase architecture.
The device memory array is divided into 8 sectors of
64K bytes each. The sectors can be erased indi-
vidually or in groups without affecting the data in
other sectors. The multiple sector erase and full
chip erase capabilities add flexibility to altering the
data in the device. To protect data in the device
from accidental program and erase, the device
also has a sector protect function. This function
hardwarewriteprotectstheselectedsectors.The sector
The HY29F040A is entirely pin and command set
compatible with the JEDEC standard for 4 Mega-
bit Flash memory devices. The commands arewrit-
tentothecommandregisterusingstandardmicropro-
cessor write timings. Register contents serve as
input to an internal state-machine which controls
the erase and programming circuitry. Write cycles
also internally latch addresses and data needed
for the programming and erase operations.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licences are implied.
Rev.03/Aug.97
Hyundai Semiconductor
protect and sector unprotect features can be en- Vcc detector inhibits write operations on loss of
abled in a PROM programmer.
power. End of program or erase is detected by/Data
Polling of DQ7 or by the Toggle Bit feature on DQ6.
The HY29F040A needs a single 5.0 volt power- Once program or erase cycle is successfully com-
supply for read, program and erase operation. In- pleted, the device internally resets to the Read
ternally generated and well regulated voltages are mode.
provided for program and erase operation. A low
BLOCK DIAGRAM
DQ 0-DQ7
E rase V oltage
Generator
Vcc
Vss
Input/Output
B uffers
State
C ontrol
WE
Com mand
R egister
P GM V oltage
Generator
Chip E nable
Output E nable
Logic
C E
OE
STB
Data Latch
STB
Y -Gating
Y-D ecoder
A ddress
Latch
Cell Matrix
V cc D etector
Timer
X-D ecoder
A 0-A18
2
HY29F040A
PIN DESCRIPTION
Pin Name
A0 - A18
DQ0 - DQ7
/CE
Pin Function
Address Inputs
Data Input/Output
Chip Enable
/OE
Output Enable
Write Enable
/WE
Vss
Device Ground
Vcc
Device Power Supply
(5.0V ±10 % for -70, -90, -120 and -150)
(5.0V ±5 % for -55)
PIN CONNECTION
A1 1
A 9
A 8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
O E
A1 0
C E
O E
A1 0
C E
32
A1 1
A 9
A 8
1
31
2
30
3
A1 3
A1 4
A1 7
W E
V cc
A1 8
A1 6
A1 5
A1 2
A 7
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
V ss
DQ 2
DQ 1
DQ 0
A 0
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
V ss
DQ 2
DQ 1
DQ 0
A 0
29
A1 3
A1 4
A1 7
W E
V cc
A1 8
A1 6
A1 5
A1 2
A 7
4
28
5
27
6
26
7
25
8
9
24
9
10
11
12
13
14
15
16
23
10
11
22
21
12
13
20
A 6
A 5
A 4
A 1
A 2
A 3
A 1
A 2
A 3
19
A 6
A 5
A 4
14
15
16
18
17
Standard TSOP
Reverse TSOP
1
V cc
W E
A1 7
A1 4
A1 3
A 8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A1 8
A1 6
A1 5
A1 2
A 7
2
3
4
29
28
27
26
25
24
23
22
21
5
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
A1 4
A1 3
A 8
5
6
6
A 6
7
7
A 9
A 5
8
A 9
8
A1 1
O E
A 4
9
A1 1
O E
9
A 3
10
11
12
13
10
11
12
13
14
15
16
A1 0
C E
A 2
A1 0
C E
A 1
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
A 0
DQ 0
DQ 7
DQ 0
DQ 1
DQ 2
V ss
PDIP
PLCC
3
HY29F040A
BUS OPERATION
Table 1. Bus Operations(1)
OPERATION
/CE /OE /WE
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
I/O
Electronic ID Manufacturer Code(2)
Electronic ID Device Code(2)
Read(3)
L
L
L
H
L
L
L
L
L
L
H
H
H
X
H
L
Code
Code
DOUT
H
L
L
L
A0
X
A1
X
A6
X
Standby
X
High Z
High Z
Output Disable
H
H
VID
L
X
X
X
X
(4)
Write
A0
X
A1
X
A6
X
A9
VID
VID
DIN
Enable Sector Protect
L
X
Verify Sector Protect
H
L
H
L
Code
Notes:
1. L = VIL, H = VIH, X = Don’t Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 4.
3. /WE can be VIL if /CE is VIL, /OE at VIH initiates the write operations.
4. Refer to Table 4 for valid DIN during a write operation.
Table 2. Sector Protection Verify Electronic ID Codes
Type
A18 A17
A16
A6
A1
A0
Code DQ7
HEX
DQ6
DQ5
DQ4 DQ3 DQ2
DQ1
DQ0
Manufacture Code
X
X
X
X
X
VIL
VIL
VIL
ADH
1
0
1
0
1
1
0
1
HY29F040A
Device Code
X
VIL
VIL
VIL
VIH
VIL
A4H
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
Sector Protection
Sector Addresses
VIH
01H(1)
Notes:
1. Outputs 01H at protected sector addresses, and output 00H at unprotected sector addresses.
4
HY29F040A
Table 3. Sector Addresses
A18
A17
0
A16
0
Address Range
00000H - 0FFFFH
10000H - 1FFFFH
20000H - 2FFFFH
30000H - 3FFFFH
40000H - 4FFFFH
50000H - 5FFFFH
60000H - 6FFFFH
70000H - 7FFFFH
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Electronic ID Mode
Read Mode
The Electronic ID mode allows the reading out of The HY29F040A has three control functions which
a binary code from the device and will identify its must be satisfied to obtain data at the outputs. /
manufacturer and device type. This mode is in- CE is the power control and should be used for
tended for use by programming equipment for the device selection. /OE is the output control and
purpose of automatically matching the device to be should be used to gate data to the output pins if a
programmed with its corresponding programming device is selected. As shown in Table 1, /WE
algorithm. This mode is functional over the entire should be held at VIH, except in Write mode and
temperature range of the device.
Enable Sector Protect mode.
To activate this mode, the programming equipment
must force VID (11.5V to 12.5V) on address pin
A9. Two identifier bytes may then be sequenced
from the device outputs by toggling address A0
from VIL to VIH. All addresses are don’t cares ex-
cept A0, A1, A6, and A9.
Address access time (tACC) is equal to the delay
from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from
stable addresses and stable /CE to valid data at
the output pins. The output enable access time is
the delay from the falling edge of /OE to valid data
at the output pins (assuming the addresses have
been stable for at least tACC-tOE time).
The manufacturer and device codes may also be
read via the command register, (i.e., when
HY29F040A is erased or programmed in a system
without access to high voltage on the A9 pin). The
command sequence is illustrated in Table 4 (refer
to Electronic ID Command section).
Standby Mode
The HY29F040A has two standby modes: a CMOS
standby mode (/CE input held at Vcc ± 0.5V), when
current consumed is typically less than 1 mA; and a
TTL standby mode (/CE is held at VIH) when the
typical current required is reduced to 1 mA. In
standby mode, outputs are in a high impedance
state, independent of /OE input.
Byte 0 (A0=VIL) represents the manufacturer’s code
(Hyundai Electronics=ADH) and byte 1 (A0=VIH)
the device identifier code (HY29F040A=A4H).
These two bytes are given in Table 2. All identifi-
ers for manufacturer and devices will exhibit odd
parity with the MSB (DQ7) defined as the parity
bit. To permit reading of the proper device codes
when executing the Electronic ID, A1 must be VIL
(see Table 2).
If the device is deselected during programming or
erase, the device will draw active current until the
programming or erase operation is completed.
5
HY29F040A
mode that disables both Programming and Erase
operation to protected sectors. In this device there
are 8 sectors of 64K bytes each. The sector protect
feature is enabled using programming equipment
at the user’s site. The device is shipped from
Hyundai’s factory with all sectors unprotected.
Output Disable Mode
With the /OE input at a logic high level (VIH), output
from the device is disabled. This will cause the
output pins to be in a high impedance state. It is
shown in Table 1 that /CE = VIL and /WE = VIH for
Output Disable. This is to differentiate Output Dis-
able mode from Write mode and to prevent
inadvertant writes during Output Disable.
To activate the Sector Protect mode, the user
must force VID on address pin A9 and control pin /
OE. The sector addresses (A18, A17 and A16)
should be set to the sector to be protected (see
Table 3 for the sector address for each of the eight
individual sectors). Programming of the protec-
tion circuitry starts on the falling edge of /WE pulse
and is terminated with the rising edge of
/WE. Sector addresses must be held fixed during
the /WE pulse.
Write Mode
Device programming and erase are accomplished
via the command register. The contents of the reg-
ister serve as inputs to the internal state machine.
Outputs of the state machine dictate the function
of the device.
The command register itself does not occupy any
addressable memory locations. The register is a
latch used to store the commands along with the
addresses and data information needed to execute
the command. The command register is written
by bringing /WE to VIL, while /CE is at VIL and /OE
is at VIH. Addresses are latched on the falling edge
of /WE or /CE, whichever happens later, while data
is latched on the rising edge of /WE or /CE, which-
ever happens first. Standard microprocessor
write timings are used. Refer to AC Characteris-
tics for Programming/Erase and their respective
Timing Waveforms for specific timing parameters.
To verify programming of the protection circuitry,
the programming equipment must force VID on the
address pin A9 with /CE and /OE at VIL and
/WE at VIH. As shown in Table 2, scanning the
sector addresses (A18, A17 and A16) while (A6,
A1 and A0) = (0, 1, 0) will produce a 01H code at
the device output pins for a protected sector. In
the Verify Sector Protect mode, the device will read
00H for an unprotected sector. In this mode, the
lower order addresses, except for A0, A1 and A6,
are don’t care. Address locations with A1 = VIL are
reserved for electronic ID manufacturer and de-
vice codes. It is also possible to determine if a
sector is protected in-system by writing the Elec-
tronic ID command (described in the Electronic
ID command section below).
Enable Sector Protect and Verify
Sector Protect Modes
The HY29F040A has a hardware Sector Protect
6
HY29F040A
COMMAND DEFINITIONS
Device operations are selected by writing
specific address and data sequences into the
Command register. Writing incorrect addresses
and data values or writing them in the improper
sequence will reset the device to Read mode.
Table 4 defines the valid register command
sequences. Either Read/Reset command will
reset the device (when applicable).
(1,2,3,4)
Table 4. Command Definitions
Bus
First Bus
Second Bus
Write Cycle
Third Bus
Fourth Bus
Write Cycle
Fifth Bus
Sixth Bus
Command
Sequence
Write
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Cycles
Req'd Addr
Data
F0H
Addr
RA
Data
Addr
Data
Addr
RA
Data
Addr
Data
Addr
Data
Read/Reset
Read/Reset
Electronic ID
1
4
4
XXXH
5555H
5555H
RD
55H
55H
AAH 2AAAH
AAH 2AAAH
5555H F0H
5555H 90H
RD
XX00H ADH
XX01H
PA
A4H
PD
Byte Program
Chip Erase
4
6
6
1
1
5555H
5555H
5555H
XXXH
XXXH
AAH 2AAAH
AAH 2AAAH
AAH 2AAAH
B0H
55H
55H
55H
5555H A0H
5555H 80H
5555H 80H
5555H
5555H
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
SA
10H
30H
Sector Erase
Erase Suspend
Erase Resume
30H
Notes:
1. Bus Operations are defined in Table 1.
2. For a Command Sequence, address bits A15, A14, A13, A12, and A11 = X = Don’t care. Address bits A18, A17, A16,
and A15 = X = Don’t care for all address commands except for Program Address(PA) and Sector Address(SA).
In the case of Sector Address, address bit A15 = X = Don’t care for all addresses except for Program Address (PA)
and Sector Addresses (SA).
3. RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the /WE pulse.
PD = Data to be programmed at location PA. Data is latched on the falling edge of /WE.
SA = Address of the sector to be erased (see Table 3).
4. The Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation
is in progress.
7
HY29F040A
the falling edge of /CE or /WE, whichever hap-
pens later, and program data (PD) is latched on
the rising edge of /CE or /WE, whichever happens
first. The rising edge of /CE or /WE, whichever
happens first, begins byte programming.
Read/Reset Command
The read or reset operation is initiated by writing
the Read/Reset command sequence in to the com-
mand register. Microprocessor read cycles retrieve
the data from the memory. The device remains
enabled for reads until the command register con-
tents are changed.
Upon executing the Byte Programming command
sequence, the device’s internal state machine ex-
ecutes an internal byte programming algorithm. The
system is not required to provide further con-
trols or timings. The device will automatically pro-
vide adequate internally generated program pulses
and verify the programmed cell margin of the byte.
The device will automatically power-up in the Read/
Reset mode. In this case, a command sequence
is not needed to read the memory data. This de-
fault power-up to Read mode ensures that no spu-
rious changes of the data can take place during
the power transitions. Refer to the AC Character-
istics for Read-Only Operation and the respective
Timing Waveforms for the specific timing param-
eters.
During byte programming operation, data bit DQ7
shows the complement of the program data. This
operation is known as /Data Polling. The internal
byte programming algorithm has completed it’s
operation when the data on DQ7 is equivalent to
the last data written to this bit (see Write Operation
Status section). At the completion of the byte pro-
gramming algorithm, the device returns to the read
mode. At this time, the address pins are no longer
latched. Therefore, the system must supply the last
program address at the completion of the byte pro-
gramming operation to read the correct program
data on DQ7.
Electronic ID Command
The HY29F040A contains an Electronic ID com-
mand to supplement the traditional PROM
programming method described in the Electronic
ID Mode section. The operation is initiated by
writing the Electronic ID command sequence into
the command register. Following the command
write, a read cycle from address XX00H retrieves
manufacturer code of ADH. A read cycle from ad-
dress XX01H returns the device code A4H (see
Table 2). All manufacturer and device codes will
exhibit odd parity with the MSB (DQ7) defined as
the parity bit.
Byte programming is allowed in any sequence, and
across sector boundaries. However, remember that
a data “0” cannot be programmed to a data ”1".
Only erase operations can convert alogical ”0" to a
logical “1”. Attempting to program data from “0” to
“1” may cause the device to exceed time limits, or
even worse, result in an apparent success accord-
ing to the /Data Polling algorithm. In the later case,
however, a subsequent read of this bit will show
that the data is still a logical “0”.
The Electronic ID command can also be used
to identify protected sectors. After writing the
Electronic ID command sequence, the CPU can
scan the sector addresses (A18, A17, A16) while
(A6, A1, A0) = (0, 1, 0). Protected sectors will
return 01H on the data outputs and unprotected
sectors will return 00H. To terminate the operation, it
is necessary to write the Read/Reset command
sequence into the command register.
Figure 1 illustrates the Byte Programming
Algorithm using typical command strings and bus
operations.
Chip Erase Command
Byte Programming Command
Chip erase is a six bus cycle operation (see Table 4).
Chip erase begins on the rising edge of the last /
WE pulse in the command sequence. There are
two 'unlock' write cycles. These are followed by
The HY29F040A is programmed one byte at a time.
Programming is a four bus cycle operation (see
Table 4). The program address (PA) is latched on
8
HY29F040A
writing the "set-up" command. Two more 'unlock' executes an internal erase algorithm. The system is
write cycles are then followed by the chip erase not required to provide further controls or
command.
timings. The device will automatically provide
adequate internally generated erase pulses and
verify sector erase within the proper cell margins.
Protected sectors of the device will not be erased,
even if they are selected with the Sector Erase
command.
Upon executing the Chip Erase command
sequence, the device’s internal state machine
executes an internal erase algorithm. The system is
not required to provide further controls or timings.
The device will automatically provide adequate in-
ternally generated erase pulses and verify chip
erase within the proper cell margins. During chip
erase, all sectors of the device are erased except
protected sectors.
Multiple sectors can be erased sequentially by writ-
ing the sixth bus cycle command of the Sector Erase
command for each sector to be erased. The time
between initiation of the next Sector Erase com-
mand must be less than 80 ms to guarantee ac-
ceptance of the command by the internal state ma-
chine. The time-out window can be monitored via
the write operation status pin DQ3 (refer to the Write
Operation Status section for Sector Erase Timer
operation). It is recommended that CPU interrupts
be disabled during this time to ensure that the sub-
sequent Sector Erase commands can be initiated
within the 80 ms window. The interrupts can be re-
enabled after the last Sector Erase command is
written. As mentioned above, an internal device timer
will initiate the Sector Erase operation 100 ms ±20%
(80 ms to 120 ms) from the rising edge of the last /
WE pulse. The Sector Erase Timer Write Operation
Status pin (DQ3) can be used to monitor the time out
window. If another falling edge of the /WE occurs
within the 100 ms time-out window, the internal de-
vice timer is reset. Loading the sector erase buffer
may be done in any sequence and with any num-
ber of sectors.
During Chip Erase, data bit DQ7 shows a logical
“0”. This operation is known as /Data Polling. The
erase operation is completed when the data on DQ7
is a logical “1” (see Write Operation Status sec-
tion). Upon completion of the Chip Erase
operation, the device returns to read mode. At this
time, the address pins are no longer latched. Note
that /Data Polling must be performed at a sector
address within any of the sectors being erased and
not a protected sector to ensure that DQ7 returns
a logical “1” upon completion of the Chip Erase
operation.
Figure 2 illustrates the Chip Erase Algorithm
using typical command strings and bus operations.
The device will ignore any commands written to
the chip during execution of the internal Chip Erase
algorithm.
Sector Erase Command
Any command other than Sector Erase or Erase
Suspend or Erase Resume during this period and
afterwards will reset the device to read mode, ig-
noring the previous command string. Resetting the
device after it has begun execution of a Sector
Erase operation will result in the data in the oper-
ated sectors being undefined. In this case, restart
the Sector Erase operation on those sectors and
allow them to complete the Erase operation.
Sector erase is a six bus cycle operation (see Table
5). There are two 'unlock' write cycles that are fol-
lowed by writing the "set-up" command. Two more
"unlock" write cycles are then followed by the sec-
tor erase command. The sector address (any ad-
dress location within the desired sector) is latched
on the falling edge of /WE, while the command data
is latched on the rising edge of /WE. An internal de-
vice timer initiates Sector Erase operation after 100
ms ±20% (80 ms to 120 ms) from the rising edge of
the /WE pulse for the last Sector Erase command
entered on the device.
When erasing a sector or multiple sectors, the data
in the unselected sectors remains unaffected. The
system is not required to provide any controls or
timings during these operations.
Upon executing the Sector Erase command
sequence, the device’s internal state machine
9
HY29F040A
During Sector Erase operation, data bit DQ7 shows Writing the Erase Suspend command during the
a logical “0”. This operation is known as time-out will result in immediate termination of the
/Data Polling. Sector Erase operation is complete time-out period. Any subsequent writes of the Sec-
when data on DQ7 is a logical “1” (see Write Opera- tor Erase command will be taken as the Erase
tion Status section) at which time the Resume command (30H). Note that any other com-
device returns to read mode. At this time, the mands during the time-out will reset the
address pins are no longer latched. Note that device to the read mode. The address pins are
/Data Polling must be performed at a sector don’t-cares when writing the Erase Suspend or
address within any of the sectors being erased and Erase Resume commands.
not a protected sector to ensure that DQ7 returns
When the Erase Suspend command is written dur-
a logical “1” upon completion of the Sector Erase
ing a Sector Erase operation, the chip will take a
operation.
maximum of 15 ms to suspend the erase opera-
Figure 2 illustrates the Sector Erase Algorithm us- tion and go into erase suspended-read mode.
ing typical command strings and bus operations.
During this time, the system can monitor the /Data
Polling or Toggle Bit write operation status flags to
determine when the device has entered erase sus-
pend-read mode (see Write Operation Status sec-
tion). The system must use an address of an eras-
ing sector to monitor /Data Polling or Toggle Bit to
determine if the Sector Erase operation has been
suspended.
During execution of the Sector Erase command, only
the Erase Suspend and Erase Resume com-
mands are allowed. All other commands will reset
the device to read mode. Note: Do not attempt to
write an invalid command sequence during the
sector erase operation. Doing so will terminate the
sector erase operation and the device will reset to
the read mode.
In the erase suspend-read mode, the system can
read data from any sector that is not being erased.
A read from a sector being erased may result in
invalid data.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command allows the user to
interrupt a Sector Erase operation and read data
from or program to a sector that is not being erased.
The Erase Suspend command onthe HY29F040 also
allows for Byte Programming during the suspended
erase from a sector not being erased. The Erase
Suspend command is applicable only during Sector
Erase operation and will be ignored if written during
the Chip Erase operation or Byte Programming op-
eration. The Erase Suspend command (B0H) will
be allowed only during the Sector Erase opera-
tion, including, but not limited to, the sector erase
time-out period after any Sector Erase commands
(30H) have been initiated.
After the system writes the Erase Suspend com-
mand and waits until the Toggle Bit stops toggling,
data reads from the device may then be performed.
Any further writes of the Erase Suspend command
at this time will be ignored.
To resume operation of Sector Erase, the Erase
Resume command (30H) should be written. Any
further writes of the Erase Resume command at
this point will be ignored. Another Erase Suspend
command can be written after the chip has re-
sumed the Sector Erase operation.
10
HY29F040A
WRITE OPERATION STATUS
Table 5. Write Operation Status Flags(1)
Status
DQ7
/DQ7
0
DQ6
Toggle
DQ5
DQ3
0
Byte Programming Operation
0
0
0
In Progress Chip or Sector Erase Operation
Erase Suspend Erase Suspended Sector
Toggle
1
1
No Toggle
N/A
Mode
Non-Erase Suspended Sector
Data
/DQ7
0
Data
Data
Data
Exceeded
Byte Programming Operation
Toggle
Toggle
Toggle
1
1
1
0
1
1
Time Limits Chip or Sector Erase Operation
Program in Erase Suspend Mode
/DQ7
Notes:
1. DQ0, DQ1, DQ2, DQ4 are reserve pins for future use.
chronously while the output enable (/OE) is as-
serted low. This means that the device is driving sta-
tus information on DQ7 at one instant of time and
valid data at the next instant of time. Depending on
when the system samples the DQ7 output, it may
read the status or valid data. Even if the device has
completed the Internal Algorithm operation and DQ7
has a valid data, data outputs on DQ0-DQ6 may be
still invalid. Valid data on DQ0-DQ7 will be read on
successive read attempts.
DQ7
/Data Polling
The HY29F040A device features /Data Polling as
a method to indicate to the host the status of the
Byte Programming, Chip Erase, and Sector Erase
operations. When the Byte Programming opera-
tion is in progress, an attempt to read the device
will produce the compliment of the data last writ-
ten to DQ7. Upon completion of the Byte Program-
ming operation, an attempt to read the device will
produce the true data last written to DQ7. When
the Chip Erase or Sector Erase operation is in
progress, an attempt to read the device will produce
a logical “0” at the DQ7 output. Upon completion of
the Chip Erase or Sector Erase operation, an at-
tempt to read the device will produce a logical ”1" at
the DQ7 output. The flowchart for /Data Polling (DQ7)
is shown in Figure 3.
The Data Polling feature is only active during the
Byte Programming operation, Chip Erase
operation, Sector Erase Operation, or sector
erase time-out window (see Table 5).
DQ6
Toggle Bit
The HY29F040A also features the “Toggle Bit”
as a method to indicate to the host system the
status of the Internal Programming and Erase
Algorithms. The flowchart for Toggle Bit (DQ6) is
shown in Figure 4.
For Chip Erase, the /Data Polling is valid after the
rising edge of the sixth /WE pulse in the six write
pulse sequence. For Sector Erase, the /Data Poll-
ing is valid after the last rising edge of the sector
erase /WE pulse. For both Chip Erase and Sec-
tor Erase, /Data Polling must be performed atsec-
tor address within any of the sectors being erased
and not a protected sector. Otherwise, the /Data
Polling status may not be valid. Once the Internal
Algorithm operation is close to being completed,
the HY29F040A data pins (DQ7) may change asyn-
During an Internal Programming or Erase Algorithm
cycle, successive attempts to read (/OE toggling)
data from the device will result in DQ6 toggling
between one and zero. Once the Internal Pro-
gramming or Erase operation is completed, DQ6
will stop toggling and valid data will be read on the
11
HY29F040A
next successive attempts. During Byte Programming, Erase operation, it indicates the entire chip is bad
the Toggle Bit is valid after the rising edge of the or combination of sectors are bad. In this situa-
fourth /WE pulse in the four write pulse tion, the chip should not be reused.
sequence. For Chip Erase, the Toggle Bit is valid
after the rising edge of the sixth /WE pulse in the If this failure condition occurs during the Byte Pro-
six write pulse sequence. For Sector Erase, the gramming operation, it indicates the entire sector
Toggle Bit is valid after the last rising edge of the containing that byte is bad and this sector may not
sector erase /WE pulse. The Toggle Bit is also be reused (other sectors are still functional and can
active during the sector erase time-out win- be reused).
dow.
The DQ5 failure condition may also appear if a
In Byte Programming, if the sector being written to is user tries to program a non-blank location without
protected, the Toggle Bit toggles for about 2 ms and erasing. In this example, the device may exceed time
then stops toggling without the data having changed. limits and not complete the Internal Algorithm op-
In Chip Erase or Sector Erase, the device will eration. Hence, the system never reads valid data
erase all the selected sectors except for the ones on DQ7 bit, and DQ6 never stops toggling. Once
that are protected. If all selected sectors are pro- the device has exceeded timing limits, the DQ5
tected, the chip will toggle the Toggle Bit for about bit will indicate a “1”.
100 ms and then drop back into read mode, having
changed none of the data. Either /CE or /OE tog-
DQ3
Sector Erase Timer
gling will cause the DQ6 Toggle Bit to toggle.
After the completion of the initial Sector Erase com-
mand sequence, the sector erase time-out win-
dow will begin. DQ3 will remain low until the time-
DQ5
Exceeded Timing Limits
DQ5 will indicate if Byte Programming, Chip Erase, out window is closed. /Data Polling and Toggle Bit
or Sector Erase time has exceeded the specified are valid after the initial Sector Erase command
limits (internal pulse count) of the device. Under sequence.
these conditions DQ5 will produce a logical “1”. This
isafailureconditionthatindicatestheprogramor erase If /Data Polling or the Toggle Bit indicates the de-
cycle was not successfully completed. /Data Poll- vice has been written with a valid erase
ing is the only operating functionofthedeviceunder command, DQ3 may be used to determine if the
this condition. The /OE and /WE pins will control Sector Erase time-out window is still open. If DQ3
output disable functions as described in Table 1.
is a logical “1”, the internally controlled erase cycle
has begun. Attempts to write subsequent com-
If this failure condition occurs during Sector Erase mand to the device will be ignored until the erase
operation, it indicates a particular sector is bad operation is completed as indicated by /Data Poll-
and it may not be reused. However, other sectors ing or Toggle Bit. If DQ3 is a logical ”0", the device
are still functional and may continue to be used will accept additional Sector Erase commands.
for the program or erase operation. To use other To insure the command has been accepted, the
sectors of the device, it must be reset to Read system software should check the status of DQ3
mode. Write the Read/Reset command sequence prior to and following each subsequent Sector
to the device, and then execute the Byte Program- Erase command. If DQ3 were high on the second
ming or Sector Erase command sequence. This status check, the command may not have been
allows the system to continue to use the other accepted. Refer to Table 5: Write Operation Sta-
active sectors in the device.
tus Flags.
If this failure condition occurs during the Chip
12
HY29F040A
DATA PROTECTION
Power-Up Write Inhibit
The HY29F040A is designed to offer protection Power-up of the device with /WE = /CE = VIL and
against accidental erasure or programming /OE = VIH will not accept commands on the rising
caused by spurious system level signals that may edge of /WE. The internal state machine is
exist during power transitions. During power-up the automatically reset to Read mode on power-up.
device automatically resets the internal state ma-
chine in the Read mode. Also, with its control reg-
ister architecture, alteration of the memory con-
Sector Protection
Sectors of the HY29F040A may be hardware
protected at the users factory. The protection
circuitry will disable both program and erase
functions for the protected sectors. Requests to
program or erase a protected sector will be
ignored by the device. Sector protection is
accomplished in a PROM programmer.
tents only occurs after successful completion of spe-
cific multi-bus cycle command sequences. The
device also incorporates several features to pre-
vent inadvertent write cycles resulting from Vcc
power-up and power-down transitions or
system noise.
Low Vcc Write Inhibit
The HY29F040A features hardware sector protec-
tion that will disable both program and erase
operations to an individual sector or any group of
sectors. To activate this mode, programming
equipment must force VID on control pin /OE and
address pin A9. Sector addresses should be set
using higher address lines A18, A17 and A16. The
protection mechanism begins on the falling edge
of the /WE pulse and is terminated with the rising
edge of /WE. See Figures 13 and 14 for details of
implementing Sector Protect.
To avoid initiation of a write cycle during Vcc power-
up and power-down, a write cycle is locked out for
Vcc less than 3.2V (typically 3.7V). If Vcc < VLKO
,
the command register is disabled and all internal
programming/erase circuits are disabled. Under
this condition the device will reset to the Read
mode. Subsequent writes will be ignored until the
Vcc level is greater than VLKO. It is the users re-
sponsibility to ensure that the control pins are logi-
cally correct to prevent unintentional writes when
Vcc is above 3.2V.
Sector Unprotect
Write Pulse “Glitch” Protection
The HY29F040A also features a sector unprotect
mode, so that a protected sector may be unpro-
tected to incorporate any changes in the code.
Protecting all sectors is necessary before
unprotecting any sector(s). Sector unprotection is
accomplished in a PROM programmer. See Fig-
ures 15 and 16 for details of implementing Sector
Unprotect.
Noise pulses of less than 5 ns (typical) on /OE,
/CE or /WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of
/OE = VIL, /CE = VIH , or /WE = VIH. To initiate a
write cycle /CE and /WE must be a logical “0” while
/OE is a logical “1”.
13
HY29F040A
START
Write Program Command Sequence
(see below)
/Data Polling Device
NO
Last Address
Increment Address
?
YES
Programming Completed
Program Command Sequence (Address/Command)
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Figure 1. Internal Programming Algorithm
14
HY29F040A
Start
W rite Erase Com m and Sequ ence
(see below)
/Data Polling or Toggle Bit
S uccessfully C ompleted
Erase Co mpleted
Ind ividual Se ctor/M ultiple Se ctor
Ch ip Erase Com m and Sequence
(Address/Com m and)
Erase Com m and Sequ ence
(Address/Com m and)
5555 H/AA H
2AA AH /55H
5 555H /80H
5555 H/AA H
2AA AH /55H
5 555H /10H
5555 H/AA H
2AA AH /55H
5 555H /80H
5555 H/AA H
2AA AH /55H
Sector Addre ss/30 H
Sector Addre ss/30 H
Sector Addre ss/30 H
Add itio na l sector
erase c om m a nds
a re o ptiona l
Figure 2. Internal Erase Algorithm
15
HY29F040A
START
VA
=
=
Byte address for programming
Any of the sector addresses
within the sector being erased
during sector erase operation.
Read Byte
(DQ0-DQ7), Addr = VA
=
XXXXH during Chip Erase
YES
DQ7 = Data
?
NO
NO
DQ5 = 1
?
YES
Read Byte
(DQ0-DQ7), Addr = VA
YES
DQ7 = Data
?
NO
Fail
Pass
Notes:
1. DQ7 is rechecked even if DQ5 = logical “1” because DQ7 may change simultaneously with DQ5.
Figure 3. /Data Polling Algorithm
16
HY29F040A
START
Read Byte
(DQ0-DQ7)
NO
DQ6 = Toggle
?
YES
NO
DQ5 = 1
?
YES
Read Byte
(DQ0-DQ7)
NO
DQ6 = Toggle
?
YES
Fail
Pass
Notes:
1. DQ6 is rechecked even if DQ5 = logical “1” because DQ6 may stop toggling at the same
time as DQ5 changing to a logical ”1".
Figure 4. Toggle Bit Algorithm
17
HY29F040A
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Package .............................. -65°C to + 125°C
Ambient Temperature
With Power Applied .......................... -55°C to + 125°C
Voltage with Respect to Ground
All pins except A9 (1) .......................... -2.0V to + 7.0V
Vcc(1) ............................................... -2.0V to + 7.0V
A9(2) ............................................... -2.0V to + 14.0V
Commercial( C) Devices ..................... 0°C to + 70°C
Industrial (I) Devices ........................ -40°C to + 85°C
Extended (E) Devices ..................... -55°C to + 125°C
Vcc Supply Voltages .................................................
Vcc for HY29F040A-55 .................. + 4.75V to + 5.25V
Vcc for HY29F040A-70, -90, -120, -150
Output Short Circuit Current(3) ......................... 200 mA
..........................................................+ 4.5V to + 5.5V
Notes:
Notes:
1. Operating ranges define those limits between which
the functionality of the device is guaranteed.
1. Minimum DC voltage on input or I/O pins
is - 0.5V. During voltage transitions, inputs may
overshoot Vss to -2.0V for periods of up to 20 ns.
Maximum DC voltage on output and I/O pins is Vcc +
0.5V. During Voltage transitions, outputs may
overshoot to Vcc + 2.0V for periods up to 20 ns.
2. Minimum DC input voltage on A9 pin is -0.5V.
During voltage transitions, A9 may overshoot Vss
to -2.0V for periods of up to 20 ns. Maximum DC input
voltage on A9 is + 13.5V which may overshoot to 14.0V
for periods of up to 20 ns.
3. No more than one output shorted at a time. Duration
of the short circuit should not be greater than one
second.
indicated in the operational sections of this specification
is not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
18
HY29F040A
20 ns
20 ns
+0.8 V
-0.5 V
- 2.0 V
20 ns
Figure 5. Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns
20 ns
Figure 6. Maximum Positive Overshoot Waveform
19
HY29F040A
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
Test Conditions
Min.
Max.
±1.0
50
Unit
mA
ILI
VIN = Vss to Vcc, Vcc = Vcc Max.
Vcc = Vcc Max., A9 = VID
VOUT = Vss to Vcc, Vcc = Vcc Max.
/CE = VIL, /OE = VIH
ILIT
A9 Input Load Current
Output Leakage Current
Vcc Active Current(1)
Vcc Active Current(2,3)
Vcc Standby Current
Input Low Level
mA
ILO
±1.0
40
mA
ICC1
ICC2
ICC3
VIL
VIH
mA
mA
mA
V
/CE = VIL, /OE = VIH
60
Vcc = Vcc Max., /CE = VIH
1.0
-0.5
2.0
0.8
Input High Level
Vcc
+ 0.5
V
VID
Voltage for Electronic ID
and Sector Protect
Vcc = 5.0 V
11.5
12.5
0.45
V
V
V
V
VOL
VOH
VLKO
Output Low Voltage
IOL = 12 mA, Vcc = Vcc Min.
IOH = -2.5 mA, Vcc = Vcc Min.
Output High Voltage
Low Vcc Lock-Out Voltage
2.4
3.2
4.2
Notes:
1. The Icc current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is less than 1 mA/MHz, with /OE at VIH.
2. Icc active while Internal Algorithm (program or erase) is in progress.
3. Not 100% tested.
20
HY29F040A
DC CHARACTERISTICS (continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Load Current
VIN = Vss to Vcc, Vcc = Vcc Max.
Vcc = Vcc Max., A9 = VID
±1.0
mA
ILIT
A9 Input Load Current
Output Leakage Current
Vcc Active Current(1)
Vcc Active Current(2,3)
Vcc Standby Current
Input Low Level
50
±1.0
40
mA
mA
mA
mA
mA
V
ILO
VOUT = Vss to Vcc, Vcc = Vcc Max.
/CE = VIL, /OE = VIH
ICC1
ICC2
ICC3
VIL
VIH
/CE = VIL, /OE = VIH
60
Vcc = Vcc Max., /CE = Vcc ± 0.5V
5.0
-0.5
0.7x
Vcc
0.8
Input High Level
Vcc
+ 0.3
V
VID
Voltage for Electronic ID
and Sector Protect
Vcc = 5.0 V
11.5
12.5
0.45
V
V
V
VOL
Output Low Voltage
Output High Voltage
IOL = 12 mA, Vcc = Vcc Min.
IOH = -2.5 mA, Vcc = Vcc Min.
VOH1
0.85x
Vcc
Vcc
-0.4
3.2
VOH2
IOH = -100 mA, Vcc = Vcc Min.
V
V
VLKO
Low Vcc Lock-out Voltage
4.2
Notes:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 1 mA/MHz, with /OE at VIH.
2. Icc active while Internal Algorithm (program or erase) is in progress.
3. Not 100% tested.
21
HY29F040A
AC CHARACTERISTICS
Read Only Operations
Parameter Symbol
JEDEC Standard
Description
Test Setup
-55(1)
-70(2)
-90(2)
-120(2) - 150(2)
Unit
tAVAV
tRC
Read Cycle Time(3)
Address to
Min.
55
55
70
70
90
90
120
120
150
150
ns
n s
tAVQV
tACC
/CE = VIL
/OE = VIL
/OE = VIL
Max.
Max.
Max.
Max.
Output Delay
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tCE
tOE
tHZ
tDF
tOH
Chip Enable to
Output Delay
55
25
18
18
0
70
30
20
20
0
90
35
20
20
0
120
50
30
30
0
150
55
35
35
0
n s
n s
n s
ns
ns
Output Enable to
Output Delay
Chip Enable to
Output High Z(3,4)
Output Enable to
Output High Z(3,4)
Output Hold Time
from Addresses,
/CE or /OE,
Min.
Whichever
Occurs First
Notes:
1. Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
2. Test Conditions:
3. Output driver disable time.
4. Not 100% tested.
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 20 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level
Input: 0.8 and 2.0 V
Output: 1.5 V
Output: 0.8 and 2.0 V
22
HY29F040A
5.0 V
2.7 KOhm
IN30 64 or
Equivalent
DEVICE
UNDER
TEST
C
L
Diodes = IN3064
or Equivalent
6.2 KOhm
Notes:
1. For -55: CL = 30pF including jig capacitance.
2. For all others: CL = 100pF including jig capacitance.
Figure 7. Test Condition
23
HY29F040A
AC CHARACTERISTICS
Programming/Erase Operations
Parameter Symbols
JEDEC Standard Description
-55
-70
-90
-120
-150
Unit
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
tWC
tAS
Write Cycle Time(1)
Address Setup Time
Address Hold Time
Data Setup Time
Min.
Min.
Min.
Min.
Min.
Min.
55
0
70
0
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
tAH
40
25
0
45
30
0
45
45
0
50
50
0
50
50
0
tDS
tDH
Data Hold Time
tOES
tOEH
Output Enable Setup Time
0
0
0
0
0
Output
Read(1)
Min.
Min.
0
0
0
0
0
ns
ns
Enable
Toggle Bit &
/Data Polling(1)
10
10
10
10
10
Hold Time
tGHWL
tELWL
tGHWL
Read Recover Time Before Write Min.
0
0
0
0
0
ns
tCS
tCH
/CE Setup Time
Min.
Min.
Min.
Min.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Min.
Min.
0
0
0
0
0
0
0
0
0
0
ns
ns
t
/CE Hold Time
WHEH
tWLWH
tWP
Write Pulse Width
30
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
tWHWL
tWPH
tWHWH1
Write Pulse Width High
Byte Programming Operation
ns
tWHWH1
ms
1.0
1.0
15
8
1.0
1.0
15
8
1.0
1.0
15
8
1.0
1.0
15
8
1.0
1.0
15
8
m s
sec
sec
sec
sec
ms
tWHWH2
tWHWH2
Sector Erase Operation
Chip Erase Operation
Vcc Setup Time(1)
tWHWH3
tWHWH3
120
50
500
4
120
50
500
4
120
50
500
4
120
50
500
4
120
50
500
4
tVCS
tVIDR
tOESP
tVLHT
tWPP1
tWPP2
tCSP
(1,2)
Rise Time to VID
ns
/OE Setup Time to /WE Active(1,2) Min.
ms
Voltage Transition Time(1,2)
Min.
Min.
4
4
4
4
4
ms
Sector Protect Write Pulse Width(2)
100
10
4
100
10
4
100
10
4
100
10
4
100
10
4
ms
Sector Unprotect Write Pulse Width(2) Min.
/CE Setup Time to /WE Active(1, 2) Min.
m s
ns
Notes:
1. Not 100% tested.
2. These timings are for Sector Protect and/or Sector Unprotect operations.
24
HY29F040A
SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be Steady
Will Be Steady
May Change
from H to L
Will Be Changing
from H to L
May Change
from L to H
Will Be Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing, State
Unknown
Does Not
Apply
Center Line is
High Impedance
“Off” State
tRC
Addresses
CE
Address Stable
tACC
tHZ
tOE
OE
tDF
tOEH
WE
tCE
tOH
High Z
High Z
Outputs
Output Valid
Figure 8. AC Waveforms for Read Operations
25
HY29F040A
SWITCHING WAVEFORMS
Data Polling
PA
5555H
tWC
PA
Addresses
CE
tAH
tAS
tGHWL
OE
tWP
tWHWH1
WE
tWPH
tCS
tDH
Data
DOUT
A0H
PD
DQ7
tDS
5.0V
VCC
GND
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. /DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 9. AC Waveforms Program Operations
26
HY29F040A
SWITCHING WAVEFORMS
tAS
tAH
5555H
2AAAH
5555H
5555H
2AAAH
SA
Addresses
CE
tGHWL
OE
tWP
WE
tWPH
tCS
tDH
Data
AAH
55H
80H
AAH
55H
10H/30H
tDS
tVCS
5.0V
VCC
GND
Notes:
1. SA is the sector address for Sector Erase. Address = X = Don’t Care for Chip Erase.
Figure 10. AC Waveforms Chip/Sector Erase Operations
27
HY29F040A
SWITCHING WAVEFORMS
tC H
C E
O E
tDF
tO E
tO E H
W E
tC E
tO H
H igh
Z
DQ 7
DQ 7
DQ 7=Valid Data
tW HW H
1 o r 2
Data
DQ 0-DQ 7
Valid Data
D Q0-D Q6= Invalid
DQ 0-DQ 6
tO E
5.0V
C C
V
GN D
Notes:
1. DQ7 = Valid Data (The device has completed the internal program or erase operation.)
Figure 11. AC Waveforms for /Data Polling during Internal Algorithm Operations
28
HY29F040A
SWITCHING WAVEFORMS
C E
tO E H
W E
tO E S
O E
Data
(D Q0-D Q7)
D Q 6 =
S top Tog gling
DQ 0-DQ 7
V alid
Data
DQ 6 = Toggle
DQ 6 = Toggle
tO E
5.0V
VC C
G N D
Notes:
1. DQ6 stops toggling (The device has completed the internal program or erase operation)
Figure 12. AC Waveforms for Toggle Bit during Internal Algorithm Operations
29
HY29F040A
STA R T
Set U p S ector Ad dress
(A1 8, A 17, A 16)
PLS C N T = 1
A9 = V ID
/O E = V ID
/C E = V IL
Activate /W E P uls e
Tim e Ou t 10 0
µs
Pow e r D ow n /OE
/W E = V IH
/C E = /O E = V IL
A9 R em ains at V ID
Im p lem en t PLSC N T
Add res s = SA
A0 = V IL, A 1 = VIH , A 6 = VIL
N o
Re ad from Sec tor
N o
PL S C NT = 25
?
D ata = 01H
?
Ye s
Ye s
D e vic e F ailed
Prote ct
Ye s
Another S ector?
N o
Pow er D o wn A 9
Sec tor P ro tec t C om ple te
Figure 13. Sector Protection Algorithm
30
HY29F040A
SWITCHING WAVEFORMS
A18
A17
A16
SAX
SAY
12V
A9
tVLHT
tVLHT
12V
OE
CE
tVLHT
t CSP
tWPP1
WE
A0
A1
A6
Data
O1H
tOE
5.0V
VCC
GND
Notes:
1. SAX = Sector Address for initial sector
2. SAY = Sector Address for next sector
Figure 14. AC Waveforms for Sector Protection
31
HY29F040A
Start
Protect All Sectors
PLSCNT = 1
Set Up Sector Unprotect Mode
A6 = A12 = A16 = VIH
A9 = VID
/CE = VID
/OE = VID
Activate /WE Pulse
Time Out 10 ms
Increment PLSCNT
/WE = VIH
/CE = /OE = VIL
A9 Remains at VID
Set Up Sector Address = SA0
A0 = VIL, A1 = VIH, A6 = VIH
No
Read Data from Device
Yes
No
Increment Sector Address
PLSCNT= 1000
?
Data = 00H
?
Yes
Yes
Sector
Address = SA7
?
No
Device Failed
Yes
Power Down A9
Sector Unprotect Complete
Notes:
1. SA0 = Sector Address for initial sector
2. SA7 = Sector Address for the last sector
Figure 15. Sector Unprotect Algorithm
32
HY29F040A
SWITCHING WAVEFORMS
A6
A12
A16
SA0
12V
A9
tVLHT
12V
CE
tCE
tVLHT
12V
OE
tOESP
tVLHT
WE
tWPP2
A18
A17
SA0
A0
A1
Data
00H
5.0V
VCC
Notes:
1. Starts with SA0 and sequences to SA7.
2. See Figure 15 for details.
Figure 16. AC Waveforms for Sector Unprotect
33
HY29F040A
AC CHARACTERISTICS
Write / Erase / Program Operations
Alternate /CE Controlled Writes
Parameter
Symbols
JEDEC
tAVAV
Standard Description
tWC
Write Cycle Time(1)
tAS
-55
55
0
-70
70
0
-90
90
0
-120
120
0
-150
150
0
Unit
ns
Min.
Min.
Min.
25
tAVEL
Address Setup Time
Address Hold Time
Data Setup TimeMin.
Data Hold Time
ns
tELAX
tAH
40
30
0
45
45
0
45
50
0
50
50
0
50
ns
0
ns
tDVEH
tEHDX
tDS
tDH
tOES
tOEH
Min.
Min.
Min.
ns
ns
ns
Output Enable Setup Time
0
0
0
0
0
Output
Read(1)
0
0
0
0
0
Enable
Toggle Bit and
/Data Polling(1)
Min.
10
10
10
10
10
ns
Hold Time
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tGHEL
tWS
tWH
tCP
Read Recover Time Before Write
/WE Setup Time
Min.
Min.
Min.
Min.
Min.
Typ.
0
0
0
0
0
0
0
0
0
0
ns
ns
/WE Hold Time
0
0
0
0
0
ns
/CE Pulse Width
30
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
tCPH
/CE Pulse Width High
Byte Programming Operation
ns
tWHWH1 tWHWH1
ms
Max. 1.0
Typ.
Max. 15
Typ.
Max. 120
Min. 50
Min. 500
1.0
1
1.0
1
1.0
1
1.0
1
ms
sec
sec
tWHWH2 tWHWH2
Sector Erase Operation(2)
Chip Erase Operation(2)
1
15
15
15
15
tWHWH3 tWHWH3
8
8
120
50
500
4
8
120
50
500
4
8
120
50
500
4
8
120
50
500
4
sec
sec
ms
tVCS
VCC Set Up Time(1)
(1,2)
tVIDR
tCESP
tVLHT
tWPP1
tWPP2
tCSP
Rise Time to VID
ns
/OE Setup Time to /WE Active(1,2) Min.
Voltage Transition Time(1,2)
Min.
4
4
ms
4
4
4
4
ms
Sector Protect Write Pulse Width(2) Min. 100
100
10
4
100
10
4
100
10
4
100
10
4
ms
Sector Unprotect Write Pulse Width(2) Min.
/CE Setup Time to /WE Active(1,2)
Min.
10
4
ms
ns
Notes:
1. Not 100% tested.
2. These timings are for Sector Protect and/or Sector Unprotect operations.
34
HY29F040A
SWITCHING WAVEFORMS
Data Polling
5555H
tWC
PA
PA
Addresses
WE
tAH
tAS
tGHEL
OE
tCP
tWHWH1
CE
tCPH
tWS
tDH
AOH
PD
DQ7
DOUT
Data
tDS
VCC
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 17. Alternate /CE Controlled Program Operation Timings
35
HY29F040A
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Limits
Typ.
1.0
8
Unit
Min.
Max.
15
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time
sec
sec
120
1000
25
7
ms
7
sec
Erase/Program Cycles
100,000
1,000,000
cycles
LATCH UP CHARACTERISTICS
Parameter
Min.
Max.
Input Voltage with respect to Vss on all I/O pins
Vcc Current
-1.0V
Vcc + 1.0V
+ 100 mA
-100 mA
Notes:
1. Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
PDIP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
CIN
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
4
8
8
6
pF
pF
pF
12
12
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 Mhz
PLCC PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
CIN
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
4
8
8
6
pF
pF
pF
12
12
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 Mhz
TSOP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
VIN = 0
Typ.
6
Max.
7.5
12
Unit
pF
CIN
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
36
HY29F040A
DATA RETENTION
Parameter
Test Conditions
150OC
Minimum
Unit
Minimum Pattern Data Retention Time
10
20
Years
Years
125OC
37
HY29F040A
PACKAGE DRAWINGS - Physical Dimensions
TSOP32
0.95
32-Pin Standard Thin Small Outline Package (measured in millimeters)
1.05
Pin 1 I.D.
1
17
7.90
8.10
0.50 BSC
16
32
18.30
18.50
0.05
0.15
19.80
20.20
.0.08
.0.20
1.20
MAX
.0.18
.0.21
0o
5o
0.25MM (0.0098") BSC
.015
.060
PDIP32
32-Pin Plastic DIP (measured in inches)
1.640
1.680
.600
.625
32
17
16
.530
.580
.008
.015
Pin 1 I.D.
.630
.700
0O
10O
.005 MIN
.045
.065
.140
.225
.040
.225
SEATING PLANE
.015
.060
.120
.160
.090
.110
.014
.022
38
HY29F040A
PACKAGE DRAWINGS - Physical Dimensions
PLCC32
32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
Pin 1 I.D
.
.042
.056
.585 .547
.595 .553
.125
.140
.080
.095
SEATING
PLANE
.400
REF
.013
.021
.490
.530
.026
.032
.050 REF.
TOP VIEW
SIDE VIEW
39
HY29F040A
ORDERING INFORMATION
Hyundai products are available in several packages and operating ranges.
The order number (Valid Combination) is formed by a combination of the following:
HY29F040A
X
– X
X
X
SPECIAL INSTRUCTIONS
TEMPERATURE RANGE
Blank = Commercial (0OC to +70OC)
I
=
Industrial (–40OC to +85OC)
E = Extended (–55OC to +125OC)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
PACKAGE TYPE
P = 32-Pin Plastic DIP (PDIP)
C = 32-Pin Rectangular Plasteic Leaded
Chip Carrier (PLCC)
T = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout
R = 32-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
DEVICE NUMBER/DESCRIPTION
HY29F040A
4 Megabit (512K x 8-Bit) CMOS 5.0 volt-only.
Sector Erase Flash Memory.
VALID COMBINATIONS
P-55, C-55, T-55, R-55
55ns
P-55I, C-55I, T-55I, R-55I
P-55E, C-55E, T-55E, R-55E
P-70, C-70, T-70, R-70
P-70I, C-70I, T-70I, R-70I
P-70E, C-70E, T-70E, R-70E
70ns
90ns
VALID COMBINATIONS
Valid Combinations List configurations planned to
be supported in volume for this device. Consult the
local Hyundai sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
P-90, C-90, T-90, R-90
P-90I, C-90I, T-90I, R-90I
P-90E, C-90E, T-90E, R-90E
P-12, C-12, T-12, R-12
120ns
150ns
P-12I, C-12I, T-12I, R-12I
P-12E, C-12E, T-12E, R-12E
P-15, C-15, T-15, R-15
P-15I, C-15I, T-15I, R-15I
P-15E, C-15E, T-15E, R-15E
40
HY29F040A
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