HY29F040C-12E [HYNIX]
Flash, 512KX8, 120ns, PQCC32, PLASTIC, LCC-32;
| 型号： | HY29F040C-12E |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Flash, 512KX8, 120ns, PQCC32, PLASTIC, LCC-32 |
| 文件： | 总40页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY29F040 Series
512K x 8-bit CMOS, 5.0 Volt-only, Sector Erase Flash Memory
KEY FEATURES
•
•
Sector Protection
•
•
•
5.0 V ± 10% Read, Program, and Erase
- Minimizes system-level power requirements
High performance
- 90 ns access time
Low Power Consumption
- 20 mA typical active read current
- 30 mA typical program/erase current
Compatible with the JEDEC Standard for
Single-Voltage Flash Memories
- Uses software commands, pinouts, and
packages following the industry standards
for single power supply Flash memories
- Superior inadvertent write protection
Flexible Sector Architecture
- Any sector may be locked to prevent any
program or erase operation within that sector
Erase Suspend/Resume
- Suspends a sector erase operation to allow
data to be read from, or programmed into,
any sector not being erased
- The erase operation can then be resumed
Internal Erase Algorithm
- Automatically erases a sector, any combination
of sectors, or the entire chip
•
•
•
Internal Programming Algorithm
- Automatically programs and verifies data at a
specified address
•
- Eight equal size sectors of 64K bytes each
- Any combination of sectors can be erased
concurrently
•
•
Minimum 100,000 Program/Erase Cycles
PLCC, PDIP and TSOP Packages
- Supports full chip erase
DESCRIPTION
latch addresses and data needed for the pro-
gramming and erase operations.
The HY29F040 is a 4 Megabit, 5.0 volt-only, CMOS
Flash memory device organized as 524,288
(512 K) bytes of 8 bits each. The Flash memory
array is organized into eight uniform-sized sec-
tors of 64 Kbytes each. The device is offered
with access times of 90, 120 and 150 ns and is
provided in standard 32-pin PDIP, PLCC and
TSOP packages. It is designed to be pro-
grammed and erased in-system with a 5.0 volt
power-supply and can also be reprogrammed
in standard PROM programmers.
The HY29F040 is programmed by invoking the
program command sequence. This starts the
internal byte programming algorithm that auto-
matically times the program pulse width and
verifies the proper cell margin. An erase opera-
tion is performed likewise, by invoking the sec-
tor erase or chip erase command sequence.
This starts the internal erasing algorithm that
automatically preprograms the sector (if it is not
already programmed), times the erase pulse
width and verifies the proper cell margin. Sec-
tors of the HY29F040 Flash memory array are
electrically erased via Fowler-Nordheim tunnel-
ing. Bytes are programmed one byte at a time
using a hot electron injection mechanism.
The HY29F040 has separate chip enable (/CE),
write enable (/WE) and output enable (/OE) con-
trols. Hyundai Flash memory devices reliably
store memory data even after 100,000 program/
erase cycles.
The device is entirely pin and command set
compatible with the JEDEC standard for 4 Mega-
bit Flash memory devices. Commands are writ-
ten to an internal command register using stan-
dard microprocessor write timings. Register
contents serve as inputs to an internal state-
machine which controls the erase and pro-
gramming circuitry. Write cycles also internally
The HY29F040 features a flexible sector erase
architecture. The device memory array is divided
into eight sectors of 64K bytes each. The sec-
tors can be erased individually or in groups with-
out affecting the data in other sectors. The mul-
tiple sector erase and full chip erase capabili-
ties provide flexibility in altering the data in the
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licences are implied.
Rev.04: April 1998
Hyundai Semiconductor
device. To protect data in the device from acci- power supply for read, program and erase
dental program and erase, the device has a operations. Internally generated and regulated
sector protect function which hardware write voltages are provided for the program and erase
protects selected sectors. The sector protect and operations. A low VCC detector inhibits write op-
sector unprotect features can be enabled in a erations during power transitions. End of pro-
PROM programmer.
gram or erase is detected by /Data Polling of
DQ7 or by the Toggle Bit feature on DQ6. Once
The HY29F040 requires only a single five-volt the program or erase cycle is successfully
completed, the device internally resets to the
Read mode.
BLOCK DIAGRAM
DQ[7:0]
STATE
CONTROL
ERASE VOLTAGE
I/O BUFFERS
GENERATOR AND
DQ[7:0]
COMMAND
SECTOR SWITCHES
REGISTER
/WE
I/O CONTROL
/CE
ELECTRONIC
ID
DATA LATCH
/OE
PROGRAM
VOLTAGE
GENERATOR
Y-DECODER
X-DECODER
Y-GATING
V
SS
4 Mbit FLASH
MEMORY
ARRAY
V
V
DETECTOR
TIMER
CC
CC
(8 x 512 Kbit
Sectors)
A[18:0]
PIN DESCRIPTIONS
LOGIC SYMBOL
19
8
Pin Name
A[18:0]
DQ[7:0]
/CE
Pin Function
A[18:0]
/CE
DQ[7:0]
Address Inputs
Data Input/Output
Chip Enable
/OE
/OE
Output Enable
Write Enable
/WE
/WE
VSS
Device Ground
VCC
Device Power Supply
2
HY29F040
PIN CONNECTIONS
A11
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
/OE
A10
/CE
A8
3
A13
A14
A17
/WE
4
DQ7
DQ6
DQ5
DQ4
DQ3
5
6
7
V
8
CC
Standard
TSOP-32
A18
A16
A15
9
V
SS
10
11
DQ2
DQ1
A12
A7
12
13
21
20
DQ0
A0
A6
A5
A4
14
15
16
19
18
17
A1
A2
A3
1
2
3
4
5
6
7
32
A11
A9
/OE
A10
/CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
31
30
29
28
27
26
A8
A13
A14
A17
/WE
VCC
A18
A16
A15
A12
A7
8
9
25
24
Reverse
TSOP-32
10
11
12
13
14
15
16
23
22
21
20
19
18
17
DQ2
DQ1
DQ0
A0
A6
A1
A5
A2
A4
A3
A18
A16
A15
A12
A7
1
2
V
CC
32
31
30
/WE
A17
A14
A13
A8
3
4
29
28
27
26
25
24
23
22
21
20
A7
A6
A5
A4
A3
A2
5
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A14
A13
A8
A6
6
A5
7
A9
A9
A4
8
A11
/OE
A10
/CE
PLCC-32
A11
/OE
A10
/CE
DQ7
A3
9
PDIP-32
10
11
12
13
A2
10
11
A1
A0
A1
A0
DQ0
DQ1
DQ2
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
19
18
17
V
SS
3
HY29F040
BUS OPERATIONS
Table 1. Bus Operations (1)
OPERATION
/CE /OE
/WE
H
X
A0
A0
X
A1
A1
X
A6
A6
X
A9
A9
X
DQ[7:0]
DOUT
Read (2)
L
H
L
L
X
Standby
High Z
High Z
Output Disable
H
H
L
X
X
X
X
(6)
Write
L
H
A0
X
A1
X
A6
L
A9
VID
VID
VID
VID
VID
DIN
Sector Protect (3)
Sector Unprotect (4)
Verify Sector Protect
Electronic ID Manufacturer Code (5)
Electronic ID Device Code (5)
L
VID
VID
L
L
X
VID
L
L
X
X
H
X
H
H
H
L
H
L
Code Out
Code Out
Code Out
L
L
L
L
L
L
L
H
L
L
Notes:
1. L = VIL, H = VIH, X = Dont Care. See DC Characteristics for voltage levels.
2. /WE can be VIL if /CE is VIL. However, if /OE goes to VIH it will initiate a write operation.
3. See Figures 1 and 15 for addittional information
4. See Figures 2 and 16 for additional information.
5. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 4.
6. Refer to Table 4 for valid DIN during a write operation.
Table 2. Electronic ID and Sector Protection Codes (1)
Code
Manufacturer ID
Device ID
A18 A17 A16 A9 A6 A1 A0
Output on DQ[7:0] in Hex
X
X
X
X
X
X
VID
VID
VIL VIL
VIL VIL
VIL
VIH
Hyundai:
ADh
HY29F040: 40h
Sector
Protected:
01h
Protection State Sector Address VID
VIL VIH
VIL
Unprotected: 00h
Notes:
1. Address inputs A[15:10], A[8:7] and A[5:2] are don't care.
4
HY29F040
Table 3. Sector Addresses
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A18
0
A17
0
A16
0
Address Range
00000H - 0FFFFH
10000H - 1FFFFH
20000H - 2FFFFH
30000H - 3FFFFH
40000H - 4FFFFH
50000H - 5FFFFH
60000H - 6FFFFH
70000H - 7FFFFH
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
current until the programming or erase operation is
completed.
Read Mode
The HY29F040 has three control functions
which must be satisfied in order to obtain data
at the DQ[7:0] outputs. /CE is the power control
and is used for device selection. /OE is the out-
put control and is used to gate data to the out-
puts when a device is selected. As shown in
Table 1, /WE should be held at VIH, except in
Write mode and Enable Sector Protect/Unprotect
modes.
Output Disable Mode
With the /OE input at a logic High level (VIH), out-
puts from the device are disabled and the DQ[7:
0] pins are placed in a high impedance state.
Note, as shown in Table 1, that Write opera-
tions are possible while in this state if /WE is
brought Low.
Program and Erase Modes
Address access time (tACC) is equal to the delay
from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from
stable addresses and stable /CE to valid data
at the output pins. The output enable access
time is the delay from the falling edge of /OE to
valid data at the output pins (assuming the ad-
dresses have been stable for at least tACC - tOE).
Device programming and erase are accom-
plished via the command register. The contents
of the register serve as inputs to the internal
state machine. Outputs from the state machine
dictate the function of the device. Commands
are detailed in the Command Definitions sec-
tion of this document.
The command register itself does not occupy
any addressable memory locations. The regis-
ter is a latch used to store the commands along
with the address and data information needed
to execute a particular command. The com-
mand register is written by bringing /WE to VIL,
while /CE is at VIL and /OE is at VIH. Addresses
are latched on the falling edge of /WE or /CE,
whichever happens later, while data is latched
on the rising edge of /WE or /CE, whichever
happens first. Standard microprocessor write
timings are used. Refer to the AC Characteris-
Standby Mode
The HY29F040 has two standby modes: a
CMOS standby mode (/CE input held at VCC ± 0.
5V), when current consumed is typically less
than 60 µA; and a TTL standby mode (/CE is
held at VIH) when the typical current required is
reduced to 300 µA. In standby mode, outputs
are in a high impedance state, independent of
the /OE input.
If the device is deselected during programming
or erase, the device will continue to draw active
5
HY29F040
tics for Programming/Erase and their respec-
tive Timing Waveforms for specific timing
parameters.
dresses ([A18:16]) while A[6, 1, 0] = (0, 1, 0) will
produce a 01h on DQ[7:0] for a protected sector
and a 00h for an unprotected sector. It is also
possible to determine if a sector is protected
in-system by invoking the Electronic ID com-
mand as described in the Command Defini-
tions section below.
Enable, Disable and Verify Sector
Protect Modes
The HY29F040 Flash array is implemented as
eight sectors of 64 Kbytes each (see Table 3).
The device contains a hardware Sector Protect
feature that disables both programming and
erase operations in protected sectors. Sector
protection is typically enabled using program-
ming equipment at the users site, since a high
voltage on two pins is required for this opera-
tion (see Table 1). The device is shipped from
Hyundais factory with all sectors unprotected.
The HY29F040 also features a Sector Unprotect
operation, so that a protected sector may be
unprotected to incorporate any changes in the
code. Protecting all sectors is necessary be-
fore unprotecting any sector(s). Sector
unprotection is usually accomplished using a
PROM programmer. See Figures 2 and 16 for
details of implementing Sector Unprotect.
Electronic ID Mode
To activate the Sector Protect mode, the user
must place VID on the A9 and /OE inputs. Ad-
dress inputs A[18:16] should be set to the ad-
dress of the sector to be protected, as speci-
fied in Table 3. Programming of the protection
circuitry starts on the falling edge of the /WE
pulse and is terminated with the rising edge of
/WE. Sector addresses must be held fixed during
the /WE pulse. The procedure should be re-
peated for each sector that is to be protected.
Figure 1 illustrates the sector protection
algorithm, and Figure 15 provides the timing
information for this operation.
The Electronic ID mode allows the host to read
a binary code from the device that identifies its
manufacturer and the device type. This mode is
intended for use by programming equipment
for the purpose of automatically matching the de-
vice to be programmed with its corresponding
programming algorithm.
To activate this mode, the programming equip-
ment places VID on address pin A9 and sets A
[6, 1] = (0, 0). Two identifier bytes may then be
read from the device by toggling address A0
from VIL to VIH. See Table 2.
The manufacturer and device codes may also
be read via the command register without the
requirement for high voltage on the A9 pin. The
command sequence is illustrated in Table 4
(refer to Electronic ID Command section below).
To verify programming of the protection circuitry,
the programming equipment must force VID on
A9 with /CE and /OE at VIL and /WE at VIH. As
shown in Table 2, scanning the sector ad-
Byte 0 (A0 = VIL) represents the manufacturers
code (Hyundai Electronics = ADh) and byte 1
(A0 = VIH) the device identifier code (HY29F040
= 40h). All identifiers for manufacturer and de-
vice will exhibit odd parity with the MSB (DQ7)
defined as the parity bit.
6
HY29F040
Start
Set Up Sector Addr.
(A18,A17,A16)
PLSCNT=1
/OE=VID,A9=VID
/CE=VIL,
A1 = VIL
Activate /WE Pulse
Time Out 100us
Increment
PLSCNT
/WE=VIH,/CE=/OE=VIL
(remain A9=VID
)
Read from Sector
Addr.(A18,A17,A16)
A1= VIH, A0=A6= VIL
NO
NO
PLSCNT
=25
?
Data=01H
?
YES
YES
YES
Protect
Another Sector ?
NO
Power Down A9
Device Failed
Sector Protection
Complected
Figure 1. Sector Protection Algorithm
7
HY29F040
Start
Protect All Sectors
PLSCNT=1
Set Up Sector Unprotect Mode
A6 = A12 = A16 = VIH
Set A9 = /CE = /OE = VID
Activate /WE Pulse
Time Out 10ms
Increment
PLSCNT
Set /WE = VIH, /CE = /OE = VIL
A9 = VID
Sector Address A[18:16] = 000
A0 = VIL, A1 = A6 = VIH
Read Data from Device
NO
NO
PLSCNT
=1000
?
Data=00H
?
Increment Sector Address
YES
YES
NO
Sector
Address = 111
YES
Power Down A9
Device Failed
Sector Unprotection
Complected
Figure 2. Sector Unprotect Algorithm
8
HY29F040
COMMAND DEFINITIONS
Device operations are invoked by writing spe- will reset the device (when applicable).
cific address and data sequences into the Com-
mand register. Table 4 defines the valid com- Writing incorrect addresses and data values or
mand sequences. Either Read/Reset command writing them in the improper sequence will re-
set the device to the Read mode.
(1, 2 ,3 ,4)
Table 4. Command Definitions
Bus
First Bus
Second Bus
Write Cycle
Third Bus
Fourth Bus
Write Cycle
Fifth Bus
Sixth Bus
Command
Sequence
Cycles
Req'd.
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read/Reset(5)
Read/Reset(6)
Electronic ID (6)
2
4
4
XXXH
5555H
5555H
F0H
AAH
AAH
RA
RD
55H
55H
2AAAH
2AAAH
5555H F0H
5555H 90H
RA
RD
ADH
40H
PD
XX00H
XX01H
PA
Byte Program
Chip Erase
4
6
6
1
1
5555H
5555H
5555H
XXXH
XXXH
AAH
AAH
AAH
B0H
30H
2AAAH
2AAAH
2AAAH
55H
55H
55H
5555H A0H
5555H 80H
5555H 80H
5555H
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
SA
10H
30H
Sector Erase
Erase Suspend
Erase Resume
Notes:
1. Bus Operations are defined in Table 1.
2. RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the /WE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of /WE.
SA = A[18:16] = address of the sector to be erased (see Table 3).
3. Address bits A[18:15] = X = Dont Care for all cycles except for Read Address (RA), Program Address (PA) and Sector
Address (SA). For SA, A[18:16] = Sector Address and A15 is a Don't Care.
4. The Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation
is in progress.
5. The second bus cycle is a read cycle.
6. The fourth bus cycle is a read cycle
9
HY29F040
the operation, it is necessary to write the Read/
Reset command sequence into the command
register.
Read/Reset Command
The read or reset operation is initiated by writing
the Read/Reset command sequence into the
command register. In the Read/Reset mode,
standard microprocessor read cycles retrieve the
data from the Flash memory. The device remains
enabled for reads until the command register
contents are changed.
Byte Program Command
The HY29F040 is programmed one byte at a time.
Byte programming is allowed in any sequence,
and across sector boundaries. However, a bit
whose current contents are a 0 cannot be pro-
grammed to a 1". Only erase operations can
convert a logic 0" to a logic "1. Attempting to
program data from 0 to 1 will cause the de-
vice to exceed time limits, and may result in fail-
ure of the /Data Polling test (see below).
The device will automatically power-up in the
Read/Reset mode and thus a Read/Reset com-
mand sequence is not needed to read the
memory data immediately after power-up. This
default power-up to Read mode ensures that no
spurious changes of the data will take place
during the power transitions. Refer to the AC
Characteristics for Read Operation and the re-
spective Timing Waveforms for the specific tim-
ing parameters.
As shown in Table 4, a programming operation
is invoked using a four bus-cycle command se-
quence. The program address (PA) is latched
on the falling edge of /CE or /WE of the fourth
cycle, whichever happens later, and program
data (PD) is latched on the rising edge of /CE or
/WE of that cycle, whichever happens first. That
same rising edge starts the execution of the
internal byte programming algorithm. The host
system is not required to provide further con-
trols or timings. The device will automatically
provide enough internally generated program
pulses to program the byte with the data pro-
vided and will verify the programmed cell mar-
gin of the byte. The HY29F040 will ignore any
commands written to the chip during execution
of the internal byte programming algorithm.
Electronic ID Command
The HY29F040 contains an Electronic ID com-
mand to supplement the PROM programming
equipment method described in the Bus Opera-
tions section. After writing the three-cycle Elec-
tronic ID command sequence, a read from ad-
dress xx00h retrieves the manufacturer code
(ADh.) and a read from address xx01h returns
the device code (40h) . All manufacturer and
device codes will exhibit odd parity with the MSB
(DQ7) defined as the parity bit.
Any read operation during the execution of the
internal programming algorithm will output the
complement of the program data on DQ7. This
feature is known as /Data ("Data Bar") Polling
and may be used to determine the status of the
operation. The internal programming algorithm
has completed its operation when the data on
DQ7 is equivalent to the data provided in the last
cycle of the program command sequence. At the
completion of the byte programming algorithm,
the device returns to the read mode and the ad-
dress pins are no longer latched. Therefore, the
system should perform the read operations for
the /Data Polling test using the last program ad-
dress to ensure that it reads the correct status
The Electronic ID command can also be used to
determine whether sectors are protected or un-
protected. After writing the three-cycle Electronic
ID command sequence, the CPU can input an
address consisting of the sector address in A
[18:16] and all other address bits Don't Care
except A[6, 1, 0] = (0, 1, 0). Protected sectors will
return 01h on the data outputs and unprotected
sectors will return 00h.
Once the Electronic ID command sequence is
written, the device will remain in that mode and
the host CPU can perform multiple read cycles to
obtain the data it requires (e.g., the Protect/
Unprotect status of several sectors). To terminate
10
HY29F040
START
Write Program Command Sequence
(see below)
/Data Polling Device
NO
Last Address
Increment Address
?
YES
Programming Completed
Program Command Sequence (Address/Command)
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Figure 3. Internal Programming Algorithm
11
HY29F040
data on DQ7.
Figure 2 illustrates the operation of chip erase
using typical command strings and bus opera-
tions.
Since a "0" cannot be changed to a "1" by
programming, the /Data Polling test will never
indicate completion of the programming algo-
rithm when attempting to do so on bit 7 of the
byte. The test will output a "0", the complement
of the new data, while the chip performs the in-
ternal programming algorithm. It then outputs
the actual cell data, which was and remains a
"0", when the programming algorithm times out.
A /Data Polling algorithm which accounts for this
possible error is presented in the Write Opera-
tions Status section below.
Sector Erase Command
Sector erase is a six bus cycle operation (see
Table 4). The sector address (any address within
the desired sector, see Table 3) is latched on
the falling edge of the last /WE pulse in the com-
mand sequence. On the rising edge of that pulse,
the state machine latches the command data
and starts an internal timer with a time period of
50 µs (minimum), during which time an addi-
tional sector to be erased can be specified (see
below). When the timer expires after the data for
the last sector to be erased is input to the device,
the HY29F040 executes an internal sector erase
algorithm. The system is not required to provide
further controls or timings. The device automati-
cally pre-programs any unprogrammed cells and
will then provide internally generated erase
pulses and verify erasure of the specified sec-
tors within the proper cell margins.
Figure 3 illustrates the byte programming op-
eration using typical command strings and bus
operations.
Chip Erase Command
Chip erase is a six bus cycle operation (see Table
4). The HY29F040s internal state machine ex-
ecutes an erase algorithm which starts on the
rising edge of the last /WE pulse in the com-
mand sequence. The system is not required to
provide further controls or timings. The device
automatically pre-programs any unprogrammed
cells and will then provide internally generated
erase pulses and verify chip erasure within the
proper cell margins. During chip erase, all sec-
tors of the device are erased except protected
sectors. The device will ignore any commands
written to the chip during execution of the inter-
nal chip erase algorithm.
As outlined above, the erasure of multiple sec-
tors can be specified by writing the sixth bus
cycle command of the Sector Erase command
for each sector to be erased (note, however, that
the state machine erases the sectors
sequentially). Loading the sector erase buffer
may be done in any sequence and with any num-
ber of sectors. The 100 µs sector erase buffer
timer resets and begins another time-out each
time another sector is specified, and starts the
actual erase operation when it times out. Thus,
the maximum time before the initiation of the
next Sector Erase command (falling edge of /
WE) must be less than 100 µs to guarantee ac-
ceptance of the command by the internal state
machine. The time-out window can be monitored
via DQ3, the Sector Erase Timer status pin (refer
to Write Operation Status section below). If mul-
tiple sectors are to be specified, it is recom-
mended that CPU interrupts be disabled during
this time to ensure that the subsequent Sector
Erase commands can be initiated within the 100
µs window. The interrupts can be re-enabled
While the chip erase algorithm is executing, any
data read from the device shows a 0 on data
bit DQ7. This is similar to /Data Polling. The
erase operation is completed when the data on
DQ7 changes to a 1 (see Write Operation Sta-
tus section). Upon completion of the chip erase
operation, the device returns to read mode and
the address pins are no longer latched. Thus, /
Data Polling must be performed at a sector ad-
dress within any of the sectors being erased
and not within a protected sector to ensure that
DQ7 returns a logical 1 upon completion of the
chip erase operation.
12
HY29F040
after the last Sector Erase command is written.
Erase Suspend and Erase Resume
Commands
If the Erase Suspend command is input during
the time-out period, the state machine immedi-
ately terminates the time-out, locks the sector
erase buffer and places the device in the read
mode. When the Erase Resume command is
issued subsequently, the erase operation itself
begins. Additional sectors for erasure cannot
be specified after the Erase Resume command
is input. If additional sectors require erasure, a
new Sector Erase command sequence for those
sectors must be initiated after the previously in-
voked sector erase operation is completed.
The Erase Suspend command allows the user
to interrupt a sector erase operation to read data
from, or program data into, a sector that is not
being erased. The Erase Suspend command is
applicable only during the sector erase operation,
including during the sector erase time-out pe-
riod after any Sector Erase commands (30h)
have been issued. The command will be ignored
if issued during a chip erase or byte program-
ming operation.
Writing the Erase Suspend command during the
sector erase time-out will result in immediate
termination of the time-out period. When the
Erase Suspend command is written while the
internal sector erase algorithm is in progress,
the chip will take between 1 µs and 410 µs to
suspend the erase operation and go into erase
suspended-read mode. The system can moni-
tor the /Data Polling (DQ7) or Toggle Bit (DQ6)
status flags to determine when the device has
entered erase suspend-read mode (see Write
Operation Status section). The system must use
an address of an erasing sector to monitor /
Data Polling or Toggle Bit to determine when
the sector erase operation has been
suspended. Once the host determines that the
device is in the erase suspend-read mode, it
may perform data reads from the device or ini-
tiate a byte programming operation. Any further
writes of the Erase Suspend command at this
time will be ignored.
Any command other than Sector Erase or Erase
Suspend during the time-out period will reset
the device to read mode, ignoring the previous
command string. In such case, the entire Sector
Erase sequence must be repeated to erase
those sectors. During execution of the internal
sector erase algorithm, only the Erase Suspend
and Erase Resume commands are permitted.
All other commands will be ignored.
When erasing a sector or multiple sectors, the
data in the unselected sectors remains
unaffected. Protected sectors of the device will
not be erased, even if they are specified with the
Sector Erase command.
While the sector erase algorithm is executing,
any data read from the device shows a 0 on
data bit DQ7. This is similar to /Data Polling.
The erase operation is completed when the data
on DQ7 changes to a 1 (see Write Operation
Status section). Upon completion of the sector
erase operation, the device returns to read mode
and the address pins are no longer latched.
Thus, /Data Polling must be performed at a sec-
tor address within any of the sectors being
erased and not within a protected sector to en-
sure that DQ7 returns a logical 1 upon comple-
tion of the sector erase operation.
To resume the sector erase operation, the Erase
Resume command should be written. Any further
writes of the Erase Resume command at this
point will be ignored. Another Erase Suspend
command can be written after the chip has re-
sumed the Sector Erase operation.
Figure 4 illustrates the Sector Erase Algorithm
using typical command strings and bus
operations.
13
HY29F040
Start
Write Erase Command Sequence
(see below)
/Data Polling or Toggle Bit
Successfully Completed
Erase Completed
Individual Sector/Multiple Sector
Chip Erase Command Sequence
(Address/Command)
Erase Command Sequence
(Address/Command)
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
Figure 4. Internal Erase Algorithm
14
HY29F040
WRITE OPERATION STATUS
Table 5. Write Operation Status Flags(1)
Status
DQ7
/DQ7
0
DQ6
Toggle
Toggle
N/A
DQ5
DQ3
DQ2
N/A
Byte Programming Operation
Chip or Sector Erase Operation
0
0
0
0
1
1
In
Progress
Toggle
Toggle
Erase
Suspend
Mode
Erase Suspended
Sector
Non-Erase
1
Data
Data
Data
Data
Data
Suspended Sector
Byte Programming Operation
Chip or Sector Erase Operation
Program in Erase Suspend Mode
/DQ7
0
Toggle
Toggle
Toggle
1
1
1
0
1
1
N/A
Toggle
N/A
Exceeded
Time
Limits
/DQ7
Notes:
1. DQ0, DQ1, DQ2 and DQ4 as status indicators are reserved for future use.
a valid sector erase command has been
recorded. As previously described, the sector
erase operation itself will not actually begin until
the expiration of the internal time-out window
after receipt of the last sector erase command.
For both chip erase and sector erase, /Data
Polling must be performed at an address within
any of the sectors being erased and not within
a protected sector. Otherwise, the /Data Polling
status may not be valid.
DQ7: /Data Polling
The HY29F040 features /Data Polling ("Data Bar
Polling") as a method to indicate to the host the
status of the byte programming, chip erase,
sector erase and erase suspend operations.
While the byte programming algorithm is in
progress, a read of the device will output the
complement of the data last written to DQ7 (that
is, the complement of the data being pro-
grammed into bit 7 of the byte). Upon comple-
tion of the byte programming operation, a de-
vice read at the address of the byte last pro-
grammed will output the true data last written to
DQ7.
When the host determines, by reading valid data
on DQ7, that the internal algorithm operation
has been completed, it should not rely on the
data on DQ[6:0] to be valid at the same time.
This is because the HY29F040 data pins may
change asynchronously while the output enable
(/OE) is asserted Low since the device is driving
status information on DQ7 (as well as DQ6,
DQ5 and DQ3, see below) at one instant of time
and valid data at the next instant of time. To en-
sure that the entire data byte read is valid, the host
should perform an additional read cycle after DQ7
indicates completion of the internal algorithm.
This is illustrated in the /Data Polling timing,
Figure 13.
While the chip erase or sector erase algorithm
is in progress, a read operation will produce a
logical 0 at the DQ7 output. Upon completion of
the chip erase or sector erase operation, or if the
device enters the Erase Suspend mode, a de-
vice read at an address within one of the erased
(or erase suspended) sectors will produce a
logical 1" at the DQ7 output. For chip erase, /
Data Polling is valid after the rising edge of the
sixth /WE pulse in the six cycle command se-
quence and indicates that the chip erase op-
eration is in progress. For sector erase, /Data
Polling is also valid after the rising edge of the
sixth /WE pulse in the six cycle command
sequence, but in this case it indicates only that
The DQ7 status indications are summarized in
Table 5. A flowchart for a /Data Polling algorithm
for the byte programming, chip erase and sec-
tor erase operations is shown in Figure 5. This
15
HY29F040
algorithm includes monitoring of DQ5 (see
below) to prevent an infinite loop in case of a
programming or erase failure.
DQ5: Exceeded Timing Limits
DQ5 will indicate if the Byte Programming, Chip
Erase, or Sector Erase time has exceeded the
internally controlled timing limits for the device. In
such an event, a read of the device data will pro-
duce a logical 1 on DQ5. This is a failure con-
dition which indicates that the program or erase
cycle was not successfully completed.
DQ6: Toggle Bit
The HY29F040 also features the Toggle Bit
as a method of indicating to the host system
the status of the Internal Programming and
Erase Algorithms. The DQ6 status indications
are summarized in Table 5.
If this failure condition occurs during a sector
erase or chip erase operation, it indicates that
one or more of the sectors selected for erasure
is defective. The operation should be repeated
for a single sector at a time if the host wishes to
determine which sector or sectors are defective.
Sectors which do not indicate failure are still
functional and may continue to be used.
While the internal programming or erase algo-
rithm is operating, successive reads of data from
the device at any address will result in DQ6 tog-
gling between one and zero. Once the internal
programming or erase operation is completed,
DQ6 will stop toggling and valid data will be read
on subsequent read cycles. ("Valid data" when
reading an erased sector after the erase cycle is
finished is a '1'). For byte programming, the
Toggle Bit is valid after the rising edge of the
fourth /WE pulse in the four cycle command se-
quence. For chip or sector erase, the Toggle Bit
is valid after the rising edge of the sixth /WE
pulse in the six cycle command sequence. The
Toggle Bit is also active during the sector
erase time-out window.
If this failure condition occurs during the byte
programming operation, the entire sector con-
taining that byte should be considered bad and
should not be used. Other sectors are still func-
tional and can be used.
The DQ5 failure condition may also appear if a
user tries to program a non-blank location with-
out first erasing it. In this case, the device may
exceed time limits and not complete the internal
algorithm operation. Hence, the system never
reads valid status data on DQ7 and DQ6 never
stops toggling. Once the device has exceeded
timing limits, the DQ5 bit will indicate a 1.
In the case of byte programming, if the sector be-
ing written to is protected, the Toggle Bit toggles
for about two µs and then stops toggling without
the data having changed. In chip erase or sector
erase operations, the device will erase all the
selected sectors except for sectors that are pro-
tected. If all the selected sectors are protected,
the chip will toggle the Toggle Bit for about 100
µs and will then return to read mode, having
changed none of the data. Either /CE or /OE
toggling will cause the DQ6 Toggle Bit to toggle.
In the case of an 'exceeded timing limits' (DQ5)
failure, the device does not automatically reset
to the read state. Thus, the host must issue a
Read/Reset Command sequence to the device
to continue to use the other sectors in the
device.
A flowchart for a Toggle Bit algorithm for the byte
programming, chip erase and sector erase op-
erations is shown in Figure 6. This algorithm
includes monitoring of DQ5 (see below) to pre-
vent an infinite loop in case of a programming
or erase failure. Figure 14 illustrates the timing
for the Toggle Bit operation.
DQ3: Sector Erase Timer
After the completion of the initial Sector Erase
Command sequence, the sector erase time-
out window will begin. DQ3 will remain low until
the time-out window is closed. /Data Polling and
16
HY29F040
START
VA = Byte address for a program
operation.
= Any address within the sectors
being erased for a sector erase
operation.
= Any address for a chip erase
operation.
Read Byte
(DQ0-DQ7), Addr = VA
YES
Test for DQ7 = 1 for a chip erase or
sector erase operation.
DQ7 = Data
?
NO
NO
DQ5 = 1
?
YES
Read Byte
(DQ0-DQ7), Addr = VA
Test for DQ7 = 1 for a chip erase or
sector erase operation.
YES
DQ7 = Data
?
NO
Fail
Pass
Notes:
1. DQ7 is rechecked even if DQ5 = logical 1 because DQ7 may change simultaneously with DQ5.
Figure 5. /Data Polling Algorithm
17
HY29F040
START
Read Byte(DQ0-DQ7)
Addr=VA
YES
DQ6=Data
?
NO
NO
DQ5=1
?
YES
Read Byte(DQ0-DQ7)
Addr=VA
YES
DQ6=Data
?
NO
Fail
Pass
Notes:
1. DQ6 is rechecked even if DQ5 = logical 1 because DQ6 may stop toggling at the same
time as DQ5 is changing to a logical 1".
Figure 6. Toggle Bit Algorithm
18
HY29F040
Toggle Bit are valid after the initial Sector Erase der this condition the device will reset to the
command sequence.
Read mode. Subsequent writes will be ignored
until the VCC level is greater than VLKO. It is the
If /Data Polling or the Toggle Bit indicates the users responsibility to ensure that the control
device has been written with a valid erase com- pins are logically correct to prevent unintentional
mand, DQ3 may be used to determine if the writes when VCC is above 3.2V.
sector erase time-out window is still open. If
DQ3 is a logical 1, the internally controlled
erase cycle has begun and attempts to write
additional sector erase commands to the de-
vice will be ignored until the erase operation is
completed. If DQ3 is a logical 0", the device
will accept additional sector erase commands.
To insure the command has been accepted,
the system software should check the status of
DQ3 prior to and following each subsequent
sector erase command. If DQ3 is High on the
second status check, the command may not
have been accepted. Refer to Table 5, Write Op-
eration Status Flags.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on /OE,
/CE or /WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of /OE =
VIL, /CE = VIH , or /WE = VIH. To initiate a write
cycle /CE and /WE must be a logic 0 while
/OE is a logic 1.
Power-Up Write Inhibit
Power-up of the device with /WE = /CE = VIL and
/OE = VIH will not accept commands on the rising
edge of /WE. The internal state machine is auto-
matically reset to Read mode on power-up.
DATA PROTECTION
The HY29F040 incorporates a number of
mechanisms designed to offer protection
against accidental erasure or programming.
During power-up, the device automatically re-
sets the internal state machine to the Read
mode. Also, alteration of the memory contents
through programming or erase operations occurs
only after successful completion of specific multi-
cycle command sequences, which are unlikely
to be invoked accidentally. These are described
in the Command Definitions section of this
document.
Sector Protection
Sectors of the HY29F040 may be hardware pro-
tected at the user's factory. The protection cir-
cuitry will disable both program and erase func-
tions for the protected sectors. Requests to pro-
gram or erase a protected sector will be ignored
by the device.
Sector protection is accomplished in a PROM
programmer. To activate this mode, program-
ming equipment must force VID on control pin /
OE and address pin A9. Sector addresses
should be set using the high address lines A
[18:16]. The protection mechanism begins on
the falling edge of the /WE pulse and is termi-
nated with the rising edge of /WE. See Figures
1 and 2 for details of implementing sector pro-
tection and unprotection.
The device also incorporates several features
to prevent inadvertent write cycles resulting from
VCC power-up and power-down transitions or
system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC
power-up and power-down, a write cycle is
locked out for VCC less than VLKO (specified as 3.
2V minimum, typically 3.7V). If VCC < VLKO, the
command register is disabled and all internal
programming/erase circuits are disabled. Un-
19
HY29F040
OPERATING RANGES
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Package .............................. -65°C to + 125°C
Ambient Temperature
With Power Applied ......................... -55°C to + 125°C
Voltage with Respect to Ground:
Commercial( C) Devices ................... 0°C to + 70°C
Industrial (I) Devices ....................... -40°C to + 85°C
Extended (E) Devices .................... -55°C to + 125°C
All pins except A9 (Note 1) ........... -2.0V to + 7.0V
VCC(1) ............................................... -2.0V to + 7.0V
A9(2) .............................................. -2.0V to + 14.0V
VCC Supply Voltage
VCC for HY29F040-90, -120, -150 ..... +4.5V to + 5.5V
Output Short Circuit Current(3) ....................... 200 mA
Notes:
Notes:
1. Operating ranges define those limits between which the
functionality of the device is guaranteed.
1. Minimum DC voltage on input or I/O pins is - 0.5V. During
voltage transitions, inputs may overshoot VSS to -2.0V for
periods of up to 20 ns. Maximum DC voltage on output
and I/O pins is VCC + 0.5V. During Voltage transitions,
outputs may overshoot to VCC + 2.0V for periods up to 20
ns.
2. Minimum DC input voltage on A9 pin is -0.5V. During
voltage transitions, A9 may overshoot VSS to -2.0V for
periods of up to 20 ns. Maximum DC input voltage on A9
is + 13.5V which may overshoot to 14.0V for periods of up
to 20 ns.
3. No more than one output shorted at a time. Duration of the
short circuit should not be greater than one second.
Stresses above those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. This is a stress rating only; functional opera-
tion of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure of the de-
vice to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
20
HY29F040
20 ns
20 ns
+0.8 V
-0.5 V
- 2.0 V
20 ns
Figure 7. Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive Overshoot Waveform
21
HY29F040
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
Test Conditions
Min.
Max.
Unit
ILI
VIN = Vss to VCC, VCC = VCC Max.
±1.0
µA
ILIT
ILO
ICC1
ICC2
A9 Input Load Current
Output Leakage Current
VCC Active Current(1)
VCC Active Current(2,3)
VCC = VCC Max., A9 = 12.5 V
VOUT = Vss to Vcc, VCC = VCC Max.
/CE = VIL, /OE = VIH
50
±1.0
40
µA
µA
mA
mA
/CE = VIL, /OE = VIH
60
ICC3
VIL
VIH
VCC Standby Current
Input Low Level
Input High Level
VCC = VCC Max., /CE = VIH
1.0
0.8
mA
V
-0.5
2.0
VCC
+
V
0.5
VID
Voltage for Electronic ID
and Sector Protect
VCC = 5.0 V
11.5
12.5
0.45
V
V
V
V
VOL
VOH
VLKO
Output Low Voltage
Output High Voltage
IOL = 12 mA, VCC = VCC Min.
IOH = -2.5 mA, VCC = VCC Min.
2.4
3.2
Low VCC Lock-Out Voltage
4.2
Notes:
1. The Icc current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is less than 2 mA/MHz, with /OE at VIH.
2. Icc active while Internal Algorithm (program or erase) is in progress.
3. Not 100% tested.
22
HY29F040
DC CHARACTERISTICS (continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC Max.
VCC = VCC Max., A9 = 12.5 V
VOUT = VSS to VCC, VCC = VCC Max.
/CE = VIL, /OE = VIH
±1.0
µA
ILIT
A9 Input Load Current
Output Leakage Current
Vcc Active Current(1)
Vcc Active Current(2,3)
Vcc Standby Current
Input Low Level
50
±1.0
40
µA
µA
mA
mA
µA
V
ILO
ICC1
ICC2
ICC3
VIL
VIH
/CE = VIL, /OE = VIH
60
VCC = VCC Max., /CE = VCC ± 0.5V
100
0.8
-0.5
0.7 x
VCC
Input High Level
VCC
+
V
0.3
VID
Voltage for Electronic ID
and Sector Protect
VCC = 5.0 V
11.5
12.5
0.45
V
V
V
VOL
Output Low Voltage
Output High Voltage
IOL = 12 mA, VCC = VCC Min.
VOH1
IOH = -2.5 mA, VCC = VCC Min.
0.85 x
VCC
VOH2
IOH = -100 µA, VCC = VCC Min.
VCC
3.2
-
V
V
0.4
VLKO
Low VCC Lock-out Voltage
4.2
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with /OE at VIH.
2. ICC active while Internal Algorithm (program or erase) is in progress.
3. Not 100% tested.
23
HY29F040
AC CHARACTERISTICS
Read Only Operations
Parameter Symbol
JEDEC Standard
Description
Test Setup
-90(1)
-120(1)
-150(1)
Unit
tAVAV
tAVQV
tRC
Read Cycle Time(3)
Min.
90
90
120
120
150
150
ns
ns
tACC
Address to Output Delay /CE = VIL Max.
/OE = VIL
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tCE
tOE
tHZ
tDF
tOH
Chip Enable to
Output Delay
/OE = VIL
Max
Max
Max.
90
35
20
20
0
120
50
30
30
0
150
55
35
35
0
ns
ns
ns
ns
ns
Output Enable to
Output Delay
Chip Enable to
Output High Z(2,3)
Output Enable to
Output High Z(2,3)
Output Hold Time from
Addresses, /CE or /OE,
Whichever Occurs First
Min.
Notes :
1. Test Conditions:
Output Load: 1TTL gate and 100 pF
Input rise and fall times; 20ns
Input pulse levels: 0.45V to 2.4V
Timing measurement reference levels:
Input: 0.8 and 2.0V
Output: 0.8 and 2.0V
2. Output driver disable time
3. Not 100% tested
24
HY29F040
5.0 V
2.7 KOhm
IN3064 or
Equivalent
DEVICE
UNDER
TEST
C
L
Diodes = IN3064
or Equivalent
6.2 KOhm
Notes:
CL = 100pF including jig capacitance.
Figure 9. Test Condition
25
HY29F040
AC CHARACTERISTICS
Programming/Erase Operations
Parameter Symbols
JEDEC Standard
-90
90
0
-120 -150 Unit
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
tOES
tWC
tAS
tAH
tDS
tDH
Write Cycle Time(1)
Address Setup Time
Address Hold Time
Data Setup Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Typ.
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
sec
sec
sec
µs
ns
µs
µs
µs
ms
ns
45
45
0
50
50
0
50
50
0
Data Hold Time
Output Enable Setup Time
Output Enable Read(1)
0
0
0
tOEH
0
0
0
Hold Time
Toggle &/Data Polling(1)
10
0
10
0
10
0
tGHWL
tELWL
tGHWL
tCS
Read Recover Time Before Write
/CE Setup Time
0
0
0
tWHEH
tWLWH
tWHWL
tWHWH1
tCH
/CE Hold Time
0
0
0
tWP
Write Pulse Width
45
20
16
50
20
16
350
50
20
16
350
tWPH
tWHWH1
Write Pulse Width High
Byte Programming Operation
Max. 350
Typ. 0.35
tWHWH2
tWHWH2
Sector Erase Operation
Chip Erase Operation
Vcc Setup Time(1)
0.35 0.35
Max.
Typ.
15
15
2.7
120
50
500
4
15
2.7
120
50
500
4
tWHWH3
tWHWH3
2.7
Max. 120
tVCS
Min.
Min.
Min.
Min.
Min.
Min.
Min.
50
500
4
(1,2)
tVIDR
tOESP
tVLHT
tWPP1
tWPP2
tCSP
Rise Time to VID
/OE Setup Time to /WE Active(1,2)
Voltage Transition Time(1,2)
4
4
4
Sector Protect Write Pulse Width(2)
Sector Unprotect Write Pulse Width(2)
/CE Setup Time to /WE Active(1, 2)
100
10
4
100
10
4
100
10
4
Notes:
1. Not 100% tested.
2. These timings are for Sector Protect and/or Sector Unprotect operations.
26
HY29F040
SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be Steady Will Be Steady
May Change
from H to L
Will Be Changing
from H to L
May Change
from L to H
Will Be Changing
from L to H
Don`t Care,
Any Change
Permitted
Changing, State
Unknown
Does Not
Apply
CenterLine is
High Impedance
(High Z) State
tRC
Addresses
CE
Address Stable
tACC
tHZ
tOE
OE
tDF
tOEH
WE
tCE
tOH
High Z
High Z
Outputs
Output Valid
Figure 10. AC Waveforms for Read Operations
27
HY29F040
SWITCHING WAVEFORMS
Data Polling
PA
5555H
tWC
PA
Addresses
CE
tAH
tAS
tGHWL
OE
tWP
tWHWH1
WE
tWPH
tCS
tDH
Data
DOUT
A0H
PD
DQ7
tDS
5.0V
VCC
GND
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. /DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 11. AC Waveforms Program Operations
28
HY29F040
SWITCHING WAVEFORMS
tAS
tAH
5555H
2AAAH
5555H
5555H
2AAAH
SA
Addresses
CE
tGHWL
OE
tWP
WE
tWPH
tCS
tDH
Data
AAH
55H
80H
AAH
55H
10H/30H
tDS
tVCS
5.0V
VCC
GND
Notes:
1. SA is the sector address for Sector Erase. Address = X = Dont Care for Chip Erase.
Figure 12. AC Waveforms Chip/Sector Erase Operations
29
HY29F040
SWITCHING WAVEFORMS
tCH
CE
OE
tDF
tOE
tOEH
WE
tCE
tOH
High
Z
DQ7
DQ7
DQ7=Valid Data
tWHWH 1 or 2
Data
DQ0-DQ7
Valid Data
DQ0-DQ6=Invalid
DQ0-DQ6
tOE
5.0V
CC
GND
V
Notes:
1. DQ7 = Valid Data (The device has completed the internal program or erase operation.)
Figure 13. AC Waveforms for /Data Polling during Internal Algorithm Operations
30
HY29F040
SWITCHING WAVEFORMS
CE
tOEH
WE
tOES
OE
Data
(DQ0-DQ7)
DQ6 =
Stop Toggling
DQ0-DQ7
Valid
Data
DQ6 = Toggle
DQ6 = Toggle
tOE
5.0V
VCC
GND
Notes:
1. DQ6 stops toggling (The device has completed the internal program or erase operation)
Figure 14. AC Waveforms for Toggle Bit during Internal Algorithm Operations
31
HY29F040
SWITCHING WAVEFORMS
A18
A17
A16
SAX
SAY
12V
A9
tVLHT
tVLHT
12V
OE
tVLHT
CE
t CSP
tWPP1
WE
A0
A1
A6
Data
O1H
tOE
5.0V
VCC
GND
Notes:
1. SAX = Sector Address for initial sector
2. SAY = Sector Address for next sector
Figure 15. AC Waveforms for Sector Protection
32
HY29F040
SWITCHING WAVEFORMS
A6
A12
A16
SA0
12V
A9
tVLHT
12V
CE
tCE
tVLHT
12V
OE
tOESP
tVLHT
WE
tWPP2
A18
A17
SA0
A0
A1
Data
00H
5.0V
VCC
Notes:
1. Starts with SA0 and sequences to SA7.
2. See Figure 15 for details.
Figure 16. AC Waveforms for Sector Unprotect
33
HY29F040
AC CHARACTERISTICS
Write / Erase / Program Operations
Alternate /CE Controlled Writes
Parameter Symbols
JEDEC Standard Description
-90
90
0
-120
120
0
-150 Unit
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
tWC
tAS
Write Cycle Time(1)
Address Setup Time
Address Hold Time
Data Setup Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Typ.
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
sec
sec
sec
µs
µs
µs
ms
µs
ns
tAH
45
45
0
50
50
0
50
50
0
tDS
tDH
Data Hold Time
tOES
tOEH
Output Enable Setup Time
Output Enable Read(1)
0
0
0
0
0
0
Hold Time
Toggle and /Data Polling(1)
10
0
10
0
10
0
tGHWL
tWLEL
tEHWH
tELEH
tGHWL
tWS
Read Recover Time Before Write
/WE Setup Time
0
0
0
tWH
/WE Hold Time
0
0
0
tCP
/CE Pulse Width
45
20
16
50
20
16
350
0.35
15
2.7
120
50
4
50
20
16
350
0.35
15
2.7
120
50
4
tEHEL
tCPH
tWHWH1
/CE Pulse Width High
Byte Programming Operation
tWHWH1
Max. 350
Typ. 0.35
tWHWH2
tWHWH2
Sector Erase Operation
Chip Erase Operation
Max.
Typ.
15
tWHWH3
tWHWH3
2.7
Max. 120
tVCS
Vcc Setup Time(1)
Min.
Min.
Min.
Min.
Min.
Min.
50
4
tVLHT
tWPP1
tWPP2
tOESP
tCSP
Voltage Transition Time(1,2)
Sector Protect Write Pulse Width(1,2)
Sector Unprotect Write Pulse Width(1,2)
/OE Setup Time to /WE Active(1,2)
/CE Setup Time to /WE Active(1,2)
100
10
4
100
10
4
100
10
4
4
4
4
Notes:
1. Not 100% tested.
2. These timings are for Sector Protect and/or Sector Unprotect operations.
34
HY29F040
SWITCHING WAVEFORMS
Data Polling
5555H
tWC
PA
PA
Addresses
WE
tAH
tAS
tGHEL
OE
CE
tCP
tWHWH1
tCPH
tWS
tDH
AOH
PD
DQ7
DOUT
Data
VCC
tDS
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 17. Alternate /CE Controlled Program Operation Timings
35
HY29F040
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Limits
Typ.
0.35
2.7
Unit
Min.
Max.
15
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time
sec
sec
120
350
25
16
µs
11
sec
Erase/Program Cycles
100,000
1,000,000
cycles
LATCH UP CHARACTERISTICS
Parameter
Min.
Max.
Input Voltage with respect to Vss on all I/O pins
Vcc Current
-1.0V
Vcc + 1.0V
+ 100 mA
-100 mA
Notes:
1. Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
PDIP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
C
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
4
8
8
6
pF
pF
pF
IN
COUT
12
12
C
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 Mhz
PLCC PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
C
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
4
8
8
6
pF
pF
pF
IN
COUT
12
12
C
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 Mhz
TSOP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
VIN = 0
Typ.
6
Max.
7.5
12
Unit
pF
C
Input Capacitance
Output Capacitance
Control Pin Capacitance
IN
COUT
VOUT = 0
VIN = 0
8.5
7.5
pF
C
9
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
36
HY29F040
DATA RETENTION
Parameter
Test Conditions
150OC
Minimum
10
Unit
Minimum Pattern Data Retention Time
Years
Years
125OC
20
37
HY29F040
PACKAGE DRAWINGS - Physical Dimensions
TSOP32
32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
17
7.90
8.10
0.50 BSC
16
32
18.30
18.50
0.05
0.15
19.80
20.20
.0.08
.0.20
1.20
MAX
.0.18
.0.21
0o
5o
0.25MM (0.0098") BSC
.015
.060
PDIP32
32-Pin Plastic DIP (measured in inches)
1.640
1.680
.600
.625
32
17
16
.530
.580
.008
.015
Pin 1 I.D.
.630
.700
0O
10O
.005 MIN
.045
.065
.140
.225
.040
.225
SEATING PLANE
.015
.060
.120
.090
.014
.022
.160
.110
38
HY29F040
PACKAGE DRAWINGS - Physical Dimensions
PLCC32
32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
Pin 1 I.D
.
.042
.056
.585 .547
.595 .553
.125
.140
.080
.095
SEATING
PLANE
.400
REF
.013
.021
.490
.530
.026
.032
.050 REF.
TOP VIEW
SIDE VIEW
39
HY29F040
ORDERING INFORMATION
Hyundai products are available in several packages and operating ranges.
The order number (Valid Combination) is formed by a combination of the following:
HY29F040
X
X
X
X
SPECIAL INSTRUCTIONS
TEMPERATURE RANGE
Blank = Commercial (0OC to +70OC)
I
=
Industrial (40OC to +85OC)
E = Extended (55OC to +125OC)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
PACKAGE TYPE
P = 32-Pin Plastic DIP (PDIP)
C = 32-Pin Rectangular Plasteic Leaded
Chip Carrier (PLCC)
T = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout
R = 32-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
DEVICE NUMBER/DESCRIPTION
HY29F040
4 Megabit (512K x 8-Bit) CMOS 5.0 volt-only.
Sector Erase Flash Memory.
VALID COMBINATIONS
P-90, C-90, T-90, R-90
P-90I, C-90I, T-90I, R-90I
P-90E, C-90E, T-90E, R-90E
VALID COMBINATIONS
90ns
Valid Combinations List configurations planned to
be supported in volume for this device. Consult the
local Hyundai sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
P-12, C-12, T-12, R-12
P-12I, C-12I, T-12I, R-12I
P-12E, C-12E, T-12E, R-12E
120ns
150ns
P-15, C-15, T-15, R-15
P-15I, C-15I, T-15I, R-15I
P-15E, C-15E, T-15E, R-15E
40
HY29F040
相关型号：
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