HY29F400AR-15 [HYNIX]
Flash, 512KX8, 150ns, PDSO48, REVERSE, TSOP-48;
| 型号： | HY29F400AR-15 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Flash, 512KX8, 150ns, PDSO48, REVERSE, TSOP-48 ISM频段 光电二极管 内存集成电路 |
| 文件： | 总43页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY29F400A Series
4 Megabit 5.0 volt-only Sector Erase Flash Memory
KEY FEATURES
•
•
•
•
•
Ready//Busy
•
•
•
5.0 V± 10% Read, Program, and Erase
Minimizes system-level power requirements
High performance
45 ns access time
Compatible with JEDEC-Standard Commands
-
RY//BY output pin for detection of programming
or erase cycle completion
-
/RESET
Hardware pin resets the internal state machine
to the read mode
Internal Erase Algorithms
-
-
-
Uses software commands, pinouts, and
packages following industry standards for
single power supply Flash memory
-
Automatically erases a sector, any combination
of sectors, or the entire chip
•
•
Minimum 100,000 Program/Erase Cycles
Sector Erase Architecture
Internal Programming Algorithms
-
Automatically programs and verifies data at a
specified address.
-
One 16 Kbytes, two 8 Kbytes, one 32 Kbytes,
and seven 64 Kbytes (byte mode)
Low Power Consumption
-
Any combination of sectors can be erased
concurrently; also supports full chip erase
-
-
-
20 mA typical active read current for Byte Mode
28 mA typical active read current for Word Mode
30 mA typical program/erase current
•
Erase Suspend/Resume
-
Suspend a sector erase operation to allow a
data read in a sector not being erased within
the same device
•
•
Sector Protection
-
Hardware method disables any combination
of sectors from a program or erase operation
Boot Code Sector Architecture
DESCRIPTION
operations.
The HY29F400A is an 4 Megabit, 5.0 volt-only CMOS
Flash memory device organized as a 512 Kbytes of 8-
bits each, or 256 Kbytes of 16 bits each. The device
is offered in standard 44-pin PSOP and 48-pin
TSOP packages. It is designed to be programmed
and erased in-system with a 5.0 volt power-supply
and can also be programmed in standard PROM
programmers.
The HY29F400A is programmed by executing the
program command sequence. This will start the
internal byte/word programming algorithm that
automatically times the program pulse widths
and also verifies proper cell margin. Erase is ac-
complished by executing either the sector erase
or chip erase command sequence. This will start
the internal erasing algorithm that automatically
times the erase pulse width and also verifies
proper cell margin. No preprogramming is re-
quired prior to execution of the internal erase al-
gorithm. Sectors of the HY29F400A Flash
memory array are electrically erased via Fowler-
Nordheim tunneling. Bytes/words are pro-
grammed one byte/word at a time using a hot
electron injection mechanism.
With access times of 45ns, 55ns, 70ns, 90 ns, 120
ns and 150 ns, the HY29F400A has separate chip
enable (/CE), write eable (/WE), and output enable (/
OE) controls. Hyundai Flash memory devices re-
liably store memory data even after 100,000 pro-
gram/erase cycles.
The HY29F400A is entirely pin and command set
compatible with the JEDEC standard for 4Mega-
bit Flash memory devices. Commands are writ-
ten to the command register using standard mi-
croprocessor write timings. Register contents
serve as input to an internal state-machine that
controls the erase and programming circuitry.
Write cycles also internally latch addresses and
data needed for the programming and erase
The HY29F400A features a sector erase architec-
ture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and
seven 64 Kbytes. Sectors can be erased indi-
vidually or in groups without affecting the data in
other sectors. Multiple sector erase and full chip
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits
described. No patent licences are implied.
Rev.03/Aug.97
Hyundai Semiconductor
erase capabilities add flexibility to altering the data in The HY29F400A also has a hardware /RESET pin.
the device. To protect this data from accidental Driving the /RESET pin low during execution of an
program and erase, the device also has a sector Internal Programming or Erase command will ter-
protect function. This function hardware write pro- minate the operation and reset the device to the Read
tects the selected sector(s). The sector protect mode. The /RESET pin may be tied to the system
and sector unprotect features can be enabled in reset circuitry, so that the system will have ac-
a PROM programmer.
cess to boot code upon completion of system
reset, even if the Flash device is in the process
of an Internal Programming or Erase operation. If
the device is reset using the /RESET pin during an
Internal Programming or Erase operation, data
in the address locations on which the internal state
machine is operating will be erroneous. Thus,
these address locations will need rewriting after
the device is reset.
For read, program and erase operation, the
HY29F400A needs a single 5.0 volt power-supply.
Internally generated and well regulated voltages
are provided for the program and erase
operation. A low Vcc detector inhibits write opera-
tions on loss of power. End of program or erase is
detected by the Ready/Busy status pin, /Data Polling
of DQ7, or by the Toggle Bit I feature on DQ6.
Once the program or erase cycle has been suc-
cessfully completed, the device internally resets to
the Read mode.
BLOCK DIAGRAM
RY/BY
Buffer
RY/BY
Vcc
DQ0-DQ15
Erase Voltage
Vss
Generator
Input/Output
Buffer
/WE
/BYTE
/RESET
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
/CE
/OE
Y-Gating
Y-Decoder
STB
Address
Latch
Vcc Detector
Timer
Cell Matrix
X-Decoder
A0-A17
A-1
HY29F400A
2
PIN DESCRIPTION
A0 - A17
Address Inputs
DQ0 - DQ14 Data Input/Output
DQ15 /A-1
Mux.
Data Input/Output (word mode),
Address input (byte mode)
Chip Enable
/CE
/OE
Output Enable
/WE
Write Enable
Vss
Device Ground
/RESET
RY/ /BY
Vcc
Hardware Reset Pin, Active Low
Ready/Busy Status Output
Device Power Supply
Selects 8-bit or 16-bit Mode
Not Connected Internally
/BYTE
NC
PIN CONNECTIONS
A16
BYTE
Vss
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
2
BYTE
Vss
3
3
DQ15/A1
DQ7
4
4
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
5
5
DQ14
DQ6
6
6
7
7
DQ13
DQ5
8
A8
A8
8
9
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
NC
9
DQ12
DQ4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
RESET
NC
Vcc
DQ11
DQ3
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
NC
DQ10
DQ2
RY/BY
NC
DQ9
A17
A7
DQ1
DQ8
A6
A6
DQ0
A5
A5
OE
A4
A4
Vss
A3
A3
Vss
CE
A2
A2
CE
A0
A1
A1
A0
Reverse TSOP
Standard TSOP
NC
RY/BY
A17
A7
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
2
WE
A8
3
4
A9
A6
5
A10
A11
A12
A13
A14
A15
A16
BYTE
Vss
A5
6
A4
7
A3
8
A2
9
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
CE
Vss
OE
DQ15/A-1
DQ7
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
PSOP
HY29F400A
3
BUS OPERATION
(1)
Table 1. Bus Operations (/BYTE = VIH)
OPERATION
/CE /OE
/WE
H
H
H
X
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
DQ0-DQ15
Code
/RESET
Electronic ID Manufacturer(2)
Electronic ID Device(2)
Read(3)
L
L
L
H
X
L
L
L
L
X
L
L
H
H
H
L
L
Code
L
A0
X
A1
X
A6
X
DOUT
H
Standby
X
High Z
High Z
High Z
H
Hardware RESET
Output Disable
X
X
X
X
X
X
L
H
H
VID
L
H
L
X
X
X
X
H
(4)
Write
A0
X
A1
X
A6
X
A9
VID
VID
A9
DIN
H
Enable Sector Protect
Verify Sector Protect(2)
Temporary Sector Unprotect
L
X
H
H
X
L
H
L
Code
DIN
H
X
A0
A1
A6
VID
Notes:
1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3. /WE can be VIL if /CE is VIL, /OE at VIH initiates the write operations.
4. Refer to Table 6 for valid DIN during a write operation.
(1)
Table 2. Bus Operations (/BYTE = VIL)
OPERATION
/CE /OE /WE A0
A1 A6
A9 DQ0-DQ7 DQ8-DQ15 /RESET
Electronic ID Manufacturer(2)
L
L
L
H
X
L
L
L
L
X
L
L
H
H
H
X
X
H
L
L
H
L
L
L
L
VID
VID
A9
X
Code
Code
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
X
H
H
H
H
L
Electronic ID Device(2)
Read(3)
L
A0
X
A1 A6
DOUT
Standby
X
X
X
X
X
X
X
High Z
High Z
High Z
Hardware RESET
Output Disable
X
X
X
H
H
VID
L
X
X
H
H
H
H
(4)
Write
A0
X
A1 A6
A9
VID
VID
A9
DIN
Enable Sector Protect
Verify Sector Protect(2)
Temporary Sector Unprotect
L
X
H
X
L
X
H
X
L
Code
X
A0
A1 A6
DIN
V
ID
Notes:
1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3. /WE can be VIL if /CE is VIL, /OE at VIH initiates the write operations.
4. Refer to Table 6 for valid DIN during a write operation.
HY29F400A
4
Table 3. Sector Protection Verify Electronic ID Codes
Type
A17-A12
A6
A1
A0
Code (HEX)
Manufacturer Code
X
V
VIL
VIL
ADH
IL
Byte
23H
29F400T
X
X
VIL
VIL
VIH
Word
2223H
29F400
A
Byte
ABH
22ABH
01H(1)
29F400B
VIL
VIL
VIL
VIH
VIH
VIL
Word
Sector
Address
Sector Protection
Note:
1. Outputs 01H at protected sector addresses, and outputs 00H at unprotected addresses.
Table 5. Sector Address Tables ( HY29F400AT)
A17
A16
A15
A14
A13
A12
Sector
Size
(x8) Address Range
(x16) Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
64
64
64
64
64
64
64
32
8
00000H-0FFFFH
10000H-1FFFFH
20000H-2FFFFH
30000H-3FFFFH
40000H-4FFFFH
50000H-5FFFFH
60000H-6FFFFH
70000H-77FFFH
78000H-79FFFH
7A000H-7BFFFH
7C000H-7FFFFH
00000H-07FFFH
08000H-0FFFFH
10000H-17FFFH
18000H-1FFFFH
20000H-27FFFH
28000H-2FFFFH
30000H-37FFFH
38000H-3BFFFH
3C000H-3CFFFH
3D000H-3DFFFH
3E000H-3FFFFH
1
1
0
1
8
SA10
1
1
X
16
Notes:
1.The address range is A17:A-1 if in byte mode (/BYTE = VIL).
2.The address range is A17:A0, if in word mode (/BYTE = VIH).
Table 5. Sector Address Tables ( HY29F400AB)
A17
A16
A15
A14
A13
A12
Sector
Size
(x8) Address Range
(x16) Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
X
0
16
8
00000H-03FFFH
04000H-05FFFH
06000H-07FFFH
08000H-0FFFFH
10000H-1FFFFH
20000H-2FFFFH
30000H-3FFFFH
40000H-4FFFFH
50000H-5FFFFH
60000H-6FFFFH
70000H-7FFFFH
00000H-01FFFH
02000H-02FFFH
03000H-03FFFH
04000H-07FFFH
08000H-0FFFFH
10000H-17FFFH
18000H-1FFFFH
20000H-27FFFH
28000H-2FFFFH
30000H-37FFFH
38000H-3FFFFH
0
1
0
1
1
8
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32
64
64
64
64
64
64
64
X
X
X
X
X
X
X
SA10
Notes:
1.The address range is A17:A-1 if in byte mode (/BYTE = VIL).
2.The address range is A17:A0, if in word mode (/BYTE = VIH).
HY29F400A
5
pins. Output enable access time is the delay from
the falling edge of /OE to valid data at the output
pins (assuming the addresses have been stable
for at least tACC-tOE time).
Electronic ID Mode
The Electronic ID mode allows the reading out of a
binary code from the device and will identify its
manufacturer and device type. This mode is in-
tended for use by programming equipment for
the purpose of automatically matching the de-
vice to be programmed with its corresponding
programming algorithm. This mode is functional
over the entire temperature range of the device.
Standby Mode and Hardware /RESET
Standby Mode
The HY29F400A has two methods for imple-
menting standby mode. The first method re-
quires use of both the /CE pin and the /RESET
pin. The second method only requires use of the
/RESET pin.
To activate this mode, the programming equip-
ment must force VID (11.5V to 12.5V) on address
pin A9. Two identifier bytes may then be sequenced
from the device outputs by toggling address A0 from
VIL to VIH. All addresses are don't cares except A0,
A1, and A6 (see Table 3).
When using both pins, a CMOS standby mode is
achieved when both /CE and /RESET are held at
Vcc±0.5V. In this condition, the current consumed
is typically less than 1 µA. A TTL standby mode is
achieved with both /CE and /RESET held at VIH.
In this condition, the typical current required is
reduced to 200 µA. The device can be read with
standard access time (tCE) from either of these
two standby modes.
Manufacturer and device codes may also be read
via the command register. The command se-
quence is illustrated in Table 6 (refer to Electronic
ID Command section).
Byte 0 (A0=VIL) represents the manufacturer's
code (Hyundai Electronics = ADH) and byte 1
(A0=VIH) the device identifier code (HY29F400AT
= 23H and HY29F400AB = ABH for 8-bit mode;
HY29F400AT = 2223H and HY29F400AB =
22ABH for 16-bit mode). These two byte words
are given in Table 3. To read the proper device
codes when executing the Electronic ID, all iden-
tifiers for manufacturer and device will exhibit odd
parity with the MSB (DQ7) defined as the parity
bit. A1 must be VIL (see Table 3).
When using the /RESET pin only, a CMOS
standby mode is achieved with /RESET held at
Vss±0.5V. In this condition, the current con-
sumed is typically less than 1 µA. A TTL standby
mode is achieved with /RESET held at VIL. In this
condition, the typical current required is reduced
to 200 µA. Once the /RESET pin is taken high, the
device requires 50 ns of wake-up time before out-
puts are valid for a read access.
Read Mode
If the device is deselected during programming
or erase, the device will draw active current until
the programming or erase operation is
completed. In the standby mode the outputs are
in a high impedance state, independent of the /
OE input.
The HY29F400A has three control functions
which must be satisfied in order to obtain data at
the outputs. /CE is the power control and should
be used for device selection. /OE is the output
control and should be used to gate data to the
output pins if a device is selected. As shown in
Table 1, /WE should be held at VIH, except in Write
mode and Enable Sector Protect mode.
Output Disable Mode
With the /OE input at a logic high level (VIH), out-
put from the device is disabled. This will cause
the output pins to be in a high impedance state.
It is shown in Table 1 that /CE = VIL and /WE = VIH
Address access time (tACC) is equal to the delay
from stable addresses to valid output data. Chip en-
able access time (tCE) is the delay from stable ad-
dresses and stable /CE to valid data at the output
HY29F400A
6
for Output Disable. This is to differentiate Output To verify programming of the protection circuitry,
Disable mode from Write mode and to prevent the programming equipment must force VID on
inadvertent writes during Output Disable.
the address pin A9 with /CE and /OE at VIL and /
WE at VIH. As shown in Table 2, scanning the sec-
tor addresses while (A6, A1 and A0) = (0, 1, 0) will
produce a 01H code at the device output pins for
a protected sector. In the Verify Sector Protect
mode, the device will read 00H for an unprotected
sector. In this mode, the lower order addresses,
except for A0, A1 and A6, are don't care. Address
locations with A1 = VIL are reserved for Electronic
ID manufacturer and device codes. It is also pos-
sible to determine if a sector is protected in-sys-
tem by writing the Electronic ID command (de-
scribed in the Electronic ID command section be-
low.)
Program and Erase Modes
Device programming and erase are accom-
plished via the command register. Contents of
the register serve as inputs to the internal state
machine. Outputs of the state machine dictate
the function of the device.
The command register itself does not occupy
any addressable memory locations. The regis-
ter is a latch used to store the commands along
with the addresses and data information needed
to execute the command. The command regis-
ter is written by bringing /WE to VIL, while /CE is at
VIL and /OE is at VIH. Addresses are latched on the
Temporary Sector Unprotect Mode
falling edge of /WE or /CE, whichever happens The HY29F400A has a Temporary Sector Unprotect
later, while data is latched on the rising edge of / feature that allows the protect feature to be tem-
WE or /CE, whichever happens first. Standard mi- porarily suspended to change data in a protected
croprocessor write timings are used. Refer to AC sector in-system. The Temporary Sector Unprotect
Characteristics for Programming/Erase and their mode is activated by setting the /RESET pin to VID
respective Timing Waveforms for specific timing (11.5V - 12.5V).
parameters.
In this mode, protected sectors can be pro-
Enable Sector Protect and Verify Sector
Protect Modes
grammed or erased by selecting the sector
addresses. Once VID is removed from the /RE-
SET pin, all previously protected sectors will be
The HY29F400A has a hardware Sector Protect protected. Refer to the Temporary Sector
mode that disables both Programming and Erase Unprotect algorithm and timing waveforms.
operation to the protected sector(s). There are
total 11 sectors in this device. The sector protect
feature is enabled using programming equipment
at the user's site. The device is shipped from the
Hyundai factory with all sectors unprotected.
To activate the Sector Protect mode, the user must
force VID on address pin A9 and control pin /OE.
The sector addresses (see Table 4 and Table 5)
should be set to the sector to be protected. Pro-
gramming of the protection circuitry starts on the
falling edge of /WE pulse and is terminated with
the rising edge of /WE. Sector addresses must
be held fixed during the /WE pulse.
HY29F400A
7
COMMAND DEFINITIONS
quence will reset the device to Read mode. Table
defines the valid register command
sequences. Either of the two Read/Reset com-
mands will reset the device (when applicable).
Device operations are selected by writing spe-
cific address and data sequences in to the Com-
mand register. Writing incorrect addresses and
data values or writing them in the improper se-
6
Table 6. Command Definitions
Command
Sequence
Bus
write
Cycles
1
First bus
Second bus
Write Cycle
Third bus
Fourth bus Write
Cycle
Fifth bus
Sixth bus
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Addr
RA
Data Addr
Data Addr
Data Addr
Data
Addr
Data Addr
Data
Reset/Read
Read/
RD
Word
Byte
4
555H
AAAH
555H
AAH
2AAH
555H
2AAH
555H
55H
555H
AAAH
555H
F0H
RA
RD
Reset
Device ID
(Top
Word
Byte
3
3
AAH
55H
55H
90H
X01H
X02H
2223H
23H
AAAH AAH
AAAH 90H
Boot)
Device ID
(Bottom
Boot)
Word
Byte
555H
AAH
2AAH
555H
55H
55H
555H
90H
X01H
X02H
22ABH
ABH
AAAH AAH
AAAH 90H
Program
Word
Byte
4
6
6
1
1
555H
AAAH
555H
AAAH
555H
AAAH
AAH
AAH
AAH
2AAH
555H
2AAH
555H
2AAH
555H
55H
55H
55H
555H
AAAH
555H
AAAH
555H
AAAH
A0H
80H
80H
PA
PD
Chip
Word
Byte
555H
AAAH
555H
AAAH
AAH
AAH
2AAH
555H
2AAH
555H
55H
55H
555H
AAAH
SA
10H
30H
Erase
Sector
Erase
Word
Byte
Erase
Word
Byte
XXXH B0H
Suspend
Erase
Word
Byte
XXXH 30H
Resume
Notes:
1. Bus operations are defined in Tables 1 and 2.
2. For a Command Sequence, address bit A[18:15] = X = Don't Care for all address commands except for Program
Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the /WE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of /WE.
SA = Address of sector to be erased. (See Table 4 for top boot and Table 5 for bottom boot.)
4. The Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase
operation is in progress.
5. Reading from, and programming to, non-erasing sectors is allowed in the Erase Suspend mode.
6. The System should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 - A10.
Byte Mode: AAAH or 555H to addresses A-1 - A10.
7. Address 00H returns the manufacturer's ID code (Hyundai - ADH), address 01H returns the device ID code.
HY29F400A
8
The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus
cycle operation (see Table 6). There are two 'un-
lock' write cycles. These are followed by the pro-
gram set-up command and data write cycles.
Addresses are latched on the falling edge of /CE
or /WE, whichever happens later, and program
data (PD) are latched on the rising edge of /CE
or /WE, whichever happens first. The rising edge
of /CE or /WE, whichever happens first, begins
programming using the Embedded Program Al-
gorithm.
Read/Reset Command
The read or reset operation is initiated by writing
the Read/Reset command sequence into the
command register. Microprocessor read cycles
retrieve the data from the memory. The device
remains enable for reads until the command reg-
ister contents are changed.
The device will automatically power-up in the
Read/Reset mode. In this case, a command se-
quence is not needed to read the memory data.
This default power-up to Read mode ensures
that no spurious changes of the data can take
place during the power transitions. Refer to the
AC Characteristics for Read-Only Operation and
the respective Timing Waveforms for the specific
timing parameters.
Upon executing the algorithm, the system is not
required to provide further controls or timings.
The device will automatically provide adequate
internally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is com-
pleted when the data on DQ7 (also used as /
Data Polling) is equivalent to the data written to
this bit at which time the device returns to the
read mode and addresses are no longer latched
(see Table 7, Write Operation Status Flags).
Therefore, the device requires that a valid ad-
dress to the device be supplied by the system at
this particular instance of time for /Data Polling
operations. /Data Polling must be performed at
the memory location which is being programmed.
Electronic ID Command
The HY29F400A contains an Electronic ID com-
mand to supplement the traditional PROM pro-
gramming method described in the Electronic
ID Mode section. The operation is initiated by
writing the Electronic ID command sequence into
the command register. Following command
write, a read cycle from address XX00H retrieves
manufacturer code of ADH. A read cycle from
address XX01H returns the device code
(HY29F400AT = 23H and HY29F400AB = ABH
for 8-bit mode; HY29F400AT = 2223H and
HY29F400AB = 22ABH for 16-bit mode) (see
Table 3). All manufacturer and device codes ex-
hibit odd parity with the MSB (DQ7) defined as
the parity bit.
Any commands written to the chip during the In-
ternal Program Algorithm will be ignored. If a hard-
ware reset occurs during the programming opera-
tion, the data at that particular location will be
corrupted.
Byte/Word programming is allowed in any
sequence, and across sector boundaries. How-
ever, remember that a data "0" cannot be pro-
grammed to a data "1". Only erase operations
can convert a logical "0" to a logical "1". Attempt-
ing to program data from "0" to "1" may cause
the device to exceed time limits, or even worse,
result in an apparent success according to the /
Data Polling algorithm. In the later case, however,
a subsequent read of this bit will show that the
data is still a logical "0".
The Electronic ID command can also be used to
identify protected sectors. After writing the Elec-
tronic ID command sequence, the CPU can scan
the sector addresses (see Table 4 and Table 5)
while (A6, A1, A0) = (0, 1, 0). Protected sectors
will return 01H on the data outputs and unpro-
tected sectors will return 00H. To terminate the
operation, it is necessary to write the Read/Re-
set command sequence into the command
register.
Figure 1 illustrates the Byte/Word Programming
Byte/Word Programming Command
HY29F400A
9
Algorithm using typical command strings and bus Table 6). The sector address (any address loca-
operations.
tion within the desired sector) is latched on the
falling edge of /WE, while the command data is
latched on the rising edge of /WE. An internal
device timer will initiate the Sector Erase opera-
tion 50 µs from the rising edge of the /WE pulse
for the last Sector Erase command entered on
the device.
The device will ignore any commands written to
the chip during execution of the internal Byte/
Word Programming Algorithm. If a hardware/
RESET occurs during the Byte/Word Program-
ming operation, the data at that particular ad-
dress location will be corrupted.
Upon executing the Sector Erase command se-
quence, the device internal state machine executes
an internal erase algorithm. The system is not
required to provide further controls or timings.
The deviceautomatically provides adequate in-
ternally generated erase pulses and verify sec-
tor erase within the proper cell margins. Pro-
tected sectors of the device will not be erased,
even if they are selected with the Sector Erase
command.
Chip Erase Command
Chip erase is a six bus cycle operation (see Table
6). The chip erase begins on the rising edge of
the last /WE pulse in the command sequence.
Upon executing the Chip Erase command
sequence, the devices internal state machine ex-
ecutes an internal erase algorithm. The system
is not required to provide further controls or tim-
ings. The device will automatically provide ad-
equate internally generated erase pulses and
verify chip erase within the proper cell margins.
During chip erase, all sectors of the device are
erased except protected sectors.
Multiple sectors can be erased simultaneously by
writing the sixth bus cycle command of the Sec-
tor Erase command for each sector to be erased.
The time between initiation of the next Sector
Erase command must be less than 50 µs to guar-
antee acceptance of the command by the internal
state machine. The time-out window can be moni-
tored via the write operation status pin DQ3 (refer
to the Write Operation Status section for Sector
Erase Timer operation). It is recommended that
CPU interrupts be disabled during this time to
ensure that the subsequent Sector Erase com-
mands can be initiated within the 50 µs window.
The interrupts can be re-enabled after the last
Sector
Erese commnad is written. As mentioned above,
an internal device timer will initiate the Sector
Erase operation 50 µs from the rising edge of
the last /WE pulse. Sector Erase Timer Write Op-
eration Status pin (DQ3) can be used to monitor
time out window. If another falling edge of the /WE
occurs within the 50 µs time-out window, the in-
ternal device timer is reset. Loading the sector
erase buffer may be done in any sequence and
with any number of sectors.
During Chip Erase, data bit DQ7 shows a logical
"0". This operation is known as /Data Polling.
The erase operation is completed when the data
on DQ7 is a logical "1" (see Write Operation Sta-
tus section). Upon completion of the Chip Erase
operation, the device returns to read mode. At
this time, the address pins are no longer latched.
Note that /Data Polling must be performed at a
sector address within any of the sectors being
erased and not a protected sector to ensure that
DQ7 returns a logical "1" upon completion of the
Chip Erase operation.
Figure 2 illustrates the Chip Erase Algorithm using
typical command strings and bus operations.
The device will ignore any commands written to
the chip during execution of the internal Chip
Erase algorithm. If a hardware /RESET occurs
during the Chip Erase operation, the data in the
device will be corrupted.
Any command other than Sector Erase or Erase
Suspend during this period and afterwards will
reset the device to read mode, ignoring the previ-
Sector Erase Command
Sector erase is a six bus cycle operation (see
HY29F400A
10
ous command string. Resetting the device with
a hardware /RESET after it has begun execution
of a Sector Erase operation will result in the data
in the operated sectors being undefined and may
be unrecoverable. In this case, restart the Sector
Erase operation on those sectors and attempt to
allow them to complete the Erase operation.
Writing the Erase Suspend command during the
time-out will result in immediate termination of
the time-out period. Any subsequent writes of
the Sector Erase command will be taken as the
Erase Resume command (30H). Note that any
other commands during the time-out will reset
the device to the Read mode. The address pins
When erasing a sector or multiple sectors the are "don't cares" when writing the Erase Sus-
data in the unselected sectors remains pend or Erase Resume commands.
unaffected. The system is not required to pro-
When the Erase Suspend command is written
vide any controls or timings during these
during a Sector Erase operation, the chip will
operations.
take a maximum of 20 µs to suspend the erase
During Sector Erase operation, data bit DQ7 operation and go into Erase Suspended mode.
shows a logical "0". This operation is known as During this time, the system can monitor the /
/Data Polling. Sector Erase operation is com- Data Polling or Toggle Bit write operation status
plete when data on DQ7 is a logical "1" (see flags to determine when the device has entered
Write Operation Status section) at which time erase suspend mode (see Write Operation Sta-
the device returns to read mode. At this time, the tus section.) The system must use an address
address pins are no longer latched. Note that / of an erasing sector to monitor /Data Polling or
Data Polling must be performed at a sector ad- Toggle Bit to determine if the Sector Erase op-
dress within any of the sectors being erased and eration has been suspended.
not a protected sector to ensure that DQ7 re-
In Erase Suspend mode, the system can read
turns a logical "1" upon completion of the Sector
data from any sector that is not being erased. A
Erase operation.
read from a sector being erased will result in write
operation status data. After the system writes
the Erase Suspend command and waits until
the Toggle Bit stops toggling, data reads from
the device may then be performed (see Write
Operation Status section). Any further writes of
the Erase Suspend command at this time will
be ignored.
Figure 2 illustrates the Sector Erase Algorithm
using typical command strings and bus
operations.
During execution of the Sector Erase command,
only the Erase Suspend and Erase Resume
commands are allowed. All other commands will
reset the device to read mode.
To resume operation of Sector Erase, the Erase
Resume command (30H) should be written. Any
further writes of the Erase Resume command at
this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed
Sector Erase operation.
Note: Do not attempt to write an invalid command
sequence during the sector erase operation.
Doing so will terminate the sector erase opera-
tion and the device will reset to the read mode.
Erase Suspend/Erase Resume Commands
In Erase Suspend mode, the system can also
use the Byte/Word Programming Command.
However, data must be programmed to sectors
that are not erase suspended.
The Erase Suspend command allows the user
to interrupt a Sector Erase operation and read
data from or to a sector that is not being erased.
The Erase Suspend command is applicable only
during Sector Erase operation, including, but not
limited to, sector erase time-out period after any
Sector Erase commands (30H) have been initiated.
HY29F400A
11
WRITE OPERATION STATUS
Table7. Write Operation Status Flags(1)
Mode
Operation
DQ[7] 1
DQ[7]#
Data
0
DQ[6]
Toggle
Data 4
Toggle
Data 4
DQ[5]
0/1 2
DQ[3] DQ[2] 1 RY/BY#
Programming in progress
Programming completed
Erase in progress
N/A
Data
1 3
N/A
Data
0
1
0
1
Data
0/1 2
Normal
To g g le
Data 4
Erase completed
1
Data
Data
Read within erase suspended
sector
1
No toggle
Data
0
N/A
Toggle
Data
1
1
Read within non-erase suspended
sector
Erase
Data
Data
Data
Suspend
Programming in progress 5
Programming completed 5
DQ[7]#
Data
Toggle
Data 4
0/1 2
N/A
N/A
0
1
Data
Data
Data
Notes:
1. A valid address is required when reading status information. See text for additional information.
2. DQ[5] status switches to a 1 when a program or erase operation exceeds the maximum timing limit.
3. A 1 during sector erase indicates that the 50 µs time-out has expired and active erasure is in progress.
DQ[3] is not applicable to the chip erase operation.
4. Equivalent to No Toggle because data is obtained in this state.
5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).
tor Erase, /Data Polling must be performed at
sector address within any of the sectors being
DQ7
/Data Polling
erased and not
a
protected sector.
The HY29F400 device features /Data Polling as
a method to indicate to the host the status of the
Byte/Word Programming, Chip Erase, and Sec-
tor Erase operations. When the Byte/Word Pro-
gramming operation is in progress, an attempt
to read the device will produce the compliment
of the data last written to DQ7. Upon completion
of the Byte/Word Programming operation, an at-
tempt to read the device will produce the true
data last written to DQ7. When the Chip Erase or
Sector
Otherwise, the /Data Polling status may not be
valid. Once the Internal Algorithm operation is
close to being completed, the HY29F400 data
pins (DQ7) may change asynchronously while
the output enable (/OE) is asserted low. This
means that the device is driving status informa-
tion on DQ7 at one instant and valid data at the
next instant of time. Depending on when the sys-
tem samples the DQ7 output, it may read status
or valid data. Even if the device has completed
the Internal Algorithm operation and DQ7 has a
valid data, data outputs on DQ0-DQ6 may be
still invalid. Valid data on DQ0-DQ7 will be read
on the successive read attempts.
iErase operation is in progress, an attempt to
read the device will produce a logical "0" at the
DQ7 output. Upon completion of the Chip Erase
or Sector Erase operation, an attempt to read
the device will produce a logical "1" at the DQ7
output. The flowchart for Data Polling (DQ7) is
shown in Figure 3.
The /Data Polling feature is only active during
the Byte/Word Programming operation, Chip
Erase operation, Sector Erase Operation, or Sec-
tor Erase time-out window (see Table 7).
For Chip Erase, the /Data Polling is valid after the
rising edge of the sixth /WE pulse in the six write
pulse sequence. For Sector Erase, the /Data Poll-
ing is valid after the last rising edge of the sector
erase /WE pulse. For both Chip Erase and Sec-
DQ6
Toggle Bit I
The HY29F400 also features the "Toggle bit 1"
HY29F400A
12
as a method to indicate to the host system the
status of the Internal Programming and Erase Al-
gorithms (see Figure 4 for Toggle Bit (DQ6) flow-
chart.
erasure. Thus, both status bits are required for
sector and mode information.
DQ5
During an Internal Programming or Erase Algo-
rithm cycle, successive attempts to read (/OE
toggling) data from the device will result in DQ6
toggling between one and zero. Once Internal
Programming or Erase operation is completed,
DQ6 will stop toggling and valid data will be read
on the next successive attempts. During Byte Pro-
gramming, Toggle Bit I is valid after the rising
edge of the fourth /WE pulse in the four write
pulse sequence. For Chip Erase, Toggle Bit I is
valid after the rising edge of the sixth /WE pulse in
the six write pulse sequence. For Sector Erase,
Toggle Bit I is valid after the last rising edge of the
sector erase /WE pulse. Toggle Bit I is also active
during sector erase time-out window.
Exceeded Timing Limits
DQ5 will indicate if the Byte/Word Programming,
Chip Erase, or Sector Erase time has exceeded
the specified limits (internal pulse count) of the
device. Under these conditions DQ5 will produce
a logical "1". This is a failure condition which
indicates that the program or erase cycle was not
successfully completed. /Data Polling is the only
operating function of the device under this
condition. The /OE and /WE pins will control the
output disable functions as described in Table
1.
If this failure condition occurs during Sector Erase
operation, it specifies that particular sector is bad
and it may not be reused. However, other sec-
tors are still functional and may continue to be
used for the program or erase operation. The
device must be reset to the Read mode to use
other sectors of the device. Write the Read/Reset
command sequence to the device, and then ex-
ecute the Byte/Word Programming or Sector
Erase command sequence. This allows the sys-
tem to continue to use the other active sectors in
the device.
In Byte/Word Programming, if the sector being
written to is protected, the Toggle Bit I will toggle
for about 2 µs and then stop toggling without the
data having changed. In Chip Erase or Sector
Erase, the device will erase all the selected sec-
tors except for the ones that are protected. If all
selected sectors are protected, the chip will
toggle the Toggle Bit I for about 100 µs and then
drop back into read mode, having changed none
of the data. Either /CE or /OE toggling will cause
the DQ6 Toggle Bit I to toggle.
DQ2
Toggle Bit II
If this failure condition occurs during Chip Erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad. In so, the chip
should not be reused.
Toggle Bit II, DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing or
whether that sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final /WE
pulse in the command sequence. The device
toggles DQ2 with each /OE or /CE read cycle.DQ2
toggles when the host reads at addresses within
sectors that have been selected for erasure, but
cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by
comparison, indicates whether the device is ac-
tively erasing or is in Erase Suspend, but cannot
distinguish which sectors are selected for
If this failure condition occurs during Byte/Word Pro-
gramming operation, it indicates the entire sector
containing that byte is bad and this sector may not
be reused (other sectors are still functional and
can be reused.)
The DQ5 failure condition may also appear if a
user tries to program a non blank location with-
out erasing. In this case, the device may exceed
time limits and not complete the Internal Algo-
rithm operation. Hence, the system never reads
a valid data on DQ7 bit and DQ6 never stops
HY29F400A
13
toggling. Once the device has exceeded timing
limits, the DQ5 bit will indicate a "1".
During a programming operation, the RY/ /BY
pin is driven low after the rising edge of the fourth
/WE pulse. During an erase operation, the RY/ /
BY pin is driven low after the rising edge of the
sixth /WE pulse. The RY/ /BY pin will indicate a
busy condition during the /RESET pulse. Refer
to the timing waveforms for the RY/ /BY status
pin for further clarification. The RY/ /BY pin is high
in the Standby mode.
DQ3
Sector Erase Timer
After the completion of the initial Sector Erase
command sequence, the sector erase time-out
window will begin. DQ3 will remain low until the
time-out window is closed. /Data Polling and
Toggle Bit are valid after the initial Sector Erase
command sequence.
Since this is an open-drain output, several RY/ /
BY pins can be tied together with a pull-up resis-
tor to Vcc.
/RESET
If /Data Polling or the Toggle Bit indicates the
device has been written with a valid erase com- Hardware Reset
mand, DQ3 maybe used to determine if the Sector
The HY29F400A device may be reset by driving
Erase time-out windo is still open. If DQ3 is a
logical "1" the internally controlled erase cycle
has begun. Attempts to write subsequent com-
mand to the device will be ignored until the erase
operation is completed as indicated by /Data
Polling or Toggle Bit. If DQ3 is a logical "0", the
device will accept additional Sector Erase
commands. To ensure the command has been
accepted, the system software should check the
status of DQ3 prior to and following each subse-
quent Sector Erase command. If DQ3 were high
on the second status check, the command may
not have been accepted. Refer to Table 7: Write
Operation Status Flags.
the /RESET pin to VIL. The /RESET pin must be
kept low (VIL) for at least 500ns. Pulling the /RE-
SET pin low will terminate any operation in
progress. The internal state machine will be re-
set to the read mode 20µs after the /RESET pin
is driven low. If a hardware reset occurs during a
Programming or Erase operation, the data at that
particular location will be indeterminate.
When the /RESET pin is low and the internal re-
set is complete, the device goes to Standby mode
and cannot be accessed. Also, note that all the
data output pins are tri-stated for the duration of
the /RESET pulse. Once the /RESET pin is taken
high, the device requires 50ns of wake up time
until outputs are valid for a read access.
RY/ /BY
Ready//Busy Status
The /RESET pin may be tied to the system reset
input. Therefore, if a system reset occurs during
an Internal Programming or Erase operation, the
device will be automatically reset to read mode.
This will enable the system's microprocessor to
read the boot-up firmware from the Flag's
memory.
The HY29F400A provides a RY/ /BY open-drain
output pin as a way to indicate to the host sys-
tem that an Internal Programming or Erase op-
eration is either in progress or has been
completed. If the RY/ /BY output is low, the de-
vice is busy with either a Programming or Erase
operation. If the RY/ /BY output is high, the device is
ready to accept a Read, Programming, or Erase
command. When the RY/ /BY pin is low, the de-
vice will not accept any additional Programming
or Erase commands with the exception of the
Erase Suspend command. If the HY29F400 is
placed in an Erase Suspend mode, the RY/ /BY
output will be high.
DATA PROTECTION
The HY29F400A is designed to offer protection
against accidental erasure or programming
caused by spurious system level signals that may
exist during power transitions. During power-up
the device automatically resets the internal state
HY29F400A
14
machine in the Read mode. Also, with its control
register architecture, alteration of the memory
contents only occurs after successful comple-
tion of specific multi-bus cycle command
sequences. The device also incorporates sev-
eral features to prevent inadvertent write cycles
resulting from Vcc power-up and power-down
transitions or system noise.
device. Sector protection is accomplished in a
EPROM programmer.
The HY29F400A features hardware sector pro-
tection which will disable both program and
erase operations to a sector or multiple sectors.
To activate this mode, the programming equip-
ment must force VID on control pin /OE and ad-
dress pin A9. Sector addresses should be set
using higher address lines A17:A12. The pro-
tection mechanism begins on the falling edge
of /WE pulse and is terminated with the rising
edge of /WE. See Figures 19 and 20 for details
of implementing Sector Protect.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during Vcc
power-up and power-down, a write cycle is locked
out for Vcc less than 3.2V (typically 3.7V). If Vcc <
V
LKO, the command register is disabled and all
internal programming/erase circuits are
disabled. Under this condition the device will
reset to the Read mode. Subsequent writes will
Sector Unprotect
The HY29F400A also features a sector
unprotect mode, so that protected sectors may
be unprotected to incorporate any changes in the
code. Protecting all sectors is necessary before
unprotecting any sector(s). Sector unprotection
is accomplished in a PROM programmer. See
Figures 21 and 22 for details of implementing
Sector Unprotect.
be ignored until the Vcc level is greater than VLKO
.
It is the users responsibility to ensure that the
control pins are logically correct to prevent unin-
tentional writes when Vcc is above 3.2V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on /OE, /
CE or /WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of /OE =
V
IL, /CE = VIH, or /WE = VIH. To initiate a write
cycle /CE and /WE must be a logical "0" while /
OE is a logical "1".
Power-Up Write Inhibit
Power-up of the device with /WE = /CE = VIL and
/OE = VIH will not accept commands on the rising
edge of /WE. The internal state machine is auto-
matically reset to the Read mode on power-up.
Sector Protection
Sectors of the HY29F400A may be hardware pro-
tected at the users factory. The protection circuitry
will disable both program and erase functions
for the protected sectors. Requests to program
or erase a protected sector will be ignored by the
HY29F400A
15
START
Write Program Command Sequence
(see below)
/Data Polling Device
NO
Increment Address
Last Address
?
YES
Programming Completed
Program Command Sequence (Address/Command)
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Figure 1. Internal Programming Algorithm
HY29F400A
16
Start
Write Erase Command Sequence
(see below)
/Data Polling or Toggle Bit
Successfully Completed
Erase Completed
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command)
Chip Erase Command Sequence
(Address/Command)
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
Figure 2. Internal Erase Algorithm
HY29F400A
17
START
Read Byte
(DQ0-DQ7), Addr = VA
VA
=
=
Valid address for programming
Any of the sector addresses
within the sector being erased
during sector erase operation.
=
XXXXH during Chip Erase
YES
DQ7 = Data
?
NO
NO
DQ5 = 1
?
YES
Read Byte
(DQ0-DQ7), Addr = VA
YES
DQ7 = Data
?
NO
Fail
Pass
Notes:
1. DQ7 is rechecked even if DQ5 = logical "1" because DQ7 may change simultaneously with
DQ5.
Figure 3. /Data Polling Algorithm
HY29F400A
18
START
Read Byte(DQ0-DQ7)
Addr = Don`t Care
NO
DQ6=Toggle
?
YES
NO
DQ5=1
?
YES
Read Byte(DQ0-DQ7)
Addr = Don`t Care
NO
DQ6=Toggle
?
YES
Fail
Pass
Notes:
1. DQ6 is rechecked even if DQ5 = logical "1" because DQ6 may stop toggling at the same time as
DQ5 changing to a logical "1".
Figure 4. Toggle Bit Algorithm
HY29F400A
19
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages....................... -65°Cto +150°C
Commercial(C) Devices ............... 0°C to +70°C
Industrial(I) Devices .................. -40°C to +85°C
Extended(E) Devices .............. -55°C to +125°C
Ambient Temperature
With Power Applied................ -55°C to +125°C
Vcc supply Voltages
Voltage with Respect to Ground
Vcc for -45, -55 device ...............+4.75V to +5.25V
Vcc for -70, -90, -120, -150 device
................+4.5V to +5.5V
All pins except A9(Note 1)....... -0.5V to + 7.0V
Vcc (Note 1) ............................. -2.0V to + 7.0V
A9 (Note 2) .............................-2.0V to +12.5V
Output Short Circuit Current (Note 3) .... 200 mA
Notes:
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may overshoot
Vss to -2.0V for periods of up to 20 ns. Maximum
DC voltage on output and I/O pins is Vcc +0.5V.
During Voltage transitions, outputs may overshoot
to Vcc + 2.0V for periods up to 20 ns.
1. Operating ranges define those limits between
which the functionality of the device is guaranteed.
2. Minimum DC input voltage on A9 pin is -0.5V.
During voltage transitions, A9 may overshoot Vss
to -2.0V for periods of up to 20 ns. Maximum DC
input voltage on A9 is + 12.5V which may overshoot
to +13.5V for periods of up to 20 ns.
3. No more than one output shorted at a time. Duration
of the short circuit should not be greater than one
second.
Stresses above those listed under "absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only; functional opera-
tion of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure of the de-
vice to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
HY29F400A
20
20 ns
20 ns
+0.8 V
-0.5 V
- 2.0 V
20 ns
Figure 5. Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns
20 ns
Figure 6. Maximum Positive Overshoot Waveform
HY29F400A
21
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter Parameter Description
Symbol
Test Conditions
Min.
Max.
Unit
ILI
ILIT
ILO
Input Load Current
VIN = VSS to VCC, VCC = VCC Max.
VCC = VCC Max., A9 = 12.5 V
VOUT = VSS to VCC, VCC = VCC Max.
1.0
50
υA
υA
υA
A9 Input Load Current
Output Leakage Current
1.0
ICC1
VCC Active Read Current(1) /CE = VIL, /OE = VIH
Vcc = Vcc Max
Byte
Word
40
50
mA
mA
mA
ICC2
ICC3
ICC4
VCC Active Write Current(2,3) /CE = VIL, /OE = VIH, Vcc = Vcc Max
60
VCC Standby Current
VCC = VCC Max., /CE = /RESET = VIH
1.0
VCC Standby Current
(/RESET)
VCC = VCC Max., /RESET = VIL
1.0
mA
V
VIL
VIH
VID
Input Low Level
Input High Level
-0.5
2.0
0.8
VCC + 0.5
12.5
V
Voltage for Electronic
ID and Sector Protect
VCC = 5.0 V
11.5
V
VOL
VOH
VLKO
Output Low Voltage
IOL = 5.8 mA, VCC = VCC Min.
IOH = -2.5 mA, VCC = VCC Min.
0.45
4.2
V
V
V
Output High Voltage
2.4
3.2
Low VCC Lock-Out Voltage
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component
(at 5 MHz). The frequency component typically is less than 2 mA/MHz, with /OE at VIH.
2. ICC active while Internal Algorithm (program or erase) is in progress.
3. Not 100% tested.
HY29F400A
22
DC CHARACTERISTICS (continued)
CMOS Compatible
Parameter Parameter Description
Symbol
Test Conditions
Min.
Max.
Unit
ILI
ILIT
ILO
ICC1
Input Load Current
VIN = VSS to VCC, VCC = VCC Max.
VCC = VCC Max., A9 = 12.5 V
VOUT = VSS to VCC, VCC = VCC Max.
±1.0
50
υA
υA
υA
A9 Input Load Current
Output Leakage Current
±1.0
Byte
VCC Active Read
Current(1)
/CE = VIL, /OE = VIH
VCC = VCC Max.
40
50
mA
mA
Word
ICC2
ICC3
ICC4
VCC Active Write
Current(2,3)
/CE = VIL, /OE = VIH, VCC = VCC Max.
50
VCC Standby Current
VCC = VCC Max., /CE = VCC ± 0.5V,
5
υA
υA
/RESET = VCC , ±0.5V, /OE=VIH
Vcc Standby Current
(/RESET)
VCC = VCC Max.,
5
/RESET = VSS ±0.5V
VIL
VIH
Input Low Level
Input High Level
-0.5
0.8
V
V
0.7x VCC VCC + 0.3
VID
Voltage for Electronic ID
and Sector Protect
VCC = 5.0 V
11.5
12.5
0.45
V
V
VOL
Output Low Voltage
Output High Voltage
IOL = 5.8 mA, VCC = VCC Min.
VOH1
VOH2
IOH = -2.5 mA, VCC = VCC Min.
0.85 x VIH
VCC - 0.4
V
V
IOH = -100 υA, VCC = VCC Min.
VLKO
Low VCC
3.2
4.2
V
Lock-out Voltage
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component
(at 5 MHz). The frequency component typically is less than 2 mA/MHz, with /OE at VIH.
2. ICC active while Internal Algorithm (program or erase) is in progress.
3. Not 100% tested.
HY29F400A
23
AC CHARACTERISTICS
Read-Only Operations
-45(1)
45
45
45
30
15
15
0
-55(1)
55
55
55
30
15
15
0
-60(1)
60
60
60
30
20
20
0
-70(1)
70
70
70
30
20
20
0
-90(1)
90
90
90
35
20
20
0
-120(1)
120
120
120
50
- 150(1)
150
150
150
55
Unit
ns
Description
Test Setup
JEDEC
Standard
t
t
Read Cycle
Time(2)
Min.
AVAV
RC
t
t
/CE = V
IL
Address to
Max.
Max.
Max.
Max
Max.
Min.
ns
AVQV
ACC
/OE = V
/OE = V
Output Delay
Chip Enable to
Output Delay
Output Enable to
Output Delay
Chip Enable to
Output High Z(3,4)
Output Enable to
Output High Z(3,4)
Output Hold
Time from
IL
IL
t
t
ns
ELQV
CE
t
t
ns
GLQV
OE
t
t
30
35
ns
EHQZ
CF
t
t
30
35
ns
GHQZ
DF
t
t
0
0
ns
AXQX
OH
Addresses
Whichever
Occurs First
/RESET Pin Low
to Read Mode(4)
/CE to /BYTE
Switching Low
or High
t
Max.
Max.
20
5
20
5
20
5
20
5
20
5
20
5
20
5
us
ns
READY
t
ELFL
t
ELFH
Notes:
1. Test Conditions:
2. Output driver disable time.
3. Not 100% tested.
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 20 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level
Input: 0.8 and 2.0 V
Output: 0.8 and 2.0 V
HY29F400A
24
5.0 V
2.7 KOhm
IN3064 or
Equivalent
DEVICE
UNDER
TEST
C
L
Diodes = IN3064
or Equivalent
6.2 KOhm
Notes:
CL = 100pF including jig capacitance.
Figure 7. Test Condition
HY29F400A
25
AC CHARACTERISTICS
Programming/Erase Operations
Parameter Symbols
Description
-45
-55
-60
-70
-90
-120
-150
Unit
JEDEC
tAVAV
Standard
tW C
tAS
W rite Cycle Tim e(1)
Address Setup Tim e
Address Hold Tim e
Data Setup Tim e
Min.
Min.
Min.
Min.
Min
45
0
55
0
60
0
70
0
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
tAVW L
tW LAX
tAH
45
25
0
45
25
0
45
30
0
45
30
0
45
45
0
50
50
0
50
50
0
tDVW H
tW HDX
tDS
tDH
Data Hold Tim e
tOES
tOEH
Output Enable Setup Tim e
Min.
Min.
Min.
0
0
0
0
0
0
0
Output Enable
Hold Tim e
Read(1)
Toggle &
/Data
0
0
0
0
0
0
0
10
10
10
10
10
10
10
Polling(1)
tGHW L
tGHW L
Read Recovery Tim e Before
W rite
Min.
0
0
0
0
0
0
0
ns
tELW L
tCS
/CE Setup Tim e
Min.
Min.
Min.
Min.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Min.
Min.
0
0
0
0
0
0
0
ns
tW HEH
tW LW H
tW HW L
tW HW H1
tCH
/CE Hold Tim e
0
0
0
0
0
0
0
ns
tW P
W rite Pulse W idth
W rite Pulse W idth High
30
20
7
30
20
7
35
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
tW PH
tW HW H1
ns
Program m ing
Operation
Byte Mode
us
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
us
W ord
Mode
us
us
tW HW H2
tW HW H2
Sector Erase Operation(2)
sec
sec
sec
sec
us
8
8
8
8
8
8
8
tW HW H3
tW HW H3
Chip Erase Operation(2)
19
150
50
500
19
150
50
500
19
150
50
500
19
150
50
500
19
150
50
500
19
150
50
500
19
150
50
500
tVCS
Vcc Setup Tim e(1)
tVIDR
Rise Tim e to VID Rise and
Fall Tim e(1,3)
ns
tOESP
/OE Setup Tim e to /W E
Min.
4
4
4
4
4
4
4
us
3, 4)
Active(1,
tRP
/RESET Pulse W idth
/RESET Setup Tim e for
Tem porary Sector
Min.
Min.
500
4
500
4
500
4
500
4
500
4
500
4
500
4
ns
us
tRSP
3)
Unprotect(
tBUSY
Program m ing/Erase Valid to
RY/BY Delay(1)
Min.
30
30
30
30
35
50
55
ns
4)
tVLHT
Voltage Transition Tim e(1,
Min.
Min.
4
4
4
4
4
4
4
us
us
tW PP1
Sector Protect W rite Pulse
W idth(4)
100
100
100
100
100
100
100
tW PP2
Sector Unprotect W rite
Pulse W idth(4)
Min.
Min.
10
4
10
4
10
4
10
4
10
4
10
4
10
4
m s
us
tCSP
/CE Setup Tim e to /W E
4)
Active(1,
Notes:
1. Not 100% tested.
2. Does not include pre-programming time.
3. This timing is for Temporary Sector Unprotect operation.
4. These timings are for Sector Protect and/or Sector Unprotect perations.
HY29F400A
26
SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be Steady
Will Be Steady
May Change
from H to L
Will Be Changing
from H to L
May Change
from L to H
Will Be Changing
from L to H
Don`t Care,
Any Change
Permitted
Changing, State
Unknown
Does Not
Apply
Center Line is
High Impedance
(High Z) State
t
RC
Addresses
CE
Address Stable
tACC
tCF
tOE
OE
t
DF
tOEH
WE
t
CE
tOH
High Z
High Z
Outputs
Output Valid
Figure 8. AC Waveforms for Read Operations
HY29F400A
27
SWITCHING WAVEFORMS
Data Polling
PA
5555H
PA
Addresses
tAH
t
WC
t
AS
CE
t
GHWL
OE
tWP
tWHWH1
WE
tWPH
tCS
tDH
Data
5.0V
D
A0H
PD
DQ7
OUT
tDS
V
CC
GND
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. /DQ7 is the input of the complement of the data written to the device.
4. DOUT is the output of the array data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for 16-bit mode.
Figure 9. AC Waveforms Program Operations
HY29F400A
28
SWITCHING WAVEFORMS
tAS
tAH
5555H
2AAAH
5555H
5555H
2AAAH
SA
Addresses
CE
tGHWL
OE
tWP
WE
tWPH
tCS
tDH
Data
AAH
55H
80H
AAH
55H
10H/30H
tDS
tVCS
5.0V
VCC
GND
Notes:
1. SA is the sector address for Sector Erase. Address = X = Don't Care for Chip Erase.
2. These waveforms are for 16-bit mode.
Figure 10. AC Waveforms Chip/Sector Erase Operations
HY29F400A
29
SWITCHING WAVEFORMS
tCH
CE
OE
tDF
tOE
tOEH
WE
tCE
tOH
High
Z
DQ7
DQ7
DQ7=Valid Data
tWHWH 1 or 2
Data
DQ0-DQ7
Valid Data
DQ0-DQ6
DQ0-DQ6=Invalid
tOE
5.0V
CC
V
GND
Notes:
1. DQ7 = Valid Data (The device has completed the internal program or erase operation.)
Figure 11. AC Waveforms for /Data Polling during Internal Algorithm Operations
HY29F400A
30
SWITCHING WAVEFORMS
CE
tOEH
WE
tOES
OE
Data
(DQ0-DQ7)
DQ6 =
Stop Toggling
DQ0-DQ7
Valid
Data
DQ6 = Toggle
DQ6 = Toggle
tOE
5.0V
VCC
GND
Notes:
1. DQ6 stops toggling (The device has completed the internal program or erase operation.)
Figure 12. AC Waveforms for Toggle Bit during Internal Algorithm Operation
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
5.0V
VCC
GND
Figure 13. RY/ /BY Timing Diagram During Program/Erase Operation
HY29F400A
31
SWITCHING WAVEFORMS
RY/BY
RESET
RP
t PWH
Ready
Data
Valid Data
5.0V
VCC
GND
Figure 14. /RESET Timing Diagram
HY29F400A
32
SWITCHING WAVEFORMS
tWC
Addresses
CE
Address Stable
OE
tELFL
tDF
tOE
BYTE
tOH
tCE
Data Output
on DQ0-DQ7
High Z
High Z
Data Output
on DQ0-DQ7
Data
(DQ0-DQ7)
tACC
Data
Data
(DQ8-DQ14)
Output on
DQ8-DQ14
tFHQV
tFLQZ
Data
Output on
DQ15
DQ15/A-1
HIGH Z
Address
Input
High Z
Figure 15. /BYTE Timing Diagram for Read Operation
CE
The falling edge of the last WE signal
WE
BYTE
t SET
(tAS
)
t HOLD
(tAH
)
Figure 16. /BYTE Timing Diagram for Write Operation
HY29F400A
33
Start
RESET = V
(Note 1)
ID
Perform Erase or
Program Operations
RESET = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected again.
Figure 17. Temporary Sector Unprotect Algorithm
12V
5V
RESET
0 or 5V
tVIDR
CE
WE
tRSP
Program or Erase Command Sequence
RY/BY
Figure 18. Temporary Unprotect Timing Diagram
HY29F400A
34
START
Set Up Sector Address
(A17, A16, A15, A14, A13, A12)
PLSCNT = 1
/OE = VID , A9 = VID
/CE = VIL , /RESET = VIH
Activate /WE Pulse
Implement PLSCNT
Time Out 100 µs
Power Down /OE
/WE = VIH
/CE = /OE = VIL
A9 should remain VID
Read from Sector
Addr = SA, A0 = 0, A1 = 1,
A6 = 0
No
No
PLSCNT= 25
?
Data = 01H
?
Yes
Yes
Device Failed
Protect
Another Sector
?
Yes
No
Remove VID from A9
Write Reset Command
Sector Protect Completed
Notes:
1. SA = Sector Address
2. Sector Addresses can be found in Table 4 for top boot and Table 5 for bottom boot.
Figure 19. Sector Protection Algorithm
HY29F400A
35
SWITCHING WAVEFORMS
A17, A16, A15,
A14, A13, A12
SAX
SAY
A0
A1
A6
12V
5V
A9
tVLHT
tVLHT
12V
5V
OE
tVLHT
t OESP
tWPP1
WE
CE
Data
01H
tOE
Notes:
1. SAX = Sector Address for initial sector.
2. SAY = Sector Address for next sector.
Figure 20. AC Waveforms for Sector Protection
HY29F400A
36
Start
Protect All Sectors
PLSCNT=1
Set /OE = /CE = A9 = VID,
/RESET = VIH, A6 = 1,A0 = 0, A1 = 1
Activate /WE Pulse
Time Out 100us
Increment
PLSCNT
Set /CE = /OE = VIL
A9 = VID
Set Up Sector Address SA0
Read Data from Device
NO
NO
PLSCNT
=1000
?
Data=00H
?
Increment Sector Address
YES
YES
NO
Sector
Address = SA10
YES
Power Down A9
Device Failed
Sector Unprotection
Complected
Notes:
1. SA0 = Sector Address for initial sector.
2. SA10 = Sector Address for the last sector. (See Table 4 for details.)
Figure 21. Sector Unprotection Algorithm
HY29F400A
37
SWITCHING WAVEFORMS
SA0
SA1
A17:A12
A0
A1
12V
5V
A9
tVLHT
A6
12V
5V
OE
tVLHT
tWPP2
tVLHT
WE
tVCSP
5V
CE
Execute Auto Select
Command Sequence
00H
Data
Notes:
1. Starts with SA0 and sequences to SA6.
2. See Figure 21 for details.
Figure 22. AC Waveforms for Sector Unprotection
HY29F400A
38
AC CHARACTERISTICS
Alternate /CE Controlled Erase/Program Operations
Parameter Symbols
Description
-45
-55
-60
-70
-90
-120
-150
Unit
JEDEC
tAVAV
Standard
tWC
Write Cycle Time(1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min.
Min.
Min.
Min.
Min
45
0
55
0
60
0
70
0
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
tAVEL
tAS
tELAX
tAH
45
25
0
45
25
0
45
30
0
45
30
0
45
45
0
50
50
0
50
50
0
tDVEH
tEHDX
tDS
tDH
tOES
Output Enable Setup Time
Output Enable
Min.
Min.
Min.
0
0
0
0
0
0
0
tOEH
Read(1)
Toggle
& /Data
Polling(1)
0
0
0
0
0
0
0
Hold Time
10
10
10
10
10
10
10
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tGHEL
tWS
Read Recovery Time Before Write
/WE Setup Time
Min.
Min.
Min.
Min.
Min.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
0
0
0
0
0
0
0
ns
0
0
0
0
0
0
0
ns
tWH
/WE Hold Time
0
0
0
0
0
0
0
ns
tCP
/CE Pulse Width
30
20
7
30
20
7
35
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
tCPH
tWHWH1
/CE Pulse Width High
ns
tWHWH1
Programming Operation
Byte
us
Mode
Word
Mode
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
300
12
500
1
us
us
us
tWHWH2
tWHWH2
Sector Erase Operation(2)
Chip Erase Operation(2)
Vcc Setup Time(1,3)
sec
sec
sec
sec
us
8
8
8
8
8
8
8
tWHWH3
tWHWH3
19
150
50
500
4
19
150
50
500
4
19
150
50
500
4
19
150
50
500
4
19
150
50
500
4
19
150
50
500
4
19
150
50
500
4
tVCS
(1,3)
tVIDR
tVLHT
tWPP1
tWPP2
tOESP
tCSP
Rise Time to VID
ns
Voltage Transition Time(1, 3)
us
Sector Protect Write Pulse Width(4)
Sector Unprotect Write Pulse Width(4)
/OE Setup Time to /WE Active(1, 3)
/OE Setup Time to /WE Active(1, 4)
100
10
4
100
10
4
100
10
4
100
10
4
100
10
4
100
10
4
100
10
4
us
ms
us
4
4
4
4
4
4
4
us
Notes:
1. Not 100% tested.
2. Does not include pre-programming time.
3. This timing is for Sector Unprotect operation.
4. Output Driver Disable Time.
HY29F400A
39
SWITCHING WAVEFORMS
Data Polling
PA
5555H
tWC
PA
Addresses
CE
tAH
tAS
tGHWL
OE
tWP
tWHWH1
WE
tWPH
tCS
tDH
Data
DOUT
A0H
PD
DQ7
tDS
5.0V
VCC
GND
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. /DQ7 is the input of the complement of the data written to the device.
4. DOUT is the output of the array data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 23. Alternate /CE Controlled Program Operation Timings
HY29F400A
40
ERASE AND PROGRAMMING PERFORMANCE
Limits
Unit
Parameter
Min.
Typ.
Max.
Sector Erase Time
1.0
8
sec
sec
µs
Chip Erase Time
11
Byte Programming Time
Word Programming Time
Chip Programming Time
7
12
300
500
10.8
9.3
µs
Byte
3.6
sec
sec
cycles
Word
3.1
Erase/Program Cycles
100,000
1,000,000
LATCH UP CHARACTERISTICS
Parameter
Min.
-1.0V
Max.
Input Voltage with respect to Vss on all I/O pins
Vcc Current
Vcc + 1.0V
+ 100 mA
-100 mA
Notes:
1. Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter Parameter
Test
Symbol
Description
Setup
Typ.
6
Max.
7.5
12
Unit
pF
C
Input Capacitance
Output Capacitance
VIN = 0
IN
COUT
VOUT = 0
8.5
7.5
pF
CIN2
Control Pin Capacitance VIN = 0
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25¤º, f = 1.0 MHz.
PSOP PIN CAPACITANCE
Parameter Parameter
Test
Symbol
Description
Setup
Typ.
6
Max.
7.5
12
Unit
pF
C
Input Capacitance
Output Capacitance
VIN = 0
IN
COUT
VOUT = 0
8.5
7.5
pF
CIN2
Control Pin Capacitance VIN = 0
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions Min.
Unit
Minimum Pattern Data Retention Time
150 °C
125 °C
10
20
Years
Years
HY29F400A
41
PACKAGES DRAWINGS
PSOP44
44-Pin Small Outline Package (measured in millimeters)
23
44
15.70
16.30
13.10
13.50
0.10
0.21
0O
8O
0.60
1.00
1
22
1.27 NOM.
28.00
28.40
2.17
2.45
2.80
MAX.
SEATING PLANE
0.10
0.35
0.35
0.50
TSOP48
48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 ID
1
48
0.50 BSC
11.90
12.10
24
25
18.30
18.50
0.05
0.15
19.80
20.20
0.08
0.20
1.20
MAX
0.10
0.21
0o
5o
0.25MM (0.0098") BSC
0.50
0.70
HY29F400A
42
Ordering Information
Hyundai products are available in several packages and operating ranges.
The order number (Valid Combination) is formed by a combination of the following:
HY29F400A
X
-
X
X
X
SPECIAL INSTRUCTIONS
TEMPERATURE RANGE
Blank = Commercial (0°C to +70°C)
I
= Industrial (-40°C to +85°C)
E = Extended (-55°C to +125°C)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
PACKAGE TYPE
G = 44-Pin Plastic Small Outline Package
(PSOP)
T = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
R = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
DEVICE NUMBER/DESCRIPTION
HY29F400A
4 Megabit (512K x 8-Bit) or (256K x 16-Bit)
CMOS 5.0 volt-only
Sector Erase Flash Memory
VALID COMBINATIONS
VALID COMBINATIONS
Valid Combinations List configurations planned to
be supported in volume for this device. Consult the
local Hyundai sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
G-90, T-90, R-90
G-90I, T-90I, R-90I
G-90E, T-90E, R-90E
90ns
G-12, T-12, R-12
120ns
150ns
G-12I, T-12I, R-12I
G-12E, T-12E, R-12E
G-15, T-15, R-15
G-15I, T-15I, R-15I
G-15E, T-15E, R-15E
HY29F400A
43
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