HY51V65160ASLTC-50 [HYNIX]
Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50;
| 型号： | HY51V65160ASLTC-50 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 动态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY51V64160A,HY51V65160A
4Mx16, Fast Page mode
2nd Generation
DESCRIPTION
This family is a 64M bit dynamic RAM organized 4,194,304 x 16-bit configuration with Fast Page mode CMOS DRAMs.
Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow
this device to achieve high performance and low power dissipation. Optional features are access time(60 or 70ns) and
refresh cycle(8K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s advanced
circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high
reliability.
FEATURES
Ÿ Fast page mode operation
Ÿ JEDEC standard pinout
Ÿ Read-modify-write capability
50-pin plastic TSOP-II (400mil)
Ÿ Multi-bit parallel test capability
Ÿ Single power supply of 3.3 ± 0.3V
Ÿ LVTTL(3.3V) compatible inputs and outputs
Ÿ Early write or output enable controlled write
Ÿ /CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
Ÿ Max. Active power dissipation
Ÿ Fast access time and cycle time
Speed
50
8K refresh
4K refresh
504mW
Speed
50
tRAC
50ns
60ns
tCAC
13ns
15ns
tPC
35ns
40ns
396mW
324mW
60
432mW
60
Ÿ Refresh cycles
Part number
HY51V64160A1)
HY51V65160A2)
Refresh
Normal
L-part
8K
4K
64ms
128ms
1) Normal read / write, /RAS only refresh : 8K cycles / 64ms
/CAS-before-/RAS, Hidden refresh : 4K cycles / 64ms
2) Normal read / write, /RAS only refresh : 4K cycles / 64ms
/CAS-before-/RAS, Hidden refresh
: 4K cycles / 64ms
ORDERING INFORMATION
Part Name
HY51V64160ATC
HY51V64160ALTC
HY51V64160ASLTC
HY51V65160ATC
HY51V65160ALTC
Refresh
Power
Package
8K
8K
8K
4K
4K
4K
50Pin TSOP-II
50Pin TSOP-II
50Pin TSOP-II
50Pin TSOP-II
50Pin TSOP-II
50Pin TSOP-II
L-part
*SL-part
L-part
HY51V65160ASLTC
*SL-part
*SL : Self refresh with low power.
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
Hyundai Semiconductor
Rev.12/Sep.98
1
HY51V64160A,HY51V65160A
FUNCTIONAL BLOCK DIAGRAM
DQ0 ~ DQ15
8
8
8
8
Data Input Buffer
Data Output Buffer
OE
DQ0~7
DQ8~15
DQ0~7
DQ8~15
WE
8
8
8
8
LCAS
UCAS
CAS Clock
Generator
(9/10)*
Cloumn
A0
A1
Predecoder
Column Decoder
A2
Sense Amp
I/O Gate
A3
A4
A5
A6
Refresh Controller
Refresh Counter
A7
A8
A9
A10
A11
*(A12)
Row
Decoder
Memory Array
4,194,304x16
Row Predecoder
(13/12)*
(13/12)*
RAS Clock
Generator
RAS
VCC
VSS
Substrate Bias
Generator
X32 Parallel
Test
*(A12) for 8K refresh part
(8K Refresh / 4K Refresh)*
4Mx16,FP DRAM
Rev.12/Sep.98
2
HY51V64160A,HY51V65160A
PIN CONFIGURATION (Marking Side)
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
VCC
WE
RAS
N.C
N.C
N.C
N.C
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
·
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A1
A2
A3
A4
A9
A8
A7
A6
A5
VCC
VSS
50Pin Plastic TSOP- II (400mil)
A12(N.C)* : For 4K refresh product
PIN DESCRIPTION
Pin Name
/RAS
Parameter
Row Address Strobe
/CAS
Column Address Strobe
Write Enable
/WE
/OE
Output Enable
A0~A12
A0~A11
DQ0~DQ15
Vcc
Address Input (8K Refresh Product)
Address Input (4K Refresh Product)
Data In/Out
Power (3.3V)
Vss
Ground
NC
No Connection
4Mx16,FP DRAM
Rev.12/S3ep.98
3
HY51V64160A,HY51V65160A
ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Rating
0 to 70
-55 to 150
-0.5 to 6.0
-0.5 to 4.6
50
Unit
TA
Ambient Temperature
°C
TSTG
Storage Temperature
°C
VIN, VOUT
VCC
Voltage on Any Pin relative to VSS
Voltage on VCC relative to VSS
Short Circuit Output Current
Power Dissipation
V
V
IOS
mA
PD
1
W
TSOLDER
Soldering Temperature Ÿ Time
260 Ÿ 10
°C Ÿ sec
Note : Operation at or above Absolute Maximum Ratings could adversely affect device reliability and cause permanent
damage.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to 70°C )
Symbol
VCC
Parameter
Min
3.0
Typ
Max
3.6
UNIT
Power Supply Voltage
Input High Voltage
Input Low Voltage
3.3
V
V
V
VIH
2.0
-
-
VCC+0.31)
0.8
VIL
-0.32)
Note : All voltages are referenced to VSS.
1) 6.0V at pulse width 10ns which is measured at VCC.
2) -1.0V at pulse width 10ns which is measured at VSS.
DC AND OPERATING CHARACTERISTICS
Symbol
Parameter
Test condition
VSS £ VIN £ VCC + 0.3
Min
Max
Unit
ILI
Input Leakage Current
(Any input)
-5
5
5
mA
mA
V
All other pins not under test = VSS
ILO
Output Leakage Current
(Any input)
VSS £ VOUT £ VCC
/RAS&/CAS at VIH
-5
-
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.0mA
IOH = -2.0mA
0.4
-
2.4
V
4Mx16,FP DRAM
Rev.12/Sep.98
4
HY51V64160A,HY51V65160A
DC CHARACTERISTICS
(TA = 0°C to 70°C , VCC = 3.3 ± 0.3V , VSS = 0V, unless otherwise noted.)
Max. Current
Symbol
Parameter
Test condition
Speed
Unit
8K refresh
4K refresh
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
Operating Current
/RAS, /CAS Cycling
tRC = tRC(min.)
50
60
110
90
140
120
mA
mA
mA
mA
mA
mA
LVTTL Standby
Current
/RAS, /CAS ³ VIH
Other inputs ³ VSS
1
1
/RAS-only Refresh
Current
/RAS Cycling,/CAS = VIH
tRC = tRC(min.)
50
60
110
90
140
120
FP mode Current
/CAS Cycling, /RAS = VIL
tPC = tPC(min.)
50
60
90
80
100
90
CMOS Standby
Current
500
300
500
300
/RAS = /CAS ³ VCC - 0.2V
L-part
/CAS-before-/RAS
Refresh Current
50
60
140
120
140
120
tRC = tRC(min.)
VIH = VCC - 0.2V, VIL = 0.2V
/CAS = CBR cycling or 0.2V
/OE&/WE = VIH = VCC - 0.2V
Address = Don’t care
DQ0~DQ15 = Open, tRAS £ 300ns
tRC=31.25uS
ICC7
Battery Back-up
Current (L-part)
550
450
550
450
mA
mA
ICC8
Self Refresh Current
(L-part)
/RAS&/CAS = 0.2V
Other pins are same as ICC7
Note
1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC).
2. Specified values are obtained with output unloaded.
3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,
address can be changed maximum once while /CAS=VIH withen one FP mode cycle time tPC.
4Mx16,FP DRAM
Rev.12/Sep.98
5
HY51V64160A,HY51V65160A
AC CHARACTERISTICS
(TA = 0 °C to 70 °C, VCC = 3.3 ± 0.3V , VSS = 0V, unless otherwise noted.)
50ns
Max
60ns
Max
#
Symbol
Parameter
Unit
Note
Min
90
130
35
75
-
Min
110
150
40
83
-
1
2
3
4
5
6
7
8
9
tRC
Random read or write cycle time
Read-modify-write cycle time
Fast Page mode cycle time
Fast Page mode read-modify-write cycle time
Access time from /RAS
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tPC
-
-
-
-
tPRWC
tRAC
tCAC
tAA
-
-
50
60
4,5,9,10
4,5,9
4,5,10
4
Access time from /CAS
-
13
-
15
Access time from column address
Access time from /CAS precharge
/CAS to output low impedance
Output buffer turn-off delay from /CAS
Transition time(rise and fall)
/RAS precharge time
-
25
-
30
tCPA
tCLZ
-
30
-
35
0
-
0
-
3
10 tOFF
11 tT
0
13
0
13
2
50
2
50
4
12 tRP
30
50
50
13
50
13
15
10
5
-
40
60
60
15
60
15
20
15
5
-
13 tRAS
14 tRASP
15 tRSH
16 tCSH
17 tCAS
18 tRCD
19 tRAD
20 tCRP
21 tCP
/RAS pulse width
10K
10K
/RAS pulse width(Fast Page mode)
/RAS hold time
100K
100K
-
-
/CAS hold time
-
-
/CAS pulse width
10K
10K
/RAS to /CAS delay time
37
25
-
45
30
-
9
/RAS to column address delay time
/CAS to /RAS precharge time
/CAS precharge time
10
7
-
10
0
-
14
22 tASR
23 tRAH
24 tASC
25 tCAH
26 tRAL
27 tRCS
28 tRCH
29 tRRH
30 tWCH
31 tWP
Row address set-up time
0
-
-
Row address hold time
8
-
10
0
-
Column address set-up time
Column address hold time
Column address to /RAS lead time
Read command set-up time
Read command hold time referenced to /CAS
Read command hold time referenced to /RAS
Write command hold time
0
-
-
13
13
8
-
10
30
0
-
25
0
-
-
-
-
0
-
0
-
6
6
0
-
0
-
10
8
-
10
10
-
Write command pulse width
-
-
4Mx16,FP DRAM
Rev.12/Sep.98
6
HY51V64160A,HY51V65160A
AC CHARACTERISTICS
Continued
50ns
Max
60ns
Max
#
Symbol
Parameter
Unit
Note
Min
15
8
Min
15
10
0
32 tRWL
33 tCWL
34 tDS
35 tDH
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
-
-
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
16
7,19
7,19
11,12
11,12
11,12
8
0
-
-
Data-in hold time
10
-
-
10
-
-
Refresh period(4096 cycles)
Refresh period(8192 cycles)
Refresh period(SL-part)
64
64
36 tREF
-
64
-
64
-
128
-
128
37 tWCS
38 tCWD
39 tRWD
40 tAWD
41 tCSR
42 tCHR
43 tRPC
44 tCPT
45 tROH
46 tOEA
47 tOED
48 tOEZ
49 tOEH
50 tCPWD
51 tRHCP
52 tWRP
53 tWRH
54 tWTS
55 tWTH
56 tRASS
57 tRPS
58 tCHS
Write command set-up time
/CAS to /WE delay time
0
-
-
0
-
-
32
70
45
5
35
80
50
5
8,15
8
/RAS to /WE delay time
-
-
Column address to /WE delay time
/CAS set-up time(CBR cycle)
/CAS hold time(CBR cycle)
-
-
8
-
-
17
10
5
-
10
5
-
18
/RAS to /CAS precharge time
/CAS precharge time(CBR counter test)
/RAS hold time referenced to /OE
/OE access time
-
-
25
0
-
30
0
-
-
-
-
13
-
-
15
-
/OE to data delay
13
0
15
0
Output buffer turn-off delay time from /OE
/OE command hold time
15
-
15
-
6
8
13
50
30
10
10
10
10
100K
100
-50
15
55
35
10
10
10
10
100K
110
-50
/WE delay time from /CAS precharge
/RAS hold time from /CAS precharge
/WE to /RAS precharge time(CBR cycle)
/WE to /RAS hold time(CBR cycle)
Write command set-up time(test mode in)
Write command hold time(test mode in)
/RAS pulse width(self refresh)
/RAS precharge time(self refresh)
/CAS hold time(self refresh)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4Mx16,FP DRAM
Rev.12/Sep.98
7
HY51V64160A,HY51V65160A
TEST MODE
50ns
Max
60ns
Max
#
Symbol
Parameter
Unit
Note
Min
95
130
35
75
-
Min
115
150
40
83
-
1
2
3
4
5
6
7
8
tRC
Random read or write cycle time
Read-modify-write cycle time
Fast Page mode cycle time
Fast Page mode read-modify-write cycle time
Access time from /RAS
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tPC
-
-
-
-
tPRWC
tRAC
tCAC
tAA
-
-
55
65
4,5,9,10
4,5,9
4,5,10
4
Access time from /CAS
-
18
-
20
Access time from column address
Access time from /CAS precharge
/RAS pulse width
-
30
-
35
tCPA
-
35
-
40
13 tRAS
14 tRASP
15 tRSH
16 tCSH
17 tCAS
26 tRAL
38 tCWD
39 tRWD
40 tAWD
46 tOEA
47 tOED
49 tOEH
50 tCPWD
55
55
18
55
18
30
37
75
50
-
10K
65
65
20
65
20
35
40
85
55
-
10K
/RAS pulse width(Fast Page mode)
/RAS hold time
100K
100K
-
-
4
/CAS hold time
-
-
/CAS pulse width
10K
10K
Column address to /RAS lead time
/CAS to /WE delay time
-
-
-
-
15
8
/RAS to /WE delay time
-
-
Column address to /WE delay time
/OE access time
-
-
18
-
20
-
/OE to data delay
18
18
55
20
20
60
/OE command hold time
-
-
/WE delay time from /CAS precharge
-
-
8
4Mx16,FP DRAM
Rev.12/Sep.98
8
HY51V64160A,HY51V65160A
NOTE
1. An initial pause of 200ms is required after power-up followed by 8 /RAS-only refresh cycles before proper device
operation is achieved. In case of using internal refresh counter, a minimum of 8 /CAS- before-/RAS initialization
cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully initialized to be prevented
from being entered into multi bit parallel test mode during initialization.
2. If /RAS=VSS during power-up, the HY51V64160A, HY51V65160A could begin an active cycle. This condition results in
higher current than necessary current which is demanded from the power supply during power-up.
3. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order to minimize
the power-up current.
4. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min.) and VIL(max.), and are assumed to be 5ns for all inputs.
5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1TTL loads and 100pF.
6. Either tRCH or tRRH must be satisfied for a read cycle.
7. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modify-
write cycles and late write cycle.
8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS ³ tWCS(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle. If tRWD ³ tRWD(min.), tCWD ³ tCWD(min.), tAWD ³ tAWD(min), and tCPWD ³
tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither
of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
9. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.
10.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.
11.tREF(max)=128ms is applied to L-parts.
12.A burst of 4096(4K refresh part)or 8192(8K refresh part)/RAS-only refresh cycles must be executed within 64ms
(128ms for L-parts) after exiting self refresh.(CBR refresh & Hidden refresh : 4K cycle/64ms)
13.tASC,tCAH are referenced to the earlier /CAS falling edge.
14.tCP is specified from the last /CAS rising edge in the previous to the first /CAS falling edge in the next cycle.
15.tCWD is referenced to the later /CAS falling edge at word read-modifiy-write cycle.
16.tCWL is specified from /WE falling edge to the earlier /CAS rising edge.
17.tCSR is referenced to the earlier /CAS falling before /RAS transition low.
18.tCHR is referenced to the later /CAS rising high after /RAS transition low.
19.tDS is specified for the earlier /CAS falling edge and tDH is specified by the later /CAS falling edge in early write cycle.
CAPACITANCE
(TA = 0°C to 70°C , VCC = 3.3 ± 0.3V, VSS = 0V, f = 1MHz, unless otherwise noted.)
Symbol
Parameter
Input Capacitance (A0~A12)
Typ.
Max
Unit
pF
CIN1
-
-
-
5
7
7
CIN2
CDQ
Input Capacitance (/RAS, /CAS, /WE, /OE)
Data Input / Output Capacitance (DQ0~DQ15)
pF
pF
4Mx16,FP DRAM
Rev.12/Sep.98
9
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