HY51VS18163HG [HYNIX]
1M x 16Bit EDO DRAM; 1米x 16Bit的EDO DRAM
| 型号： | HY51VS18163HG |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 1M x 16Bit EDO DRAM |
| 文件： | 总12页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY51V(S)18163HG/HGL
1M x 16Bit EDO DRAM
PRELIMINARY
DESCRIPTION
The HY51V(S)18163HG/HGL is the new generation dynamic RAM organized 1,048,576 words x 16bit.
HY51V(S)18163HG/HGL has realized higher density, higher performance and various functions by utiliz-
ing advanced CMOS process technology. The HY51V(S)18163HG/HGL offers Extended Data Out Page-
Mode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)18163HG/HGL to be
packaged in standard 400mil 42pin SOJ and 44(50) pin TSOP-II. The package size provides high system
bit densities and is compatible with widely available automated testing and insertion equipment.
FEATURES
•
•
•
•
•
Extended Data Out Mode capability
Read-modify-write capability
Multi-bit parallel test capability
TTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
•
•
•
•
•
JEDEC standard pinout
42pin plastic SOJ / 44(50)pin TSOP-II (400mil)
Single power supply of 3.3V +/- 0.3V
Battery back up operation(L-version)
2CAS byte control
•
Fast access time and cycle time
Part No
tRAC
tCAC
tRC
tHPC
HY51V(S)18163HG/HGL-5
HY51V(S)18163HG/HGL-6
HY51V(S)18163HG/HGL-7
50ns
60ns
70ns
13ns
15ns
18ns
84ns
104ns
124ns
20ns
25ns
30ns
•
Power dissipation
•
Refresh cycle
Part No
50ns
60ns
70ns
Ref
Normal
L-part
Active
684mW
612mW
540mW
HY51V18163HG
HY51V18163HGL
1K
1K
16ms
7.2mW(CMOS level Max)
0.83mW (L-version : Max)
128ms
Standby
ORDERING INFORMATION
Part Number
Access Time
Package
HY51V(S)18163HGJ/HG(L)J-5
HY51V(S)18163HGJ/HG(L)J-6
HY51V(S)18163HGJ/HG(L)J-7
50ns
60ns
70ns
400mil 42pin SOJ
HY51V(S)18163HGT/HG(L)T-5
HY51V(S)18163HGT/HG(L)T-6
HY51V(S)18163HGT/HG(L)T-7
50ns
60ns
70ns
400mil 44(50)pin TSOP-II
(S) : Self refresh,
(L) : Low power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
HY51V(S)18163HG/HGL
PIN CONFIGURATION
1
50 VSS
CC
V
1
42
41
40
39
38
37
36
VSS
VCC
49
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
2
3
4
5
6
7
8
I/O15
2
I/O15
I/O14
I/O13
I/O12
VSS
I/O0
48
I/O14
3
I/O1
47
I/O13
4
I/O2
I/O12
46
5
I/O3
45 VSS
6
VCC
44
I/O11
7
I/O11
I/O4
43
I/O10
8
35 I/O10
9
I/O5
42
41
40
I/O9
I/O8
NC
9
34
10
11
I/O9
I/O6
10
33
I/O8
I/O7
11
32
NC
NC
12
31
LCAS
NC
NC
NC
36 NC
35
15
16
13
30
UCAS
WE
LCAS
14
29
34
33
32
31
30
29
OE
17
18
RAS
WE
UCAS
15
28
RAS
A9
OE
A9
A8
A7
A6
A11
19
A11
A10
A0
A1
A2
16
27
A8
A10
20
21
22
23
24
25
17
26
A7
A0
18
25
A6
A1
19
24
A5
A2
28 A5
27 A4
26
20
23
A4
A3
A3
VCC
21
22 VSS
VCC
VSS
42 Pin Plastic SOJ
44(50) Pin Plastic TSOP-II
PIN DESCRIPTION
Pin
Function
/RAS
/UCAS, /LCAS
/WE
Row Address Strobe
Column Address Strobe
Write Enable
/OE
Output Enable
A0-A9
A0-A9
I/O 0- I/O 15
Vcc
Address Inputs
Refresh Address Inputs
Data Input / Output
Power (3.3V)
Vss
Ground
NC
No connection
Rev.0.1/Apr.01
2
HY51V(S)18163HG/HGL
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
TA
Rating
0 ~ 70
Unit
oC
oC
Ambient Temperature
Storage Temperature
TSTG
-55 ~ 125
-0.5 ~ Vcc + 0.5
(Max 4.6V)
Voltage on Any Pin relative to Vss
VT
V
Voltage on Vcc relative to Vss
Short Circuit Output Current
Power Dissipation
Vcc
IOUT
PT
-0.5 ~ 4.6
V
mA
W
50
1
Note : Operation at or above absolute Maximum Ratings can adversely affect device reliability
Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Input High Voltage
Input Low Voltage
Vcc
VIH
VIL
3.0
2.0
3.3
3.6
Vcc + 0.3
0.8
V
V
V
-
-
-0.3
Note : All voltages are referenced to Vss
The supply voltage with all Vcc pins must be on the same level. The supply voltage with all Vss pins must be on the same level
Rev.0.1/Apr.01
3
HY51V(S)18163HG/HGL
Truth Table
/RAS
/LCAS
/UCAS
/WE
/OE
Output
Operation
Notes
D
L
H
D
H
L
D
D
Open
Valid
Standby
1 ,3
L
H
L
Lower byte
Upper byte
Word
H
L
L
H
L
Valid
Read cycle
1, 3
1, 2, 3
1, 2, 3
1, 3
L
L
H
L
Valid
L
L
H
L
L
D
Open
Lower byte
Upper byte
Word
H
L
L
L
D
D
Open
Early write cycle
L
L
L
Open
L
L
H
L
L
L
H
Undefined
Undefined
Undefined
Valid
Lower byte
Upper byte
Word
H
L
L
H
Delayed write cycle
L
L
L
L
H
L
H
L
H to L
H to L
H to L
D
L to H
L to H
L to H
D
Lower byte
Upper byte
Word
H
L
L
Valid
Read-modify-write
Cycle
L
L
Valid
H
L
H to L
H to L
H to L
L
Open
Word
CBR refresh
or
Self refresh
(L-series)
H
L
D
D
Open
Word
1, 3
L
D
D
Open
Word
H
L
L
L
H
L
D
H
D
H
Open
Open
Word
/RAS only refresh
cycle
1, 3
1, 3
Read cycle
(Output disabled)
Notes :
1. H : High ( inactive) L : Low ( active) D : H or L
2. tWCS >= 0ns Early write cycle
twcs < 0ns Delayed write cycle
3. Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS
active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output
High-Z control are done independently by each /UCAS, /LCAS
ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected
Rev.0.1/Apr.01
4
HY51V(S)18163HG/HGL
DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70°C)
Symbol
Parameter
Min
Max
Unit
Note
Output Level
Output Level voltage(Iout= -2mA)
VOH
2.4
Vcc
V
Output Level
Output Level voltage(Iout=2mA)
0
0.4
V
VOL
ICC1
50ns
60ns
70ns
-
-
-
190
170
150
Operating current
Average power supply operating current
( /RAS, /CAS Cycling : tRC = tRC min)
mA
1, 2
Standby current (TTL interface)
Power supply standby current
(/RAS, /CAS=VIH, Dout = High-Z)
ICC2
ICC3
-
2
mA
mA
50ns
60ns
70ns
50ns
60ns
70ns
-
-
-
-
-
-
-
-
-
-
-
190
170
150
185
165
145
1
/RAS only refresh current
Average power supply current
/RAS only refresh mode
(tRC= tRC min)
2
1, 3
5
EDO page mode current
Average power supply current
EDO page mode (tPC=tPC min)
ICC4
ICC5
ICC6
mA
CMOS interface ( /RAS, /CAS >= Vcc-0.2V, Dout = High-Z)
Standby current ( L-version)
mA
uA
150
190
170
150
50ns
60ns
70ns
/CAS-before-/RAS refresh current (tRC=tRC min)
mA
Battery back up operating current ( standby with CBR ref.)
(CBR refresh, tRC=31.3us, tRAS <= 0.3us, Dout = High-Z, CMOS interface)
-
-
-
400
5
uA
mA
uA
4, 5
1
ICC7
ICC8
Standby current
(RAS=VIH, /CAS=VIL, Dout=Enable)
Self refresh current
(/RAS, /CAS <=0.2V, Dout=High-Z)
ICC9
II(L)
250
5
-10
-10
10
10
uA
uA
Input leakage current, Any input (0V<= Vin<=4.6V)
IO(L) Output leakage current, (Dout is disabled, 0V<= Vout<=4.6V)
Note :
1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition
2. Address can be changed once or less while /RAS=VIL
3. Address can be changed once or less while /CAS=VIH
4. /CAS = L (<=0.2) while /RAS=L (<=0.2)
5. L-Version
Rev.0.1/Apr.01
5
HY51V(S)18163HG/HGL
CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C)
Parameter
Symbol
Min.
Max
Unit
Note
Input capacitance (Address)
Input capacitance (Clocks)
CI1
CI2
-
-
-
5
7
7
pF
pF
pF
1
1
Output capacitance (Data-in, Data-out)
CI/O
1, 2
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /CAS = VIH to disable Dout
AC CHARACTERISTICS (Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 18,19,20)
Test Condition
•
•
•
Input rise and fall times = 2ns
Input timing refrence levels : VIL=0V, VIH=3.0V
Input timing reference level : VIL/VIH = 0.8/2.0V
•
•
Output timing reference level :
VOL/VOH=0.8/0.2V
Output load : 1 TTL gate + CL (100pF)
( including scope and jig )
Read, Write, Read-modify-Write and Refresh Cycle
-50
-60
-70
Parameter
Symbol
Unit
Note
Min
84
30
8
Max
Min
104
40
10
60
10
0
Max
Min
124
50
13
70
13
0
Max
Random read or write cycle time
/RAS precharge time
tRC
tRP
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
/CAS precharge time
tCP
-
/RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
50
8
10,000
10,000
10,000
/CAS pulse width
10,000
10,000
10,000
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
/RAS to /CAS delay time
/RAS to Column address delay time
/RAS hold time
0
-
-
-
-
-
-
8
10
0
10
0
21
21
3
0
-
-
-
8
-
10
14
12
13
40
5
-
13
14
12
13
45
5
-
12
10
10
35
5
37
25
-
45
30
-
52
35
-
4
23
22
/CAS hold time
-
-
-
/CAS to /RAS precharge time
-
-
-
Rev.0.1/Apr.01
6
HY51V(S)18163HG/HGL
- continued -
-50
-60
-70
Parameter
Symbol
Unit
Note
Min
13
0
Max
-
Min
15
0
Max
-
Min
18
0
Max
-
/OE to Din delay time
/OE delay time from Din
/CAS delay time from Din
Transition time ( Rise and Fall)
Refresh period
tOED
tDZO
tDZC
tT
ns
ns
ns
ns
5
6
6
7
-
-
-
0
-
0
-
0
-
2
50
16
128
2
50
16
128
2
50
16
128
-
-
-
ms 1K Ref.
ms 1K Ref.
tREF
Refresh period (L-version)
-
-
-
Read Cycle
-50
-60
-70
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Min
Max
Access time from /RAS
Access time from /CAS
tRAC
tCAC
-
50
-
60
-
70
ns
ns
8,9
9,10,
17
-
-
13
25
-
-
15
30
-
-
18
35
9,11,
17
Access time from column address
tAA
ns
Access time from /OE
Read command set-up time
Read command hold time to /CAS
Read command hold time to /RAS
Column address to /RAS lead time
Column address to /CAS lead time
/CAS to output in low-Z
tOEA
tRCS
tRCH
tRRH
tRAL
tCAL
tCLZ
-
0
13
-
-
0
15
-
-
0
18
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
21
0
-
0
-
0
-
12,22
12
5
-
5
-
5
-
25
15
0
-
30
18
0
-
35
23
0
-
-
-
-
-
-
-
Output data hold time
tOH
3
-
3
-
3
-
27
tOHO
tOFF
tOEZ
tCDD
tRCHR
tOHR
tOFR
tWEZ
tWDD
tRDD
Output data hold time from /OE
Output buffer turn off time
3
-
3
-
3
-
-
13
13
-
-
15
15
-
-
15
15
-
13,27
13
Output buffer turn off time to /OE
/CAS to Din delay time
-
-
-
13
50
3
15
60
3
18
70
3
5
Read command hold time from /RAS
Output data hold time from /RAS
Output buffer turn-off time to /RAS
Output buffer turn off time to /WE
/WE to DIN delay time
-
-
-
-
-
-
27
27
-
13
13
-
-
15
15
-
-
15
15
-
-
-
-
13
13
15
15
18
18
/RAS to DIN delay time
-
-
-
Rev.0.1/Apr.01
7
HY51V(S)18163HG/HGL
Write Cycle
-50
-60
-70
Parameter
Symbol
Unit
Note
Min
0
Max
Min
0
Max
Min
0
Max
Write command set-up time
Write command hold time
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
tWCS
tWCH
tWP
tRWL
tCWL
tDS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
14,21
21
8
10
10
10
10
0
13
10
13
13
0
8
8
8
23
0
15,23
15,23
tDH
Data-in hold time
8
10
13
Read-Modify-Write Cycle
-50
-60
-70
Parameter
Symbol
Unit
Note
Min
111
67
Max
Min
136
79
Max
Min
161
92
Max
Read-modify-write cycle time
/RAS to /WE delay time
tRWC
tRWD
tCWD
tAWD
tOEH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
14
14
14
/CAS to /WE delay time
30
34
40
Column address to /WE delay time
/OE hold time from /WE
42
49
57
13
15
18
Refresh cycle
-50
-60
-70
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
/CAS set-up time
( /CAS-before-/RAS Refresh Cycle)
tCSR
tCHR
tRPC
5
-
5
-
5
-
ns
ns
ns
21
22
21
/CAS hold time
( /CAS-before-/RAS Refresh Cycle)
8
5
-
-
10
5
-
-
10
5
-
-
/RAS precharge to /CAS hold time
( /CAS-before-/RAS Refresh Cycle)
Rev.0.1/Apr.01
8
HY51V(S)18163HG/HGL
EDO Page Mode Cycle
-50
-60
-70
Parameter
Symbol
Unit
Note
Min
20
-
Max
Min
25
-
Max
Min
30
-
Max
EDO mode cyle time
EDO mode /RAS pulse width
Access time from /CAS precharge
/RAS hold time from /CAS precharge
Output data hold time from /CAS low
/CAS hold time referred /OE
tHPC
tRASP
tACP
-
-
-
ns
ns
25
16
100K
100K
100K
-
30
-
-
35
-
-
40
-
ns 9,17,22
ns
tRHCP
tDOH
tCOL
tCOP
30
3
35
3
40
3
-
-
-
ns
ns
ns
9
8
-
10
5
-
13
5
-
/CAS to /OE setup time
5
-
-
-
Read command hold time
from /CAS precharge
tRHCP
30
-
35
-
40
-
ns
EDO Page Mode Read-Modify-Write Cycle
-50
-60
-70
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
EDO Page read-modify-write cycle time
tHPRWC
tCPW
57
-
68
-
79
-
ns
ns
EDO mode read-modify-write cycle
/CAS precharge to /WE delay time
45
-
54
-
62
-
14,22
Self Refresh Mode(L-version)
-50
-60
-70
Parameter
Symbol
Unit
Note
Min
100
90
Max
Min
100
110
-50
Max
Min
100
130
-50
Max
/RAS pulse width (self refresh)
/RAS precharge time(self refresh)
/CAS hold time(self refresh)
tRASS
tRPS
-
-
-
-
-
-
-
-
-
us
ns
ns
29
tCHS
-50
Rev.0.1/Apr.01
9
HY51V(S)18163HG/HGL
Notes :
1. AC measurements assume tT = 2ns
2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles
( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh)
If the internal refresh counter is used, a minimum of eight /CAS-before-/RAS refresh cycle are required.
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times
are measured between VIH(min) and VIL(max)
8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown
9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.( VOH=2.0V, VOL=0.8V)
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max)
11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max)
12. Either tRCH of tRRH must be satified for a read cycles
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle :
If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell : if neither of the above sets of conditions
is satified, the condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to /CAS leading edge in early write cycles and to /WE
leading edge in delayed write or read-modify-write cycles
16. tRASP defines /RAS pulse width in EDO page mode cycles
Rev.0.1/Apr.01
10
HY51V(S)18163HG/HGL
17. Access time is determined by the longest among tAA or tCAC or tACP
18. In delayed write or read-modify-write cycels, OE must disable output buffer prior to applying data to the
device, After /RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance)
If tOEH < tCWL, invalid data will be out at each I/O
19. When both /UCAS and /LCAS go low at the same time, all 16 bit data are written into the device
/UCAS and /LCAS cannot be staggered within the same write / read cycles.
20. All the Vcc and Vss pins shall be supplied with the same voltages
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of /UCAS
or /LCAS.
22. tCRP, tCHR, tRCH, tACP and tCPW are determined by the later rising edge of /UCAS or /LCAS.
23. tCWL, tDH, tDS and tCSH should be satisfied by both /UCAS and /LCAS
24. tCP is determined by that time the both /UCAS and /LCAS are high.
25. tHPC(min) can be achieved during a series of EDO page mode write cycles or EDO mode write cycles
It both write and read operation are mixed in a EDO mode /RAS cycle(EDO mode mix cycle(1,2))
minimum value of /CAS cycle(tCAS+tCP+2tT) becomes greater than the specified tHPC(min) value.
The value of /CAS cycle time of mixed EDO mode is shown in EDO mode mix cycle (1) and (2)
26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained
When output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade VIH min / VIL max level
27. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS.
Hold time and turn off time are specified by the timing specification of later rising edge of /RAS and
/CAS between tOHR and tOH, and between tOFR and tOFF
28. EDO High-Z control by /OE or /WE. /OE rising edge disables data outputs. When /OE goes high
during /CAS high, the data will not come out until next /CAS access. When /WE goes low during
/CAS high, the data will not come out until next /CAS access
29. Please do not use tRASS timing, 10us<=tRASS<=100us. During this period, The device is in transition
state from normal operation mode to self refresh mode. If tRASS>=100us, then RAS
30. H or L ( H : VIH(min) <=VIN <= VIH(max), L : VIL(min) <= VIN <= VIL(max))
Rev.0.1/Apr.01
11
HY51V(S)18163HG/HGL
PACKAGE INFORMATION
42pin SOJ
Unit: Inches (mm)
0.025(0.64)
MIN
0.093(2.38)
MIN
1.058(26.89) MAX
1.072(27.23) MAX
0.128(3.25) MIN
0.148(3.75) MAX
0.050(1.27)
TYP
0.026(0.66) MIN
0.032(0.81) MAX
0.015(0.38) MIN
0.020(0.50) MAX
44(50)pin TSOP II
Deg
0.016(0.40) MIN
0.024(0.60) MAX
0 ~ 5
0.004(0.12) MIN
0.008(0.21) MAX
0.820(20.82) MIN
0.830(21.08) MAX
0.037(0.95) MIN
0.041(1.05) MAX
0.047(1.20)
MAX
0.012(0.30) MIN
0.017(0.45) MAX
0.031(0.80)
TYP
0.002(0.05) MIN
0.006(0.15) MAX
Rev.0.1/Apr.01
12
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