HY51VS65173HGLT-6I [HYNIX]
EDO DRAM, 4MX16, 60ns, CMOS, PDSO50;
| 型号： | HY51VS65173HGLT-6I |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | EDO DRAM, 4MX16, 60ns, CMOS, PDSO50 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
4M x 16Bit EDO DRAM ET Part
PRELIMINARY
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configuration with Extented Data Out
mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read opera-
tion. The advanced circuit and process allow this device to achieve high performance and low power dissi-
pation. Features are access time(45ns or 50ns) and refresh cycle(4K ref) and power consumption(Normal
or low power with self refresh).
Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to
achieve high speed access and high reliability
FEATURES
•
•
•
•
•
Extended data out operation
Read-modify-write capability
Multi-bit parallel test capability
LVTTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
•
JEDEC standard pinout
50pin plastic SOJ/TSOP-II(400mil)
Single power supply of 3.3V +/- 10%
Battery back up operation(L-version)
•
•
•
Fast access time and cycle time
Part No
tRAC
tAA
tCAC
tRC
tHPC
HY51V65173HG-45I
HY51V65173HG-5I
HY51V65173HG-6I
45ns
50ns
60ns
23ns
25ns
30ns
12ns
13ns
15ns
74ns
84ns
17ns
20ns
25ns
104ns
•
Power dissipation
•
Refresh cycle
Part No
45ns
50ns
60ns
Ref
Normal
L-part
Active
468mW
432mW
396mW
HY51V65173HG*
HY51V65173HGL*
4K Ref
4K Ref
64ms
1.8mW(CMOS level Max)
0.72mW (L-version : Max)
128ms
Standby
* : /RAS only, CBR and hidden refresh
ODERING INFORMATION
Part Number
Access Time
Package
HY51V65173HGJ-45
HY51V65173HGJ-5
HY51V65173HGJ-6
45ns
50ns
60ns
400mil 50pin SOJ
HY51V65173HGT-45I
HY51V65173HGT-5I
HY51V65173HGT-6I
45ns
50ns
60ns
400mil 50pin TSOP-II
(S) : Self refresh,
(L) : Low power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.0/Jan.01
HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
PIN CONFIGURATION
VCC
1
50 VSS
IO0
IO1
IO2
2
3
4
49
48
IO15
IO14
47 IO13
46
IO3
VCC
IO4
5
6
7
8
9
IO12
45
44
43
42
41
40
39
38
VSS
IO11
IO10
IO5
IO6
IO9
IO8
NC
IO7 10
NC
11
12
13
14
15
16
VCC
VSS
/WE
/LCAS
/UCAS
/RAS
37
36
35
34
NC
NC
/OE
NC
NC
NC 17
NC
A0
A1
A2
A3
A4
18
19
20
21
22
23
33
32
NC
A11
31
30
29
28
27
A10
A9
A8
A7
A5 24
A6
26 VSS
VCC 25
50 Pin Plastic SOJ / TSOP-II
PIN DESCRIPTION
Pin
Function
/RAS
/UCAS, /LCAS
/WE
Row Address Strobe
Column Address Strobe
Write Enable
/OE
Output Enable
A0-A11
A0-A11
I/O 0- I/O 15
Vcc
Address Inputs
Refresh Address Inputs
Data Input / Output
Power (3.3V)
Vss
Ground
NC
No connection
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HY51V65173HGT-45/5/6I
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
TA
Rating
Unit
oC
oC
Ambient Temperature
Storage Temperature
-40 ~ +85
-55 ~ 125
TSTG
-0.5 ~ Vcc + 0.5
(Max 4.6V)
Voltage on Any Pin relative to Vss
VT
V
Voltage on Vcc relative to Vss
Short Circuit Output Current
Power Dissipation
Vcc
IOUT
PT
-0.5 ~ 4.6
V
mA
W
50
1
Note : Operation at above absolute maximum rating can adversely affect device reliability.
Recommended DC OPERATING CONDITIONS (TA= -40 to 85 oC)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Vcc
Vss
VIH
VIL
3.0
0
3.3
3.6
0
V
V
V
V
1,2
2
0
-
2.0
-0.3
Vcc + 0.3
0.8
1
-
1
Note : All voltages are referenced to Vss
1. 6.0V at pulse width 10ns which is measured at Vcc
2. -0.1V at pulse width 10ns which is measured at Vss
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HY51V65173HGJ-45/5/6I
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DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA= -40 to 85°C)
Symbol
Parameter
Min
Max
Unit
Note
Output Level
Output Level voltage(Iout= -2mA)
VOH
2.4
Vcc
V
Output Level
Output Level voltage(Iout=2mA)
0
0.4
V
VOL
ICC1
45ns
50ns
60ns
-
-
-
130
120
110
Operating current ( tRC = tRC min)
mA
1, 2
Standby current (TTL interface)
Power supply standby current
(/RAS, /UCAS,/LCAS=VIH, Dout = High-Z)
ICC2
ICC3
-
1
mA
mA
45ns
50ns
60ns
45ns
50ns
60ns
-
-
-
-
-
-
-
-
-
-
-
130
120
110
100
90
/RAS only refresh current (tRC= tRC min)
2
1, 3
4
Extended data out page mode current
(/RAS=VIL, /CAS, Address cycling : tHPC=tHPC min)
ICC4
mA
80
CMOS interface ( /RAS, /UCAS, /LCAS >= Vcc-0.2V, Dout = High-Z)
Standby current ( L-version)
0.5
mA
uA
ICC5
200
130
120
110
45ns
50ns
60ns
ICC6
/CAS-before-/RAS refresh current (tRC=tRC min)
mA
Battery back up operating current (standby with CBR)
(tRC=31.25us, tRAS=300ns, Dout=High-Z)
-
-
-
350
5
uA
mA
uA
4, 5
1
ICC7
Standby current (CMOS)
ICC8 Power supply standby current
/RAS=VIH, /UCAS./LCAS=VIL, Dout=Enable)
Self refresh current
ICC9
350
5
(/RAS, /UCAS, /LCAS <=0.2V, Dout=High-Z)
-5
-5
5
5
uA
uA
II(L)
IO(L) Output leakage current, (Dout is disabled, 0V<= Vout<=Vcc)
Note :
Input leakage current, Any input (0V<= Vin<=Vcc)
1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition
2. Address can be changed once or less while RAS=VIL
3. Measured with one sequential address change per EDO cycle, tHPC
4. VIH>=Vcc-0.2V, 0V<=VIL<=0.2V
5. L-Version
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CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C)
Parameter
Symbol
Min.
Max
Unit
Note
Input capacitance (Address)
Input capacitance (Clocks)
CI1
CI2
-
-
-
5
5
7
pF
pF
pF
1
1
Output capacitance (Data-in, Data-out)
CI/O
1, 2
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /RAS, /UCAS and /LCAS = VIH to disable Dout
AC CHARACTERISTICS (Vcc=3.3V +/-10%, TA= -40~85C, Note 1, 2, 19,20)
Test Condition
•
•
•
Input rise and fall times = 2ns
Input level : VIL/VIH = 0.0 / 0.3V
Input timing reference level : VIL/VIH = 0.8/2.0V
•
•
Output timing reference level :
VOL/VOH=0.8/0.2V
Output load : 1 TTL gate + CL (100pF)
including scope and jig
Read, Write, Read-modify-Write and Refresh Cycles
-45I
-5I
-6I
Parameter
Symbol
Unit
Note
Min
74
25
7
Max
Min
84
30
8
Max
Min
104
40
10
60
10
0
Max
Random read or write cycle time
/RAS precharge time
tRC
tRP
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
24
/CAS precharge time
tCP
-
-
-
/RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
45
7
10,000
50
8
10,000
10,000
/CAS pulse width
10,000
10,000
10,000
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
/RAS to /CAS delay time
/RAS to Column address delay time
/RAS hold time
0
-
-
0
-
-
-
-
7
8
10
0
21
21
3
0
-
0
-
-
7
-
8
-
10
14
12
15
42
5
-
11
9
33
22
-
12
10
13
40
5
37
25
-
45
30
-
4
12
38
5
/CAS hold time
-
-
-
22
/CAS to /RAS precharge time
-
-
-
Rev.0.0/Jan.01
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HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
- continued -
-45I
-5I
-6I
Parameter
Symbol
Unit
Note
Min
12
0
Max
-
Min
13
0
Max
-
Min
15
0
Max
-
/OE to Din delay time
/OE delay time from Din
/CAS delay time from Din
Transition time ( Rise and Fall)
Refresh period
tODD
tDZO
tDZC
tT
ns
ns
ns
ns
5
6
6
7
-
-
-
0
-
0
-
0
-
2
50
64
128
2
50
64
128
2
50
64
128
-
-
-
ms 4K Ref.
ms 4K Ref.
tREF
Refresh period (L-version)
-
-
-
Read Cycles
-45I
-5I
-6I
Parameter
Symbol
Unit
Note
Min
-
Max
Min
-
Max
Min
-
Max
Access time from /RAS
Access time from /CAS
tRAC
tCAC
tAA
45
12
23
12
-
50
13
25
13
-
60
15
30
15
-
ns
8, 9
-
-
-
ns 9,10,17
ns 9,11,17
Access time from column address
Access time from /OE
-
-
-
tOAC
tRCS
tRCH
tRRH
tRAL
tCAL
tOFF
tOEZ
tCDD
tRDD
tWDD
tOFR
tWEZ
tOH
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
21
Read command set-up time
0
0
0
Read command hold time to /CAS
Read command hold time to /RAS
Column address to /RAS lead time
Column address to /CAS lead time
Output buffer turn off delay time from /CAS
Output buffer turn off delay time from /OE
/CAS to Din delay time
0
-
0
-
0
-
12,22
12
0
-
0
-
0
-
23
15
-
-
25
15
-
-
30
18
-
-
-
-
-
12
12
-
13
13
-
15
15
-
13,26
13
-
-
-
12
12
12
-
13
13
13
-
15
15
15
-
5
/RAS to Din delay time
-
-
-
/WE to Din delay time
-
-
-
Output buffer turn off delay time from /RAS
Output buffer turn off delay time from /WE
Output data hold time
12
12
-
13
13
-
15
15
-
13,26
13
-
-
-
3
3
3
26
tOHR
tRCHR
tOHO
tCLZ
Output data hold time from /RAS
Read command hold time from /RAS
Output data hold time from /OE
/CAS to output in low-Z
3
-
3
-
3
-
26
45
3
-
50
3
-
60
3
-
-
-
-
0
-
0
-
0
-
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HY51V65173HGT-45/5/6I
Write Cycles
-45I
-5I
-6I
Parameter
Symbol
Unit
Note
Min
0
Max
Min
0
Max
Min
0
Max
Write command set-up time
Write command hold time
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
tWCS
tWCH
tWP
tRWL
tCWL
tDS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
14,21
21
7
8
10
10
15
10
0
7
8
12
7
13
8
23
0
0
15, 23
15, 23
tDH
Data-in hold time
7
8
10
Read-Modify-Write Cycles
-45I
-5I
-6I
Parameter
Symbol
Unit
Note
Min
101
63
Max
Min
116
67
Max
Min
140
79
Max
Read-modify-write cycle time
/RAS to /WE delay time
tRWC
tRWD
tCWD
tAWD
tOEH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
14
14
14
/CAS to /WE delay time
30
30
34
Column address to /WE delay time
/OE hold time from /WE
40
42
49
12
13
15
Refresh cycles
-45I
-5I
-6I
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
/CAS set-up time
( /CAS-before-/RAS Refresh Cycle)
tCSR
tCHR
tWRP
tWRH
tRPC
5
-
5
-
5
-
ns
ns
ns
ns
ns
21
22
/CAS hold time
( /CAS-before-/RAS Refresh Cycle)
7
0
7
5
-
-
-
-
8
0
8
5
-
-
-
-
10
0
-
-
-
-
/WE set-up time
( /CAS-before-/RAS Refresh Cycle)
/WE hold time
( /CAS-before-/RAS Refresh Cycle)
10
5
/RAS precharge to /CAS hold time
( /CAS-before-/RAS Refresh Cycle)
21
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HY51V65173HGT-45/5/6I
Extended Data Out Mode Cycles
-45I
-5I
-6I
Parameter
Symbol
Unit
Note
Min
17
7
Max
Min
20
8
Max
Min
25
10
-
Max
EDO page mode cyle time
Write pulse width during /CAS precharge
EDO mode /RAS pulse width
tHPC
tWPE
tRASP
tACP
-
-
-
ns
ns
ns
25
-
-
-
-
100K
-
100K
100K
16
Access time from /CAS precharge
/RAS hold time from /CAS precharge
/CAS hold time referred /OE
-
28
-
-
28
-
-
35
-
ns 9,17,22
tRHCP
tCOL
tCOP
26
7
28
8
35
10
5
ns
ns
ns
-
-
-
/CAS to /OE set-up time
5
-
5
-
-
Read command hold time
from /CAS precharge
tRCHP
26
-
28
-
35
-
ns
Output data hold time from /CAS low
/OE precharge time
tDOH
tOEP
3
7
-
-
3
8
-
-
3
-
-
ns
ns
9,27
10
EDO Page Mode Read-Modify-Write Cycle
-45I
-5I
-6I
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
EDO read-modify-write cycle time
tHPRWC
tCPW
57
-
57
-
68
-
ns
ns
EDO page mode read-modify-write cycle
/CAS precharge to /WE delay time
45
-
45
-
54
-
14,22
Self Refresh Cycle (L-Version)
-45I
-5I
-6I
Parameter
Symbol
Unit
Note
Min
100
90
Max
Min
100
90
Max
Min
100
110
-50
Max
/RAS pulse width ( self refresh)
/RAS precharge time ( self refresh)
/CAS hold time ( self refresh)
tRASS
tRPS
-
-
-
-
-
-
-
-
-
us
ns
ns
31
31
23
tCHS
-50
-50
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Notes :
1. AC measurements assume tT = 2ns
2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles
( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh)
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times
are measured between VIH(min) and VIL(max)
8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown
9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max)
11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max)
12. Either tRCH of tRRH must be satified for a read cycles
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels
14 tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle :
If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell : if neither of the above sets of conditions
is satified, the condition of the data out (at access time) is indeterminate.
15. tDS and tDH are refered to /UCAS and /LCAS leading edge in early write cycles and to /WE leading
edge in delayed write or read-modify-write cycles
16. tRASP defineds /RAS pulse width in extended data out mode cycles
17. Access time is determined by the longest among tAA, tCAC and tACP
18 In delaying write or read-modify-write cycles, /OE must disable output buffer prior to applying data to
the device.
Rev 0.0 / Jan’01
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19. When output buffers are enabled once, sustain the low impedence state until valid data is obtained.
when output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade VIH min / VIL max level
20. When both /UCAS and /LCAS go low at the same time, all 16 bit data are written into the device.
/UCAS and /LCAS cannot be staggered within the same write / read cycles
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of /UCAS or /LCAS
22. tCRP, tCHR, tRCH,tACP and tCPW are determined by the later rising edge of /UCAS or /LCAS
23. tCWL, tDH, tDS and tCHS should be satified by the both /UCAS and /LCAS
24. tCP is determined by the time that both /UCAS and /LCAS are high
25. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycels
If both write and read operation are mixed in a EDO mode, /RAS cycle[EDO mode mix cycle (1)(2)]
minimum value of /CAS cycle tHPC[tCAS + tCP + 2tT] become greater than the specified tHPC(min)
value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle
(1) and (2)
26. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of /RAS and
/CAS between tOHR and tOH and between tOFR and tOFF
27. tDOH defines the time at which the output level go cross, VOL=0.8V, VOH=2.0V of output timing
reference level.
28. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64ms
period on the condition a) and b) below
a) Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
b) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6us after
exiting from self refresh mode
29. In case of entering from /RAS-only-refresh, It is necessary to execute CBR refresh before and after
self refresh mode according as note 28
30. For L-version, It is available to apply each 128ms and 31.2us instead of 64ms and 15.6us at note 28
31. At tRASS > 100us, self refresh mode is activated, and not active at tRASS < 10us, It is undefined within
the range of 10us < tRASS < 100us. For tRASS > 10us, It is necessary to satify tRPS
32. XXX : H or L [ H : VIH(min) <= VIN <=VIH(max), L : VIH(min) <=VIN <=VIH(max)]
///// : Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL
Rev 0.0 / Jan’01
HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
PACKAGE INFORMATION
400mil 50pin TSOP- II Dimension
Unit: mm
0.40 MIN
20.95 MIN
21.35 MAX
0 ~ 5 deg.
0.60 MAX
0.145
0.125
0.05
0.04
1.15 MAX
0.80
0.30 0.10
0.28 0.08
0.80
0.08 MIN
0.18 MAX
0.10
Dimension including the plating thickness
Base material dimension
Rev.0.0/Jan.01
11
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