HY57V161610FT-5I [HYNIX]
Synchronous DRAM, 1MX16, 4.5ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, TSOP2-50;
| 型号： | HY57V161610FT-5I |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Synchronous DRAM, 1MX16, 4.5ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, TSOP2-50 动态存储器 光电二极管 |
| 文件： | 总13页 (文件大小：1120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16Mb Synchronous DRAM based on 512K x 2Bank x16 I/O
Document Title
2Bank x 512K x 16bits Synchronous DRAM
Revision History
Revision No.
History
Initial Draft
Final Revision
Draft Date
Feb. 2006
Apr. 2006
Remark
0.1
1.0
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.0 / Apr. 2006
1
11
Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
DESCRIPTION
THE Hynix HY57V161610F-Series is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory
and graphic applications which require large memory density and high bandwidth. HY57V161610F-Series is organized
as 2banks of 524,288x16.
HY57V161610F-Series is offering fully synchronous operation referenced to a positive edge clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a '2N' rule.)
FEATURES
•
•
•
Voltage: VDD, VDDQ 3.3V supply voltage
•
•
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
4096 Refresh cycles / 64ms
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of
pin pitch (Lead or Lead Free Package)
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency; 1, 2, 3 Clocks
Burst Read Single Write operation
•
All inputs and outputs referenced to positive edge of
system clock
•
•
Data mask function by UDQM, LDQM
Internal two banks operation
•
•
ORDERING INFORMATION (VDD(min) of HY57V161610FT(P)-5(I) series is 3.15V)
Part No.
Clock Frequency
Organization
Interface
Package
HY57V161610FT(P)-5(I)
HY57V161610FT(P)-6(I)
HY57V161610FT(P)-7(I)
HY57V161610FT(P)-H(I)
200MHz
166MHz
143MHz
133MHz
400mil
50TSOPII
2Banks x 512Kbits x16I/O
LVTTL
Note: 1. HY57V161610FTP Series: Lead free, commercial temperature(0oC ~ 70oC.)
2. HY57V161610FT Series: Leaded, commercial temperature(0oC ~ 70oC.)
3.HY57V161610FTP-xxI Series: Lead free, Industrial temperature(-40oC ~ 85oC)
4.HY57V161610FT-xxI Series: Leaded, Industrial temperature(-40oC ~ 85oC)
Rev. 1.0 / Apr. 2006
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11
Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
PIN CONFIGURATION
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
2
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50Pin TSOPII
400mil x 825mil
0.8mm pin pitch
UDQM
CLK
CKE
NC
BA
A9
A10
A8
A0
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
Clock: The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CLK
INPUT
INPUT
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among (deep) power down, suspend or self refresh
CKE
CS
BA
INPUT
INPUT
Chip Select: Enables or disables all inputs except CLK, CKE, and DQM
Bank Address: Select either one of banks during both RAS and CAS activity
Row Address: RA0 ~ RA10, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
A0 ~ A10
INPUT
INPUT
INPUT
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
UDQM, LDQM
Data Mask: Controls output buffers in read mode and masks input data in write
mode
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
NC
I/O
SUPPLY
SUPPLY
-
Data Input / Output: Multiplexed data input / output pin
Power supply for internal circuits
Power supply for output buffers
No connection : These pads should be left unconnected
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
FUNCTIONAL BLOCK DIAGRAM
512K x 2Banks x 16 I/O Synchronous DRAM
Self Refresh Counter
Refresh
Interval Timer
Refresh
Counter
512Kx16
Bank 0
Address[0:10]
Sense AMP & I/O gates
Column Decoder
DQ0
DQ1
DQ2
DQ3
CLK
CKE
Address
Register
Precharge
Row Active
BA(A11)
DQ4
DQ5
DQ6
DQ7
DQ8
Column Addr.
Latch & Counter
Column Active
CS
RAS
CAS
WE
Overflow
Burst Length
Counter
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQM
LDQM
Column Decoder
Sense AMP & I/O gates
512Kx16
Bank 1
Mode Register
Test Mode
I/O Control
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Bank
Address
0
OP Code
0
0
CAS Latency
BT
Burst Length
OP Code
A9
0
Write Mode
Burst Read and Burst Write
Burst Read and Single Write
1
Burst Type
A3
0
Burst Type
Sequential
Interleave
1
CAS Latency
Burst Length
A6
0
A5
0
A4
0
CAS Latency
Burst Length
A2
A1
A0
R e s e r v e d
1
A3 = 0
A3=1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
4
8
0
1
0
2
0
1
1
3
4
1
0
0
Reserved
R e s e r v e d
R e s e r v e d
Reserved
8
1
0
1
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
1
1
0
1
1
1
Rev. 1.0 / Apr. 2006
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11
Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
ABSOLUTE MAXIMUM RATING
Parameter
Symbol
TA
Rating
Unit
Note
commercial
temp.
oC
0 ~ 70
Ambient Temperature
Industrial
temp.
oC
-40 ~ 85
oC
V
V
mA
Storage Temperature
TSTG
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
Voltage on Any Pin relative to VSS
Voltage on VDD supply relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
VDD, VDDQ
IOS
PD
1
W
Soldering Temperature . Time
260 . 10
oC . Sec
TSOLDER
Note: 1. HY57V161610FTP Series: Lead free, commercial temperature(0oC ~ 70oC.)
2. HY57V161610FT Series: Leaded, commercial temperature(0oC ~ 70oC.)
3.HY57V161610FTP-xxI Series: Lead free, Industrial temperature(-40oC ~ 85oC)
4.HY57V161610FT-xxI Series: Leaded, Industrial temperature(-40oC ~ 85oC)
o
o
DC OPERATING CONDITION (TA= 0 to 70 C, TA= -40 to 85 C,)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
Typ
3.3
3.0
-
Max
3.6
VDDQ+0.3
0.8
Unit
Note
1, 4, 5
1, 2
V
V
V
VIL
-0.3
1, 3
Note: 1. All voltages are referenced to VSS = 0V
2. VIH (max) is acceptable 4.6V AC pulse width with <=3ns of duration.
3. VIL (min) is acceptable -1.5V AC pulse width with <=3ns of duration.
4. VDD(min) is 3.15V when HY57V161610FT(P)-7 operates at CAS latency=2
5. VDD(min) of HY57V161610FT(P)-5 is 3.15V
o
4)
o
5)
AC OPERATING TEST CONDITION (TA= 0 to 70 C , TA= -40 to 85 C
)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
VIH / VIL
Vtrip
Value
2.4 / 0.4
1.4
Unit
V
V
ns
V
pF
Note
tR / tF
Voutref
CL
1
1.4
30
1
Note 1. See to Output Load Circuit Fig.
2. VDD(min) is 3.15V when HY57V161610ET-7 operates at CAS latency=2 and tCK2=8.9ns
3. VDD(min) of HY57V161610ET-5 is 3.15V
4. HY57V161610FT(P) Series: Leaded, commercial temperature(0oC ~ 70oC.)
5. HY57V161610FT(P)-xxI Series: Lead free, Industrial temperature(-40oC ~ 85oC)
Rev. 1.0 / Apr. 2006
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11
Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
o
CAPACITANCE (TA= 25 C, f=1MHz)
Parameter
Pin
Symbol
Min
Max
Unit
CLK
CI1
2.5
4.0
pF
Input capacitance
A0 ~ A10, BA, CKE, CS, RAS, CAS, WE,
LDQM, UDQM
CI2
2.5
4
5
pF
pF
Data input / output capacitance
DQ0 ~ DQ15
CI/O
6.5
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
30pF
30pF
DC Output Load Circuit
AC Output Load Circuit
o
5)
o
6)
DC CHARACTERRISTICS I (TA= 0 to 70 C , TA= -40 to 85 C
)
Parameter
Symbol
Min
Max
Unit
Note
Power Supply Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
VDD
ILI
3.0
-1
-1
2.4
-
3.6
1
V
uA
uA
V
1, 2
3
ILO
VOH
VOL
1
4
-
IOH = -4mA
IOL = +4mA
0.4
V
Note :
1.VDD(min) is 3.15V when HY57V161610FT(P)-7 operates at CAS latency=2 and tCK2=8.9ns.
2.VDD(min) of HY57V161610FT(P)-5 is 3.15V
3.VIN = 0 to 3.6V, All other pins are not under test = 0V
4. DOUT is disabled, VOUT=0 to 3.6V
5. HY57V161610FT(P) Series: Leaded, commercial temperature(0oC ~ 70oC.)
6. HY57V161610FT(P)-xxI Series: Lead free, Industrial temperature(-40oC ~ 85oC)
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
o
4)
o
5)
DC CHARACTERISTICS II (TA= 0 to 70 C , TA= -40 to 85 C
)
Speed
Uni
t
Not
e
Parameter
Operating
Symbol
Test Condition
5
6
7
H
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
IDD1
130 120
110
110
mA
mA
2
Current
Precharge
IDD2P
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
2
1
Standby Current
in power down
mode
IDD2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= 15ns
Input signals are changed one time
during 2clks.
Precharge
IDD2N
25
Standby Current
in non power
down mode
mA
mA
All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD2NS
IDD3P
15
Active Standby
Current
CKE ≤ VIL(max), tCK = 15ns
3.0
in power down
mode
IDD3PS
CKE ≤ VIL(max), tCK = ∞
3.0
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= 15ns
Input signals are changed one time
during 2clks.
Active Standby
Current
in non power
down mode
IDD3N
50
30
mA
mA
All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD3NS
IDD4
Burst Mode
Operating
Current
tCK ≥ tCK(min),
IOL=0mA
All banks active
CL=3
CL=2
130 120
110
130 110
110
110
110
-
3
-
Auto Refresh
Current
IDD5
IDD6
tRC ≥ tRC(min), All banks active
CKE ≤ 0.2V
110
110
mA
mA
Self Refresh
Current
2
Note :
1.VDD(min) is 3.15V when HY57V161610FT(P)-7 operates at CAS latency=2 and tCK2=8.9ns.
2.VDD(min) of HY57V161610FT-5 is 3.15V
3. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
4. HY57V161610FT(P) Series: Leaded, commercial temperature(0oC ~ 70oC.)
5. HY57V161610FT(P)-xxI Series: Lead free, Industrial temperature(-40oC ~ 85oC)
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
5
6
7
H
Sym-
bol
Parameter
Unit Note
Min Max Min Max Min Max Min Max
CL = 3
CL = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
5.0
10
2.0
2.0
-
6.0
10
2.0
2.0
-
7.0
10
2.0
2.0
-
7.5
10
2.5
2.5
-
ns
ns
System Clock Cycle
Time
1000
1000
1000
1000
Clock High Pulse Width
Clock Low Pulse Width
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
-
-
-
-
CL = 3
CL = 2
4.5
5.4
5.4
5.4
Access Time From
Clock
2
-
6.0
-
6.0
-
6.0
-
6.0
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
-
-
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
tDS
-
-
-
-
1
1
1
1
1
1
1
1
tDH
-
-
-
-
tAS
-
-
-
-
tAH
-
-
-
-
-
-
-
-
tCKS
tCKH
tCS
CKE Hold Time
-
-
-
-
Command Setup Time
Command Hold Time
-
-
-
-
tCH
-
-
-
-
CLK to Data Output in Low-Z Time tOLZ
-
-
-
-
CL = 3
CL = 2
tOHZ3
tOHZ2
4.5
6.0
5.4
6.0
5.4
6.0
5.4
6.0
CLK to Data Output
in High-Z Time
-
-
-
-
Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
5
6
7
H
Sym-
bol
Parameter
Unit Note
Min
Max
Min
Max
Min
Max Min Max
RAS Cycle Time Operation tRC
Auto
55
-
60
-
63
-
-
63
63
-
-
ns
ns
RAS Cycle Time
tRRC
55
15
-
-
60
-
63
Refresh
RAS to CAS Delay
RAS Active Time
tRCD
tRAS
tRP
18
42
18
-
100K
-
20
42
20
-
100K
-
20
42
20
-
120K
-
ns
ns
ns
38.7 100K
RAS Precharge Time
15
10
1
-
-
-
-
RAS to RAS Bank Active De-
lay
tRRD
tCCD
tWTL
12
1
-
-
-
14
1
-
-
-
15
1
-
-
-
ns
CAS to CAS Delay
CLK
CLK
Write Command to
Data-In Delay
0
0
0
0
Data-in to Precharge Com-
mand
tDPL
2
-
2
-
2
-
2
-
CLK
2
Data-In to Active Command tDAL
tDPL + tRP
DQM to Data-Out Hi-Z
DQM to Data-In Mask
MRS to New Command
tDQZ
2
0
2
3
-
-
-
-
2
0
2
3
-
-
-
-
2
0
2
3
-
-
-
-
1
0
2
3
-
-
-
-
CLK
CLK
CLK
CLK
tDQM
tMRD
tPROZ3
Precharge to
Data Output
High-Z
CL = 3
CL = 2
tPROZ2
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
tDPE
tSRE
tREF
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
CLK
CLK
ms
1
64
64
64
64
Note: 1. A new command can be given tRRC after self refresh exit.
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
COMMAND TRUTH TABLE
Command
CKEn-1 CKEn
CS
L
RAS CAS WE DQM ADDR A10/AP
BA
Note
Mode Register Set
H
H
H
X
X
X
L
X
H
L
L
X
H
H
L
X
H
H
X
X
X
OP code
H
L
No Operation
X
Bank Active
Read
L
RA
V
V
L
H
L
H
H
H
X
X
L
L
H
H
L
L
H
L
X
X
X
CA
CA
X
Read with Autopre-
charge
Write
V
Write with Autopre-
charge
H
H
L
Precharge All Banks
X
V
X
X
L
L
L
H
H
L
L
Precharge
Bank
selected
Burst Stop
DQM
H
H
H
H
X
V
X
X
X
X
Auto Refresh
H
X
L
L
L
L
L
L
L
H
L
X
Burst-Read-Single-
WRITE
A9 ball High
(Other balls OP code)
MRS
Mode
H
H
X
X
Entry
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
Self Refresh1
X
Exit
L
H
L
H
L
X
X
X
H
L
Entry
Exit
Precharge
power down
X
X
H
L
H
H
L
Entry
Exit
H
L
L
X
X
Clock
pend
Sus-
H
X
Rev. 1.0 / Apr. 2006
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Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
PACKAGE INFORMATION
400mil 50pin Thin Small Outline Package (TC)
1Mx16 Synchronous DRAM
11.938(0.4700)
11.735(0.4620)
10.262(0.4040)
10.059(0.3960)
0.45(0.0177)
0.8(0.0315 BSC)
0.30(0.0118)
1.2(0.0472)
1.0(0.0394)
0.150(0.0059)
0.050(0.0020)
21.057(0.8290)
20.879(0.8220)
0.646 REF
GAGE PLANE
0~5deg
0.210(0.0083)
0.120(0.0118)
0.597(0.0235)
0.406(0.0160)
Rev. 1.0 / Apr. 2006
13
相关型号：
HY57V161610FT-6I
Synchronous DRAM, 1MX16, 5.4ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, TSOP2-50
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HY57V161610FT-H
Synchronous DRAM, 1MX16, 5.4ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, TSOP2-50
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HY57V161610FT-HI
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HY57V161610FTP-5
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HY57V161610FTP-6
Synchronous DRAM, 1MX16, 5.4ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50
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HY57V161610FTP-6I
Synchronous DRAM, 1MX16, 5.4ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50
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HY57V161610FTP-7
Synchronous DRAM, 1MX16, 5.4ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50
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Synchronous DRAM, 1MX16, 5.4ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50
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