HY57V281620ET-5_技术文档

128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

Document Title

4Bank x 2M x 16bits Synchronous DRAM

Revision History

Revision No.

History

Draft Date

Dec. 2004

Jan. 2005

Remark

1.0

1.1

First Version Release

1. Corrected PIN ASSIGNMENT A12 to NC

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 1.1 / Jan. 2005

1

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

DESCRIPTION

The Hynix HY57V281620E(L)T(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory

applications which require wide data I/O and high bandwidth. HY57V281620E(L)T(P) series is organized as 4banks of

2,097,152 x 16.

HY57V281620E(L)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and

outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve

very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-

quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or

can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-

stricted by a '2N' rule)

FEATURES

•

Voltage: VDD, VDDQ 3.3V supply voltage

All device pins are compatible with LVTTL interface

54 Pin TSOPII (Lead or Lead Free Package)

•

Auto refresh and self refresh

4096 Refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency; 2, 3 Clocks

Burst Read Single Write operation

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by UDQM, LDQM

Internal four banks operation

•

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY57V281620E(L)T(P)-5

HY57V281620E(L)T(P)-6

HY57V281620E(L)T(P)-7

HY57V281620E(L)T(P)-H

200MHz

166MHz

143MHz

133MHz

4Banks x 2Mbits x16

LVTTL

54 Pin TSOPII

Note:

1. HY57V281620ET Series: Normal power, Leaded.

2. HY57V281620ELT Series: Low power, Leaded.

3. HY57V281620ETP Series: Normal power, Lead Free.

4. HY57V281620ELTP Series: Low power, Lead Free.

Rev. 1.1 / Jan. 2005

2

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

PIN ASSIGNMENTS

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

/WE

/CAS

/RAS

/CS

VSS

2

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54 Pin TSOPII

400mil x 875mil

0.8mm pin pitch

NC

UDQM

CLK

CKE

NC

BA0

A11

BA1

A9

A10/AP

A0

A8

A7

A1

A6

A2

A5

A3

A4

VDD

VSS

Rev. 1.1 / Jan. 2005

3

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

PIN DESCRIPTION

SYMBOL

TYPE

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM

on the rising edge of CLK

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will

be one of the states among power down, suspend or self refresh

CKE

CS

Clock Enable

Chip Select

Enables or disables all inputs except CLK, CKE, UDQM and LDQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

Bank Address

Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8

Auto-precharge flag: A10

A0 ~ A11

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

UDQM, LDQM

Controls output buffers in read mode and masks input data in write

mode

Data Input/Output Mask

DQ0 ~ DQ15

VDD/VSS

VDDQ/VSSQ

NC

Data Input/Output

Multiplexed data input / output pin

Power Supply/Ground

Power supply for internal circuits and input buffers

Data Output Power/Ground Power supply for output buffers

No Connection

No connection

Rev. 1.1 / Jan. 2005

4

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

FUNCTIONAL BLOCK DIAGRAM

2Mbit x 4banks x 16 I/O Synchronous DRAM

Internal Row

Counter

Self refresh

logic & timer

2Mx16 BANK 3

2Mx16 BANK 2

2Mx16 BANK 1

2Mx16 BANK 0

CLK

Row

Pre

Decoder

Row Active

CKE

CS

DQ0

RAS

CAS

Refresh

Memory

Cell

Array

Column

Active

Column

Pre

WE

Decoder

DQ15

U/LDQM

Y-Decoder

Column Add

Counter

Bank Select

Address

Register

A0

A1

Burst

Counter

Pipe Line

Control

A11

BA1

BA0

CAS Latency

Mode Register

Data Out Control

Rev. 1.1 / Jan. 2005

5

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

BASIC FUNCTIONAL DESCRIPTION

Mode Register

BA1

0

BA0

0

A11

0

A10

0

A9

A8

0

A7

0

A6

A5

A4

A3

BT

A2

A1

A0

OP Code

CAS Latency

Burst Length

OP Code

A9

0

Write Mode

Burst Read and Burst Write

Burst Read and Single Write

Burst Type

1

A3

0

Burst Type

Sequential

Interleave

1

CAS Latency

Burst Length

A6

0

A5

0

A4

0

CAS Latency

R e s e r v e d

1

Burst Length

A2

A1

A0

A3 = 0

A3=1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

2

4

8

0

1

0

2

0

1

3

4

1

0

Reserved

R e s e r v e d

Reserved

8

1

0

1

Reserved

Full Page

Reserved

1

0

1

Rev. 1.1 / Jan. 2005

6

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

ABSOLUTE MAXIMUM RATING

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

0 ~ 70

^oC

V

mA

Storage Temperature

TSTG

VIN, VOUT

VDD, VDDQ

IOS

-55 ~ 125

-1.0 ~ 4.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

PD

1

W

^oC / Sec

Soldering Temperature / Time

TSOLDER

260 / 10

o

DC OPERATING CONDITION (TA= 0 to 70 C)

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Symbol

VDD, VDDQ

VIH

Min.

3.0

2.0

Typ

3.3

3.0

-

Max

Unit

Note

1

1, 2

1, 3

3.6

VDDQ + 0.3

0.8

V

VIL

-0.3

Note: 1. All voltages are referenced to VSS = 0V

2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration

o

AC OPERATING TEST CONDITION (TA= 0 to 70 C, VDD=3.3±0.3V, VSS=0V)

Parameter

AC Input High / Low Level Voltage

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

Symbol

VIH / VIL

Vtrip

Value

2.4 / 0.4

1.4

Unit

V

ns

V

pF

Note

tR / tF

Voutref

CL

1

1.4

50

1

Note 1.

Vtt = 1.4V

Ω

RT = 500Ω

RT = 50

Output

50pF

Z0 = 50

Ω

50pF

DC Output Load Circuit

AC Output Load Circuit

Rev. 1.1 / Jan. 2005

7

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

o

CAPACITANCE (TA= 0 to 70 C, f=1MHz, VDD=3.3V)

Parameter

Symbol

Min

Max

Unit

CLK

CI1

2.0

4.0

pF

Input capacitance

A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,

WE, LDQM, UDQM

CI2

2.5

3.0

5.0

5.5

pF

Data input / output capacitance

DQ0 ~ DQ15

CI/O

o

DC CHARACTERISTICS I (TA= 0 to 70 C)

Parameter

Symbol

Min

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

ILO

-1

2.4

-

1

uA

V

1

2

VOH

VOL

-

IOH = -2mA

IOL = +2mA

0.4

V

Note:

1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 3.6

Rev. 1.1 / Jan. 2005

8

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

o

DC CHARACTERISTICS II (TA= 0 to 70 C)

Speed

Sym-

bol

Parameter

Test Condition

Unit Note

5

6

7

H

Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA

Operating Current

IDD1

120 110 100 100 mA

1

IDD2P

CKE ≤ VIL(max), tCK = 15ns

2

mA

Precharge Standby Current

in Power Down Mode

IDD2PS CKE ≤ VIL(max), tCK = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

IDD2N

Input signals are changed one time dur-

ing 2clks.

18

Precharge Standby Current

in Non Power Down Mode

mA

All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD2NS

IDD3P

15

CKE ≤ VIL(max), tCK = 15ns

3

Active Standby Current

in Power Down Mode

IDD3PS CKE ≤ VIL(max), tCK = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

IDD3N

Input signals are changed one time dur-

ing 2clks.

All other pins ≥ VDD-0.2V or ≤ 0.2V

40

35

Active Standby Current

in Non Power Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD3NS

Burst Mode Operating Cur-

rent

tCK ≥ tCK(min), IOL=0mA

All banks active

IDD4

IDD5

120 110 100 100 mA

210 200 190 190 mA

1

2

Auto Refresh Current

tRC ≥ tRC(min), All banks active

Normal

2

mA

uA

Self Refresh Current

IDD6

CKE ≤ 0.2V

3

Low power

800

Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. HY57V281620ET(P) Series: Normal Power

HY57V281620ELT(P) Series: Low Power

Rev. 1.1 / Jan. 2005

9

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

5

6

7

H

Sym-

bol

Parameter

Unit Note

Min Max Min Max Min Max Min Max

CAS

Latency=3

tCK3

5.0

10

6.0

10

7.0

10

7.5

10

ns

System Clock

Cycle Time

1000

CAS

Latency=2

tCK2

Clock High Pulse Width

Clock Low Pulse Width

tCHW

tCLW

1.75

-

2.0

-

2.0

-

2.5

-

ns

1

CAS

Latency=3

tAC3

tAC2

-

4.5

6.0

-

5.4

6.0

-

5.4

6.0

-

5.4

6.0

ns

Access Time

From Clock

2

CAS

Latency=2

Data-out Hold Time

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

CKE Setup Time

tOH

tDS

2.0

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.0

-

2.0

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.0

-

2.5

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.5

-

2.5

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.5

-

ns

1

tDH

tAS

tAH

tCKS

tCKH

tCS

CKE Hold Time

Command Setup Time

Command Hold Time

tCH

tOLZ

CLK to Data Output in Low-Z Time

CAS

Latency=3

tOHZ3

tOHZ2

-

4.5

6.0

-

5.4

6.0

-

5.4

6.0

-

5.4

6.0

ns

CLK to

Data Output

in High-Z Time

CAS

Latency=2

Note:

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,

then (tR/2-0.5)ns should be added to the parameter.

Rev. 1.1 / Jan. 2005

10

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

5

6

7

H

Parameter

Symbol

Unit Note

Min Max Min Max Min Max Min Max

RAS Cycle Time

Operation

tRC

55

15

-

60

18

-

63

20

-

63

20

-

ns

RAS Cycle Time

Auto Refresh

tRRC

tRCD

tRAS

tRP

RAS to CAS Delay

RAS Active Time

RAS Precharge Time

38.7 100K 42 100K 42 100K 42 120K ns

15

10

1

-

18

12

1

-

20

14

1

-

20

15

1

-

ns

RAS to RAS Bank Active Delay

CAS to CAS Delay

tRRD

tCCD

CLK

Write Command to

Data-In Delay

tWTL

0

2

-

0

2

-

0

2

-

0

2

-

CLK

Data-in to Precharge Command

Data-In to Active Command

DQM to Data-Out Hi-Z

tDPL

tDAL

tDQZ

tDQM

tMRD

tDPL + tRP

2

0

2

-

2

0

2

-

2

0

2

-

2

0

2

-

CLK

DQM to Data-In Mask

MRS to New Command

Precharge to Data CAS

tPROZ3

tPROZ2

3

2

-

3

2

-

3

2

-

3

2

-

CLK

Output High-Z

Latency=3

CAS

Latency=2

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

tDPE

tSRE

tREF

1

-

1

-

1

-

1

-

CLK

1

64

-

64

64 ms

Note: 1. A new command can be given tRRC after self refresh exit.

Rev. 1.1 / Jan. 2005

11

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

COMMAND TRUTH TABLE

Command

CKEn-1

CKEn

CS

L

RAS

CAS

L

WE

L

DQM

ADDR

A10/AP

BA

Note

Mode Register Set

H

X

L

X

H

L

X

OP code

H

L

X

No Operation

X

H

Bank Active

L

H

RA

V

Read

L

H

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

H

L

X

V

X

L

H

L

H

X

V

X

DQM

X

Auto Refresh

H

X

L

H

L

X

A9 ball High

MRS

Mode

Burst-Read-Single-WRITE

Entry

H

L

X

(Other balls OP code)

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

Self Refresh¹

Exit

X

L

H

L

H

L

X

H

L

Entry

Precharge

power down

X

H

L

Exit

H

L

Entry

Clock

Suspend

H

L

X

Exit

H

X

Rev. 1.1 / Jan. 2005

12

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package

UNIT : mm(inch)

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0.150(0.0059)

0.050(0.0020)

1.194(0.0470)

0.991(0.0390)

5deg

0deg

0.210(0.0083)

0.120(0.0047)

0.597(0.0235)

0.406(0.0160)

0.400(0.016)

0.80(0.0315)BSC

0.300(0.012)

Rev. 1.1 / Jan. 2005

13


型号：	HY57V281620ET-5
厂家：	HYNIX SEMICONDUCTOR
描述：	128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O 128Mb的同步DRAM的基础上2米x 4Bank x16的I / O 动态存储器
文件：	总13页 (文件大小：127K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY57V281620ET-5 [HYNIX]

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