HY57V561620FLTP-6_技术文档

256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

256M (16Mx16bit) Hynix SDRAM

Memory

Memory Cell Array

- Organized as 4banks of 4,194,304 x 16

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

Document Title

256Mbit (16M x16) Synchronous DRAM

Revision History

Revision No.

History

Draft Date

Remark

0.1

Initial Draft

Dec. 2005

Apr. 2006

Preliminary

Define :

Current value (Page 11 ~ 12)

0.2

Preliminary

1. Cerrect :

1-1. 4Banks x 2Mbits x32 --> 4Banks x 4Mbits x16(Ordering in-

formation; Page 06).

1-2. VDDQ / VSSQ : Power supply for output buffers (Page 08).

2. Remove :

Special Power consumption function of Auto TCSR(Temperature

Compensated Self Refresh) and PASR(Partial Array Self Refresh).

3. Define :

AC Operating TEST condition and AC / DC Output Load circuit

(page 10 & 11).

0.3

Jun. 2006

Preliminary

Before :

Vtt=1.4V

RT=500

Ω

RT=50

Ω

Output

Z0

= 50Ω

Output

30pF

DC Output Load Circuit

AC Output Load Circuit

Rev 1.3 / Dec. 2009

2

Revision No.

History

Draft Date

Remark

After :

VTT =

1.4V

RT = 50

Ohom

RT = 50

Ohom

Output

Z0 = 50 Ohom

50pF

DC Output Load Circuit

AC Output Load Circuit

0.3

Jun. 2006

Preliminary

4. Specification change :

4-1. IOH / IOL (Page 11)

Before : -2 / 2mA --> After : -4 / 4mA.

4-2. tDH, tAH, tCKH, tCH (Page 13)

Before : 1.0ns --> After : 0.8ns.

1. Delete

1-1. COMMAND TRUTH TABLE for Extended Mode Register

(Page15)

2. Insert

2-1. DQM TRUTH TABLE (Page16)

0.4

Jun. 2006

Preliminary

3. Specitication change :

3-1. IDD6

Before : 3 / 1.5mA --> After : 2 / 1mA

3-2. IDD3N

Before :25mA --> After : 30mA

3-3. tCHW / tCLW Change [HY57V561620F(L)T(P)-6x]

Before :2.0ns --> After : 2.5ns

1.0

1.1

Final Ver.

Sep. 2006

Apr. 2008

Final

1. Update

1-1. Ordering Information table (Page 5)

200Mhz products added

1-2. DC Characteristics II (Page 11)

200Mhz spec. added

1-3. AC Characteristics I (Page 12)

200Mhz spec. added

1-4 AC Characteristics II (Page 13)

200Mhz spec. added

2. Cerrect

HY57V561620FT-6 --> HY57V561620FLT-6

(Ordering Information. Page 5)

Revise (Command Truth Table / P.15)

Burst Read Single Write : /WE H --> L

1.2

1.3

Final

Dec. 2009

Revise (P.12)

Symbol “-6” tCK2 (CL2) : 7.5 --> 10ns

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

DESCRIPTION

The Hynix Synchronous DRAM is suited for advaced-consumer application which use the batteries such as Image dis-

player application (Digital still camera etc.) and portable applications (portable multimedia player and portable audio

player). Also, Hynix SDRAMs is used high-speed consumer applications. Short for Hynix Synchronous DRAM, a type of

DRAM that can run at much higher clock speeds memory.

The Hynix HY57V561620F(L)T(P) Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for

the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks

of 4,194,304 x 16 I/O.

Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous

DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization

with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16

Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4,

8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is

initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the

column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one

bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed,

randon-access operation.

Read and write accesses to the Hynix Synchronous DRAM are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access.

All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal).

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

256Mb Synchronous DRAM(16M x 16) FEATURES

●

Standard SDRAM Protocol

Internal 4bank operation

Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V

All device pins are compatible with LVTTL interface

Low Voltage interface to reduce I/O power

8,192 Refresh cycles / 64ms

Programmable CAS latency of 2 or 3

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

●

0^oC ~ 70^oC Operation

Package Type : 54_Pin TSOPII (Lead Free, Lead)

HY57V561620F(L)TP Series : Lead Free

HY57V561620F(L)T Series : Leaded

ORDERING INFORMATION

Clock

Frequency Latency

CAS

54Pin

Voltage Organization Interface

TSOP

Part Number

Power

HY57V561620FT-6

HY57V561620FT-H

HY57V561620FT-5

HY57V561620FLT-6

HY57V561620FLT-H

HY57V561620FLT-5

HY57V561620FTP-6

HY57V561620FTP-H

HY57V561620FTP-5

HY57V561620FLTP-6

HY57V561620FLTP-H

HY57V561620FLTP-5

166MHz

133MHz

200MHz

166MHz

133MHz

200MHz

166MHz

133MHz

200MHz

166MHz

133MHz

200MHz

3

Normal

Leaded

Low

Power

4Banks x 4Mbits

3.3V

LVTTL

x16

Normal

Lead

Free

Low

Power

Note:

1. HY57V561620FT(P) Series: Normal power

2. HY57V561620FLT(P) Series: Low Power

3. HY57V561620F(L)T Series: Leaded 54Pin TSOPII

4. HY57V561620F(L)TP Series: Lead Free 54Pin

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

54 TSOP II Pin ASSIGNMENTS

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

/WE

/CAS

/RAS

/CS

VSS

2

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54 Pin TSOPII

400mil x 875mil

0.8mm pin pitch

NC

UDQM

CLK

CKE

A12

BA0

A11

BA1

A9

A10/AP

A0

A8

A7

A1

A6

A2

A5

A3

A4

VDD

VSS

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

54_TSOPII Pin DESCRIPTIONS

SYMBOL

TYPE

DESCRIPTION

Clock :

CLK

INPUT

The system clock input. All other inputs are registered to the SDRAM on the rising edge

of CLK

Clock Enable:

CKE

CS

INPUT

Controls internal clock signal and when deactivated, the SDRAM will be one of the states

among power down, suspend or self refresh

Chip Select:

Enables or disables all inputs except CLK, CKE and DQM

Bank Address:

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

A0 ~ A12

RAS, CAS, WE

Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8

Auto-precharge flag: A10

Command Inputs:

RAS, CAS and WE define the operation

Refer function truth table for details

Data Mask:

LDQM, UDQM

DQ0 ~ DQ15

I/O

Controls output buffers in read mode and masks input data in write mode

Data Input / Output:

Multiplexed data input / output pin

VDD / VSS

VDDQ / VSSQ

NC

SUPPLY Power supply for internal circuits and input buffers

SUPPLY Power supply for output buffers

-

No connection : These pads should be left unconnected

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

FUNCTIONAL BLOCK DIAGRAM

4Mbit x 4banks x 16 I/O Synchronous DRAM

Self refresh

logic & timer

Internal Row

Counter

4M x16 Bank3

4M x16 Bank2

4M x16 Bank1

4M x16 Bank0

CLK

CKE

CS

Row

Pre

Decoder

Row Active

DQ0

RAS

Refresh

Memory

Cell

CAS

WE

Array

Column

Active

Column

Pre

Decoder

LDQM,

UDQM

DQ15

Y decoerders

Column Add

Counter

Bank Select

Address

Register

A0

A1

Burst

Counter

Pipe Line

Control

A12

BA1

BA0

CAS Latency

Mode Register

Data Out Control

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

ABSOLUTE MAXIMUM RATING

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

0 ~ 70

^oC

V

Storage Temperature

TSTG

VIN, VOUT

VDD, VDDQ

IOS

-55 ~ 125

-1.0 ~ 4.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD supply relative to VSS

Short Circuit Output Current

Power Dissipation

V

mA

W

PD

1

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

Max

3.6

Unit

Note

1

V

2.0

VDDQ + 0.3

0.8

1, 2

1, 3

VIL

-0.3

Note: 1. All voltages are referenced to VSS = 0V.

2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with <= 3ns of duration.

3. VIL(min) is acceptable -2.0V for a pulse width with <= 3ns of duration.

o

AC OPERATING TEST CONDITION (TA= 0 to 70 C, VDD=3.3±0.3V / VSS=0V)

Parameter

Symbol

VIH / VIL

Vtrip

Value

2.4 / 0.4

1.4

Unit

V

Note

AC Input High / Low Level Voltage

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

V

tR / tF

Voutref

CL

1

ns

V

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

1.4

50

pF

1

Note: 1. See Next Page

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

VTT =

1.4V

VTT =

1.4V

RT = 50

Ohom

RT = 50

Ohom

Output

Z0 = 50 Ohom

50pF

DC Output Load Circuit

AC Output Load Circuit

CAPACITANCE (f=1MHz)

Parameter

Symbol

Min

Max

Unit

CLK

CI1

CI2

CI3

2.0

4.0

pF

Input capacitance

A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE

LDQM, UDQM

Data input / output

capacitance

DQ0 ~ DQ15

CI/O

3.5

6.5

pF

o

DC CHARACTERRISTICS I (TA= 0 to 70 C)

Parameter

Input Leakage Current

Symbol

Min

Max

Unit

Note

ILI

ILO

-1

2.4

-

1

uA

V

1

2

Output Leakage Current

Output High Voltage

Output Low Voltage

VOH

VOL

-

IOH = -4mA

IOL = +4mA

0.4

V

Note:

1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 3.6

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

o

DC CHARACTERISTICS II (TA= 0 to 70 C)

Speed

Parameter

Symbol

Test Condition

Unit

Note

5

6

H

Operating

Current

Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA

IDD1

110

100

1.0

90

mA

1

Precharge

Standby

Current

in Power Down

Mode

IDD2P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK = ∞

IDD2PS

IDD2N

1.0

15

mA

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

Precharge

Standby

Current

mA

in Non Power

Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD2NS

IDD3P

8

3

Active Standby

Current in

Power Down

Mode

CKE ≤ VIL(max), tCK = 15ns

mA

IDD3PS

CKE ≤ VIL(max), tCK = ∞

3

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

2clks.

Active Standby

Current in Non

Power Down

Mode

IDD3N

30

All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD3NS

IDD4

20

Burst Mode Op-

erating Current

tCK ≥ tCK(min), IOL=0mA

All banks active

110

190

100

180

90

mA

1

2

Auto Refresh

Current

IDD5

tRC ≥ tRC(min), All banks active

170

Normal

2.0

1.0

Self Refresh

Current

IDD6

CKE ≤ 0.2V

mA

3

Low Power

Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. HY57V561620FT(P) Series: Normal, HY57V561620FLT(P) Series: Low Power

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

5

6

H

Parameter

Symbol

CL = 3 tCK3

Unit

Note

Min

5.0

10

2.0

-

Max

Min

6.0

10

Max

Min

7.5

10

Max

1000

ns

System Clock Cycle Time

1000

CL = 2 tCK2

1000

Clock High Pulse Width

Clock Low Pulse Width

tCHW

-

2.5

-

2.5

-

1

2

tCLW

-

CL = 3 tAC3

4.5

5.4

6

-

Access Time From Clock

CL = 2 tAC2

-

6.0

-

6

-

Data-out Hold Time

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

CKE Setup Time

tOH

tDS

tDH

tAS

2.0

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.0

-

2.0

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.0

2.7

-

2.5

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.0

2.7

3

-

1

-

tAH

tCKS

tCKH

tCS

-

CKE Hold Time

-

Command Setup Time

Command Hold Time

-

tCH

-

CLK to Data Output in Low-Z Time

tOLZ

-

CL = 3 tOHZ3

CL = 2 tOHZ2

4.5

6.0

5.4

6

CLK to Data Output in

High-Z Time

-

Note:

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added

to the parameter.

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

5

6

H

Parameter

Symbol

Unit

Note

Min

55

15

38.7

15

10

1

Max

Min

60

18

42

18

12

1

Max

Min

63

20

42

20

15

1

Max

Operation

Auto Refresh

tRC

-

ns

RAS Cycle Time

tRRC

tRCD

tRAS

tRP

-

RAS to CAS Delay

RAS Active Time

-

ns

100K

ns

RAS Precharge Time

-

ns

RAS to RAS Bank Active Delay

CAS to CAS Delay

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

tPROZ3

tPROZ2

tDPE

tSRE

tREF

ns

CLK

Write Command to Data-In Delay

Data-in to Precharge Command

Data-In to Active Command

DQM to Data-Out Hi-Z

0

2

tDPL + tRP

2

0

2

3

2

1

-

2

0

2

3

2

1

-

2

0

2

3

2

1

-

CLK

ms

DQM to Data-In Mask

MRS to New Command

-

CL = 3

-

Precharge to Data

Output High-Z

CL = 2

-

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

-

1

64

Note: 1. A new command can be given tRC after self refresh exit.

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

BASIC FUNCTIONAL DESCRIPTION

Mode Register

BA1

0

BA0

0

A12

0

A11

0

A10

0

A9

A8

0

A7

0

A6

A5

A4

A3

BT

A2

A1

A0

OP Code

CAS Latency

Burst Length

OP Code

Burst Type

A9

0

Write Mode

A3

0

Burst Type

Sequential

Interleave

Burst Read and Burst Write

Burst Read and Single Write

1

CAS Latency

Burst Length

A6

0

A5

0

A4

0

CAS Latency

R e s e r v e d

2

Burst Length

A2

A1

A0

A3 = 0

A3=1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

2

0

1

0

1

3

4

1

0

Reserved

R e s e r v e d

Reserved

8

1

0

1

Reserved

Full page

Reserved

1

0

1

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

COMMAND TRUTH TABLE

A10

/AP

Function

CKEn-1

CKEn

CS

RAS CAS WE DQM ADDR

BA Note

Mode Register Set

No Operation

H

X

L

H

X

L

H

X

H

L

H

X

H

X

Op Code

X

Device Deselect

Bank Active

H

L

Row Address

V

Col-

L

Read

H

X

L

H

L

H

L

umn

Col-

H

Read with Autoprecharge

Write

X

V

umn

Col-

L

umn

Col-

H

Write with Autoprecharge

L

umn

Precharge All Banks

Precharge selected Bank

Burst stop

H

X

H

L

H

L

X

V

X

H

L

X

V

H

X

DQM

X

2

Auto Refresh

L

H

L

X

A9 Pin High

Burst-Read Single-Write

Self Refresh Entry

H

X

L

X

(Other Pins OP code)

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

X

Self Refresh Exit

L

H

L

H

L

X

1

H

L

Precharge Power Down

Entry

H

L

Precharge Power Down Exit

H

L

Clock Suspend Entry

Clock Suspend Exit

H

L

X

H

X

Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.

2. see to Next page (DQM TRUTH TABLE)

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

DQM TRUTH TABLE

Function

CKEn-1

CKEn

LDQM

UDQM

Data Write/Output enable

Data Mask/Output disable

H

X

L

H

Lower byte write/Output enable,

Upper byte mask/Output disable

H

X

L

H

L

Lower byte Mask/Output disable,

Upper byte write/Output enable

H

Note 1. H: High Level, L: Low Level, X: Don't Care

2. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CURRENT STATE TRUTH TABLE (Sheet 1 of 4)

Command

Current

Action

Notes

BA0/

BA1

State

CS RAS CAS WE

Amax-A0

Description

L

H

L

OP CODE

Mode Register Set

Set the Mode Register

X

Auto or Self Refresh Start Auto or Self Refresh

5

H

BA

Precharge

No Operation

Activate the specified

bank and row

L

H

L

H

L

BA

Row Add.

Bank Activate

Col Add.

A10

idle

H

Write/WriteAP

ILLEGAL

4

Col Add.

A10

L

H

X

L

H

X

H

X

BA

X

Read/ReadAP

ILLEGAL

4

3

X

No Operation

No Operation or Power

Down

H

X

Device Deselect

Mode Register Set

L

H

L

OP CODE

ILLEGAL

13

7

X

Auto or Self Refresh ILLEGAL

H

BA

Precharge

ILLEGAL

H

Row Add.

Bank Activate

4

Row

Active

Col Add.

A10

Start Write : optional

AP(A10=H)

L

H

L

BA

Write/WriteAP

Read/ReadAP

6

Col Add.

A10

Start Read : optional

AP(A10=H)

H

L

H

L

H

X

L

H

X

L

H

X

L

X

No Operation

ILLEGAL

Device Deselect

Mode Register Set

OP CODE

13

L

H

X

Auto or Self Refresh ILLEGAL

Termination Burst: Start

the Precharge

L

H

L

H

L

BA

Precharge

Row Add.

Bank Activate

Write/WriteAP

ILLEGAL

4

Read

Col Add.

A10

Termination Burst: Start

Write(optional AP)

H

8,9

Col Add.

A10

Termination Burst: Start

Read(optional AP)

L

H

L

H

BA

X

Read/ReadAP

No Operation

8

H

X

Continue the Burst

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CURRENT STATE TRUTH TABLE (Sheet 2 of 4)

Command

Current

Action

Notes

BA0/

BA1

State

CS RAS CAS WE

Amax-A0

Description

Read

H

L

X

L

X

L

X

L

X

Device Deselect

Continue the Burst

ILLEGAL

OP CODE

Mode Register Set

13

L

H

X

Auto or Self Refresh ILLEGAL

Termination Burst: Start

the Precharge

L

H

L

H

L

BA

Precharge

10

4

Row Add.

Bank Activate

Write/WriteAP

ILLEGAL

Write

Col Add.

A10

Termination Burst: Start

Write(optional AP)

H

8

Col Add.

A10

Termination Burst: Start

Read(optional AP)

L

H

L

H

BA

Read/ReadAP

8,9

L

H

L

H

L

H

X

L

H

X

L

H

X

L

X

No Operation

Continue the Burst

ILLEGAL

Device Deselect

Mode Register Set

OP CODE

13

L

H

L

X

BA

X

Auto or Self Refresh ILLEGAL

L

H

L

Precharge

ILLEGAL

4,12

12

Read with

Auto

Precharge

L

H

L

Row Add.

Bank Activate

ILLEGAL

H

X

L

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

ILLEGAL

L

H

X

L

ILLEGAL

12

H

X

L

X

No Operation

Continue the Burst

ILLEGAL

X

Device Deselect

Mode Register Set

OP CODE

13

L

H

L

X

BA

X

Auto or Self Refresh ILLEGAL

L

H

L

Precharge

ILLEGAL

4,12

12

Write with

Auto

Precharge

L

H

L

Row Add.

Bank Activate

ILLEGAL

H

X

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

ILLEGAL

L

H

X

ILLEGAL

12

H

X

No Operation

Continue the Burst

X

Device Deselect

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CURRENT STATE TRUTH TABLE (Sheet 3 of 4)

Command

Current

Action

Notes

BA0/

BA1

State

CS RAS CAS WE

Amax-A0

Description

L

OP CODE

Mode Register Set

ILLEGAL

13

H

X

Auto or Self Refresh ILLEGAL

No Operation:

Bank(s) idle after tRP

L

H

L

BA

Precharge

L

H

L

H

L

BA

Row Add.

Bank Activate

ILLEGAL

4,12

Precharging

H

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

ILLEGAL

L

H

ILLEGAL

No Operation:

Bank(s) idle after tRP

L

H

X

H

X

H

X

No Operation

No Operation:

Bank(s) idle after tRP

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13

X

Auto or Self Refresh ILLEGAL

H

BA

Precharge

ILLEGAL

4,12

4,11,1

2

L

H

BA

Row Add.

Bank Activate

Row

Activating

L

H

L

BA

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

ILLEGAL

4,12

H

No Operation: Row

Active after tRCD

L

H

X

H

X

H

X

No Operation

No Operation: Row

Active after tRCD

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13

X

Auto or Self Refresh ILLEGAL

H

BA

Precharge

ILLEGAL

4,13

4,12

H

Row Add.

Bank Activate

Write

Recovering

Start Write:

Optional AP(A10=H)

L

H

L

BA

X

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

Start Read: Optional

AP(A10=H)

H

9

No Operation:

Row Active after tDPL

H

X

No Operation

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CURRENT STATE TRUTH TABLE (Sheet 4 of 4)

Command

Current

Action

Notes

BA0/

BA1

State

CS RAS CAS WE

Amax-A0

Description

Write

Recovering

No Operation:

Row Active after tDPL

H

X

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13

X

Auto or Self Refresh ILLEGAL

L

H

L

BA

Precharge

ILLEGAL

4,13

4,12

4,9,12

Write

L

H

L

Row Add.

Bank Activate

Recovering

with Auto

Precharge

H

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

L

H

No Operation:

Precharge after tDPL

L

H

X

H

X

H

X

No Operation

No Operation:

Precharge after tDPL

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13

X

Auto or Self Refresh ILLEGAL

L

H

L

BA

Precharge

ILLEGAL

L

H

L

Row Add.

Bank Activate

H

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

Refreshing

L

H

No Operation:

idle after tRC

L

H

X

H

X

H

X

No Operation

No Operation:

idle after tRC

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13

X

Auto or Self Refresh ILLEGAL

L

H

L

BA

Precharge

ILLEGAL

L

H

L

Row Add.

Bank Activate

Mode

Register

Accessing

H

Col Add. A10 Write/WriteAP

Col Add. A10 Read/ReadAP

L

H

No Operation:

idle after 2 clock cycles

L

H

X

H

X

H

X

No Operation

No Operation:

idle after 2 clock cycles

H

Device Deselect

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

Note :

1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.

2. All entries assume that CKE was active during the preceding clock cycle.

3. If both banks are idle and CKE is inactive, then in power down cycle

4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,

depending on the state of that bank.

5. If both banks are idle and CKE is inactive, then Self Refresh mode.

6. Illegal if tRCD is not satisfied.

7. Illegal if tRAS is not satisfied.

8. Must satisfy burst interrupt condition.

9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

10. Must mask preceding data which don't satisfy tDPL.

11. Illegal if tRRD is not satisfied

12. Illegal for single bank, but legal for other banks in multi-bank devices.

13. Illegal for all banks.

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CKE Enable(CKE) Truth TABLE (Sheet 2 of 1)

CKE

Command

Current

State

Action

Notes

Previous Current

BA0,

BA1

CS RAS CAS WE

ADDR

Cycle

H

X

INVALID

1

2

Exit Self Refresh with

Device Deselect

L

H

Exit Self Refresh with

No Operation

L

H

X

2

Self

Refresh

L

H

L

H

L

H

L

X

H

X

L

X

ILLEGAL

2

ILLEGAL

L

X

H

X

L

ILLEGAL

L

X

H

L

X

H

L

Maintain Self Refresh

INVALID

H

X

1

2

Power Down mode exit,

all banks idle

L

H

Power

Down

L

H

L

X

H

L

ILLEGAL

2

X

H

L

H

L

X

H

L

H

L

X

H

L

Maintain Power Down Mode

H

L

3

Refer to the idle State section

of the Current State

Truth Table

L

X

Auto Refresh

L

OP CODE

Mode Register Set

4

3

4

All

Banks

Idle

X

H

L

X

H

L

X

H

L

Refer to the idle State section

of the Current State

Truth Table

L

X

Entry Self Refresh

Mode Register Set

Power Down

L

OP CODE

X

4

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)

CKE

Command

Current

State

Action

Notes

Previous Current

BA0,

BA1

CS RAS CAS WE

ADDR

Cycle

Refer to operations of

the Current State

Truth Table

H

X

Any State

other than

listed above

Begin Clock Suspend

next cycle

H

L

Exit Clock Suspend

next cycle

L

H

L

X

Maintain Clock Suspend

Note :

1. For the given current state CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,

a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.

3. The address inputs depend on the command that is issued.

4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered

from the all banks idle state.

5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.

When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of

clock after CKE goes high and is maintained for a minimum 200usec.

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

Mobile SDR SDRAM OPERATION

State Diagram

Power

On

ACT :

Active

Precharge

All

Bank

Auto

Refresh

MRS :

Mode Register Set

PRE :

Precharge

MRS

REFS

REFX

PREALL :

Precharge All Banks

Self

Refresh

Mode Register

Set

IDLE

REFA :

Auto Refresh

REFS :

Enter Self Refresh

Power

Down

REFSX :

Exit Self Refresh

WRITEA

READ :

READA

SUSPEND

Active

Power

Down

SUSPEND

Read w/o Auto

Precharge

READ

with AP

WRITE

with AP

READA :

Read with Auto

Precharge

WRITE :

Write w/o Auto

Precharge

Read

Write

Read

Write

ROW

ACTIVE

READ

WRITE

WRITEA :

Write with Auto

Precharge

WRITE

SUSPEND

READ

SUSPEND

Automatic Sequence

Manual input

Precharge

All

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

DESELECT

The DESELECT function (CS = High) prevents new commands from being executed by the SDRAM, the SDRAM ignore

command input at the clock. However, the internal status is held. The Synchronous DRAM is effectively deselected.

Operations already in progress are not affected.

NO OPERATION

The NO OPERATION (NOP) command is used to perform a NOP to a SDRAM that is selected (CS = Low, RAS = CAS =

WE = High). This command is not an execution command. However, the internal operations continue. This prevents

unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

(see to next figure)

ACTIVE

The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of

the BA0,BA1 inputs selects the bank, and the address provided on A0-A12(or the highest address bit) selects the row.

This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. (see to next fig-

ure)

CLK

CKE

CLK

CKE

High-Z

CS

RAS

CAS

WE

CAS

WE

A0~A9,

A11, A12

A0~A9,

A11, A12

RA

BA

Row Address

Bank Address

BA0,1

Don't Care

ACTIVATING A SPECIFIC

ROW IN A SPECIFIC BANK

NOP command

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

READ / WRITE COMMAND

Before executing a read or write operation, the corresponding bank and the row address must be activated by the

bank active (ACT) command. An interval of tRCD is required between the bank active command input and the follow-

ing read/write command input.

The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and

address inputs select the starting column location.

The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being

accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open

for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.

The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank

and address inputs select the starting column location.

The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being

accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open

for subsequent access.

/CLK

CLK

CKE

CLK

CKE

High-Z

CS

RAS

CAS

W E

CAS

W E

Enable

Auto

Precharge

CA

BA

CA

BA

A0 ~ A8

Disable

Auto

Precharge

A10

BA0,1

Read Com m and

Operation

W rite Com m and

Operation

Don't Care

READ / WRITE COMMAND

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

READ

A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)

cycle after read command set. The SDRAM can perform a burst read operation.

The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and

the bank select address at the read command set cycle. In a read operation, data output starts after the number of

clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.

When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the suc-

cessive burst-length data has been output.

The /CAS latency and burst length must be specified at the mode register.

tCK

CLK

REA

D

Command

DQ

NOP

tOH

Do0

tLZ

Do1

Do2

Do3

tAC

CL = 2

REA

D

NOP

tOH

Do0

Command

tLZ

Do1

Do2

Do3

DQ

tAC

Undefined

Don't Care

CL = 3

Read Burst Showing CAS Latency

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

tCK

CLK

N

OP

N

OP

RE

AD

CMD

tOH

tLZ

BL=1

Do

0

DQ

BL=2

Do

0

Do

0

Do

0

Do

1

Do

1

Do

1

DQ

BL4

Do

2

Do

2

Do

3

Do

3

BL=8

Do

4

Do

5

Do

6

Do

7

CL = 2

Undefined

Don't Care

Read Burst Showing BL

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

READ to READ

Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the

new burst follows either the last element of a completed burst or the last desired element of a longer burst that is

being truncated.

When another read command is executed at the same ROW address of the same bank as the preceding read com-

mand execution, the second read can be performed after an interval of no less than 1 clock. Even when the first com-

mand is a burst read that is not yet finished, the data read by the second command will be valid.

CLK

Command

Address

NOP

READ’

READ

NOP

BA, Col

a

BA, Col

b

CL =2

DQ

Doa0

Doa1

Doa0

Dob0

Doa1

Dob1

Dob0

CL =3

Don't Care

Consecutive Read Bursts

A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are

shown in Figure. Full-speed random read accesses within a page or pages can be performed as shown in Fig.

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CLK

Command

READ

BA, Col

n

BA, Col

b

Address

DQ

CL =2

CL =3

Dob

Don

Dob

Don

DQ

Don't Care

1) Don (or b): Data out from column n

2) BA, Col n (b) = Bank A, Column n (b)

3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following Do n (b)

Non-Consective Read Bursts

CLK

Command

READ

BA, Col

g

BA, Col

n

BA, Col

x

BA, Col

b

Address

DQ

CL =2

CL =3

Dog'

Dog

Dox

Dox'

Dox

Dob

Dox'

Don

Don'

Don

Dob'

Dob

Dog

Dob'

Dog’

Don'

DQ

1) Don, etc: Data out from column n, etc

n', x', etc : Data Out elements, accoding to the programmd burst order

2) BA, Col n = Bank A, Column n

Don't Care

3) Burst Length = 1, 2, 4, 8 or full page in cases shown

4) Read are to active row in any banks

Randum Read Bursts

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

READ BURST TERMINATE

Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is

equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ com-

mand where X equals the desired data-out element.

CLK

Command

Address

READ

BURST

BA, Col

n

CL =2

CL =3

DQ

Don

Don'

Don

Don'

1) Don : Data out from column n

2) BA, Col n = Bank A, Column n

Don't Care

3) Cases shown are bursts of 4, 8, or full page terminated after 2 data elements

Terminating a Read Burst

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

READ to WRITE

Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If trun-

cation is necessary, the BURST TERMINATE command must be used, as shown in next fig.

CLK

Command

Address

READ

BURST

WRITE

BA, Col

n

BA, Col

b

CL =2

CL =3

DQ

Don

Don'

Don

DIb0

DIb3

DIb1

DIb2

Don'

Don't Care

1) DO n = Data Out from column n; DI b = Data In to column b

Read to Write

Note :

1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preced-

ing read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High

so that the output buffer becomes High-Z before data input.

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is nec-

essary to separate the two commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided

that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data

input.

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

READ to PRECHARGE

Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.

Note that part of the row precharge time is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time

(as described above) provides the same operation that would result from the same fixed-length burst with auto pre-

charge.

The disadvantage of the PRECHARGEcommand is that it requires that the command and address buses be available at

the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to trun-

cate fixed-length or full-page bursts.

CLK

Command

Address

READ

PRE

ACT

tRP

Bank

A, All

BA, Col

n

BA,

Row

CL =2

CL =3

DQ

Don

Don't Care

1) DO n = Data Out from column n

2) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks.

3) The ACTIVE command may be applied if tRC has been met.

READ to PRECHARGE

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

Write

Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing

coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;

if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to

that byte / column location.

During WRITE bursts, the first valild data-in element will be registered coincident with the WRITE command. Subse-

quent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length

burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will

be ignored. A full-page burst will continue until terminated.

Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE

burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any

clock following the previous WRITE command, and the data provided coincident with the new command applies to the

new command.

CLK

Command

Address

WRITE

BA, Col

b

DQ

BL = 1

BL = 2

BL = 4

BL = 8

DIb0

DIb1

DQ

DIb1

DIb0

DIb2

DIb3

DIb4

DIb5

DIb6

DIb7

Don't Care

CL = 2 or 3

Basic Write timing parameters for Write Burst Operation

Note :

1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the

preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes,

the second write command has priority.

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is nec-

essary to separate the two write commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that

the other bank is in the bank active state. In the case of burst write, the second write command has priority.

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Synchronous DRAM Memory 256Mbit

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WRITE to WRITE

Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case,

a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of

the clock following the previous WRITE command. The first data-in element from the new burst is applied after either

the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The

new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of

desired data-in element.

CLK

Command

WRITE

BA, Col

b

BA, Col

n

Address

DQ

DIb1

DIn0

DIb0

DIn1

DIb2 DIb3

DIn2 DIn3

DM

CL = 2 or 3

Don't Care

Concatenated Write Bursts

CLK

Command

WRITE

NOP

BA, Col

b

BA, Col

x

BA, Col

n

BA, Col

a

BA, Col

g

Address

DQ

DIb'

DIn

DIb

DIn’

DIx

DIa

DIg

DIx’

DIa’

DIg’

DM

Don't Care

CL = 2 or 3

Random Write Cycles

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

WRITE to READ

CLK

Command

WRITE

READ

BA, Col

b

BA, Col

n

Address

CL = 2

CL = 3

BL = 4

DIb1

DOn0

DIb0

DOn1

DOn0

DOn2 DOn3

DQ

DOn1

DOn2

DOn3

Don't Care

The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new

read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency.

The preceding write operation (WRIT) writes only the data input before the read command.

The data bus must go into a high-impedance state at least one cycle before output of the latest data.

Note:

1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preced-

ing write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst

write, data will continue to be written until one clock before the read command is executed.

2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is nec-

essary to separate the two commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided

that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock

before the read command is executed (as in the case of the same bank and the same address).

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

WRITE to PRECHARGE

Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto

Precharge was not activated). When the precharge command is executed for the same bank as the write command

that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is

unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a

WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig.

CLK

Command

Address

WRITE

PRE

BA, Col

b

CL = 2 or 3

BL = 4

DIb0

DIb3

DIb1

DIOb2

DQ

tDPL

Non-Interrupting Write to Precharge

Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.

Note that only data-inthat are registered prior to the tDPL period are written to the internal array, and any subsequent

data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent com-

mand to the same bank cannot be issued until tRP is met.

CLK

Command

Address

WRITE

PRE

BA, Col

b

CL = 2 or 3

BL = 4

DIb0

DIb1

DIOb2

tDPL

DQ

Interrupting Write to Precharge

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

BURST TERMINATE

The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled). The most recently

registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation sec-

tion of this datasheet. Note the BURST TERMINATE command is not bank specific. This command should not be used

to terminate write bursts.

CLK

CKE

High-Z

CS

RAS

CAS

WE

A0 ~ A9

A11, A12

Don't Care

BA0, 1

BURST TERMINATE COMMAND

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.

Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is

completed.

If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged,

A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE

command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the

process of precharging.

CKE

High-Z

A10 defines the precharge

mode when a precharge

command, a read command

or a write command is

issued.

CS

RAS

If A10 = High when a

precharge command is

issued, all banks are

precharged.

CAS

WE

If A10 = Low when a

precharge command is

issued, only the bank that is

selected by BA1/BA0 is

precharged.

A0~A9

A11, A12

If A10 = High when read or

write command, auto-

precharge function is

enabled.

A10

While A10 = Low, auto-

precharge function is

disabled.

BA0,1

BA

Bank Address

Don't Care

PRECHARGE command

AUTO PRECHARGE

Auto Precharge is a feature which performs the same individual bank precharge function as described above, but with-

out requiring an explicit command.

This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write

command. This precharges the bank/row after the Read or Write burst is complete.

Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is

desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.

The user must not issue another command to the same bank until the precharge time (tRP) is completed.

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

AUTO REFRESH AND SELF REFRESH

Hynix SDR SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of

two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:

- AUTO REFRESH.

This command is used during normal operation of the Hynix SDR SDRAM. It is non persistent, so must be issued each

time a refresh is required. The refresh addressing is generated by the internal refresh controller.The Hynix SDR SDRAM

requires AUTO REFRESH commands at an average periodic interval of tREF.

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given SDR SDRAM, and the

maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*tREF.

-SELF REFRESH.

The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). This state retains

data in the SDR SDRAM, even if the rest of the system is powered down. Note refresh interval timing while in Self

Refresh mode is scheduled internally in the SDR SDRAM and may vary and may not meet tREF time.

After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh

operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh

exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF

(max.) period on the condition 1 and 2 below.

1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all

refresh addresses are completed.

2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting

from self-refresh mode.

Note: tREF (max.) / refresh cycles.

The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is

raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recom-

mended. The Self Refresh command is used to retain cell data in the SDR SDRAM. In the Self Refresh mode, the SDR

SDRAM operates refresh cycle asynchronously.

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

CLK

CKE

CLK

CKE

High-Z

Low-Z

CS

RAS

CAS

WE

CAS

WE

A0 ~ A9

A11, 12

A0 ~ A9

A11, 12

Don't Care

BA0, 1

AUTO REFRESH COMMAND

SELF REFRESH ENTRY COMMAND

Note 1: If all banks are in the idle status and CKE is inactive (low level), the self refresh mode is set.

Function

Auto Refresh

CKEn-1

CKEn

CS

RAS CAS WE DQM ADDR

A10/AP

BA

H

L

H

X

Self Refresh Entry

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

MODE REGISTER SET

The mode registers are loaded via the address bits.

BA0 and BA1 are used to select the Mode Register. See the Mode Register description in the register definition section.

The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress, and a

subsequent executable command cannot be issued until tMRD is met.

CLK

CKE

High-Z

CS

RAS

CAS

W E

A0 ~ A9

A11, A12

Code

Don't Care

Code

BA0, 1

MODE REGISTER SET COMMAND

Note:

BA0=BA1=Low loads the Mode Register.

CLK

MRS

NOP

tMRD

Valid

Command

Code

Address

Don't Care

Code = Mode Register / Extended Mode Register selection

(BA0, BA1) and op-code (A0 - An)

tMRD DEFINITION

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

POWER DOWN

Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in

progress. If power down occurs when all banks are idle, it is Precharge Power Down.

If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot

stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is

exited by setting CKE high while issuing a Device Deselect or NOP command.

If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down

occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down

deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby.

C LK

C K E

C K E _ Low

C S

R A S

C A S

W E

A 0 ~ A 9

A 11 , 1 2

B A 0 , 1

D o n 't C are

POWER-DOWN COMMAND

NOTE:

This case shows CKE low coincident with NO OPERATION.

Alternately POWER DOWN entry can be achieved with CKE low coincident with Device DESELECT.

CLK

CKE

COMMAND

All banks idle

NOP

ACTIVE

tRCD

NOP

Input buffers gated off

tRAS

tRC

Enter power-down mode. Exit power-down mode.

DON’T CARE

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

Power Up and Initialization

Like a Synchronous DRAM, Low Power SDRAM(Mobile SDRAM) must be powered up and initialized in a predefined man-

ner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time.

After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile

SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode

register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.)

And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR).

The following these cycles, the Mobile SDRAM is ready for normal opeartion.

Programming the registers

Mode Register

The mode register contains the specific mode of operation of the SDR SDRAM. This register includes the selection of a

burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2 or 3), a burst type. The mode register set must be done before

any activate command after the power up sequence. Any contents of the mode register be altered by re-programming

the mode register through the execution of mode register set command.

Bank(Row) Active

The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by

activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects

the bank, and the value on the A0-A12 selects the row. This row remains active for column access until a precharge

command is issued to that bank. Read and write opeartions can only be initiated on this activated bank after the min-

imum tRCD time is passed from the activate command.

Read

The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and

deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select

the sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Pre-

charge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not

selected, the row will remain active for subsequent accesses.

The length of burst and the CAS latency will be determined by the values programmed during the MRS command.

Write

The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE

and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select

the starting column location. The value on input A10 determines whether or not Auto Precharge is used.

If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Pre-

charge is not selected, the row will remain active for subsequent accesses.

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

Precharge

The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the

precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open

row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the

precharge command is issued.

Auto Precharge

The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If

A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.

Burst Termination

The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst

Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts

a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the

bank open.

Data Mask

The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is

issued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When

this command is issued, data inputs can't be written with no clock delay.

If data mask is initiated by asserting low on DQM during the read cycle, the data outputs are enabled.

If DQM is asserted to High. the data outputs are masked (disabled) and become Hi-Z state after 2 cycle later. During

the write cycle, DQM mask data input with zero latency

CK

WRIT

CMD

DM

Data Masking

0 Latency

Data Masking

0 Latency

Hi-Z

MK

D1

D0

DIN0

D1

D0

D1

D0

DIN2

D1

D0

DQ

MK

Write Data Masking

CK

READ

CMD

DM

DQ

Data Masking

2 Latency

Hi-Z

MK

D0

D1

D0

D1

D0

D1

D0

D1

DOUT0

DOUT1

DDOT2

Read Data Masking

Rev 1.3 / Dec. 2009

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HY57V561620F(L)T(P) Series

Clock Suspend

The Clock Suspend command is used to suspend the internal clock of SDR SDRAM. The clock suspend operation stops

transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation of the

device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends

data Read and Write operations. (See examples in next Figures)

CLK

Command

CKE

RD

Masked by CKE

Internal CLK

DQ

Frozen Int. CLK by CKE

(CKE = Fixed Low)

Q2

Q3

Q4

Q1

Clock Suspend

Mode

Command

CKE

WR

D1

Masked by CKE

Internal CLK

DQ

Frozen Int. CLK by CKE

(CKE = Fixed Low)

D2

D3

D4

Clock Suspend

Mode

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

Power Down

The Power Down command is used to reduce standby current. Before this command is issued, all banks must be pre-

charged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping

CKE low, all of the input buffer except CKE are gated off.

Auto Refresh

The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs.

This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address

bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter.

Self Refresh

The Self Refresh command is used to retain cell data in SDRAM. In the Self Refresh mode, the SDRAM operates refresh

cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disa-

bled(Low).

Rev 1.3 / Dec. 2009

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Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

PACKAGE INFORMATION

L1

A2

A

L

α

A1

millimeters

inches

Typ

Symbol

Min

Typ

-

Max

1.194

0.150

1.050

0.400

0.210

Min

Max

A

A1

A2

B

0.991

0.050

0.950

0.300

0.120

0.0390

0.0020

0.0374

0.012

0.0470

0.0059

0.0413

0.016

0.100

1.000

-

0.0039

0.0394

-

C

-

0.0047

-

0.0083

CP

D1

E

0.10

22.22

11.76

10.16

0.8

0.0039

0.8748

0.4630

0.4

22.149

11.735

10.058

-

22.327

11.938

10.262

-

0.8720

0.4620

0.3950

-

0.8790

0.4700

0.4040

-

E1

e

0.0315

-

L

0.406

-

0.597

-

0.0160

-

0.0235

-

L1

alpha

0.8

0.0315

0 / 5 (min / max)

Rev 1.3 / Dec. 2009

48


型号：	HY57V561620FLTP-6
厂家：	HYNIX SEMICONDUCTOR
描述：	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54 时钟动态存储器光电二极管内存集成电路
文件：	总48页 (文件大小：683K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY57V561620FLTP-6 [HYNIX]

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