HY57V651620BTC-10P [HYNIX]
4 Banks x 1M x 16Bit Synchronous DRAM; 4库x 1米x 16Bit的同步DRAM型号: | HY57V651620BTC-10P |
厂家: | HYNIX SEMICONDUCTOR |
描述: | 4 Banks x 1M x 16Bit Synchronous DRAM |
文件: | 总12页 (文件大小:83K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HY57V651620B
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
T h e H y n i x H Y 5 7 V 6 4 1 6 2 0 H G i s a 6 7 , 1 0 8 , 8 6 4 - b i t C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e m a i n m e m o r y a p p l i c a t i o n s w h i c h
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1, 048, 576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input a n d o u t p u t
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1, 2, 4, 8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Auto refresh and self refresh
•
•
•
Single 3. 3± 0 . 3 V p o w e r s u p p l y N o t e )
4096 refresh cycles / 64ms
All device pins are compatible with LVTTL interface
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
J E D E C s t a n d a r d 4 0 0 m i l 5 4 p i n T S O P - I I w i t h 0 . 8 m m
of pin pitch
•
All inputs and outputs referenced to positive edge of
system clock
•
P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks
•
•
D a t a m a s k f u n c t i o n b y U D Q M o r L D Q M
Internal four banks operation
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
H Y 5 7 V 6 5 1 6 2 0 B T C - 5 5
H Y 5 7 V 6 5 1 6 2 0 B T C - 6
H Y 5 7 V 6 5 1 6 2 0 B T C - 7
H Y 5 7 V 6 5 1 6 2 0 B T C - 7 5
H Y 5 7 V 6 5 1 6 2 0 B T C - 8
H Y 5 7 V 6 5 1 6 2 0 B T C - 1 0 P
H Y 5 7 V 6 5 1 6 2 0 B T C - 1 0 S
H Y 5 7 V 6 5 1 6 2 0 B T C - 1 0
H Y 5 7 V 6 5 1 6 2 0 B L T C - 5 5
H Y 5 7 V 6 5 1 6 2 0 B L T C - 6
H Y 5 7 V 6 5 1 6 2 0 B L T C - 7
H Y 5 7 V 6 5 1 6 2 0 B L T C - 7 5
H Y 5 7 V 6 5 1 6 2 0 B L T C - 8
H Y 5 7 V 6 5 1 6 2 0 B L T C - 1 0 P
H Y 5 7 V 6 5 1 6 2 0 B L T C - 1 0 S
H Y 5 7 V 6 5 1 6 2 0 B L T C - 1 0
1 8 3 M H z
1 6 6 M H z
1 4 3 M H z
1 3 3 M H z
1 2 5 M H z
1 0 0 M H z
1 0 0 M H z
1 0 0 M H z
1 8 3 M H z
1 6 6 M H z
1 4 3 M H z
1 3 3 M H z
1 2 5 M H z
1 0 0 M H z
1 0 0 M H z
1 0 0 M H z
N o r m a l
4 B a n k s x 1 M b i t s
x 1 6
4 0 0 m i l 5 4 p i n T S O P I I
L V T T L
L o w p o w e r
N o t e : V D D ( M i n ) o f H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 5 5 / 6 / 7 i s 3 . 1 3 5 V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
R e v . 1 . 9 / A p r . 0 1
HY57V651620B
PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
1
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V DDQ
DQ8
V SS
NC
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
UDQM
CLK
CKE
NC
BA0
A11
BA1
A 9
A10/AP
A 0
A 8
A 7
A 1
A 6
A 2
A 5
A 3
A 4
VDD
V SS
PIN DESCRIPTION
PIN
P I N N A M E
D E S C R I P T I O N
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
C L K
C l o c k
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
C K E
C S
Clock Enable
Chip Select
E n a b l e s o r d i s a b l e s a l l i n p u t s e x c e p t C L K , C K E a n d D Q M
Selects bank to be activated during R A S activity
Selects bank to be read/written during C A S activity
B A 0 , B A 1
B a n k A d d r e s s
R o w A d d r e s s : R A 0 ~ R A 1 1 , C o l u m n A d d r e s s : C A 0 ~ C A 7
Auto-precharge flag : A10
A 0
~
A 1 1
A d d r e s s
R o w A d d r e s s S t r o b e ,
R A S , C A S a n d W E define the operation
Refer function truth table for details
R A S , C A S, W E
C o l u m n A d d r e s s S t r o b e ,
W r i t e E n a b l e
L D Q M , U D Q M
D Q 0 ~ D Q 1 5
V DD /V S S
D a t a I n p u t / O u t p u t M a s k
D a t a I n p u t / O u t p u t
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
P o w e r S u p p l y / G r o u n d
D a t a O u t p u t P o w e r / G r o u n d
N o C o n n e c t i o n
Power supply for internal circuits and input buffers
Power supply for output buffers
V D D Q /V S S Q
N C
N o c o n n e c t i o n
R e v . 1 . 9 / A p r . 0 1
2
HY57V651620B
FUNCTIONAL BLOCK DIAGRAM
1 M b i t x 4 b a n k s x 1 6 I / O S y n c h r o n o u s D R A M
Self refresh logic
& timer
Internal Row
counter
1Mx16 Bank 3
1Mx16 Bank 2
CLK
CKE
CS
R o w
Pre
R o w a c t i v e
D e c o d e r s
1Mx16 Bank 1
1Mx16 Bank 0
DQ0
DQ1
RAS
CAS
W E
M e m o r y
Cell
refresh
Array
C o l u m n
A c t i v e
C o l u m n
Pre
UDQM
L D Q M
D e c o d e r s
DQ14
DQ15
Y d e c o d e r s
C o l u m n A d d
C o u n t e r
B a n k S e l e c t
A0
A1
A d d r e s s
Registers
B u r s t
C o u n t e r
A11
BA0
BA1
C A S L a t e n c y
P i p e L i n e C o n t r o l
Mode Regist ers
D a t a O u t C o n t r o l
R e v . 1 . 9 / A p r . 0 1
3
HY57V651620B
ABSOLUTE MAXIMUM RATINGS
P a r a m e t e r
S y m b o l
Rating
Unit
A m b i e n t T e m p e r a t u r e
TA
0
~
7 0
°C
S t o r a g e T e m p e r a t u r e
TS T G
- 5 5 ~ 1 2 5
-1.0 ~ 4.6
-1.0 ~ 4.6
5 0
°C
Voltage on Any Pin relative to V S S
Voltage on V D D relative to V S S
Short Circuit Output Current
Power Dissipation
V IN, V O U T
V
V D D , V D D Q
IO S
V
m A
P D
1
W
S o l d e r i n g T e m p e r a t u r e × T i m e
TS O L D E R
2 6 0 × 1 0
°C × S e c
N o t e : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION ( T A = 0 t o 7 0 °C )
P a r a m e t e r
S y m b o l
M i n
Typ.
M a x
Unit
Note
P o w e r S u p p l y V o l t a g e
Input High Voltage
I n p u t L o w V o l t a g e
V D D , V D D Q
3.0
2.0
3.3
3.0
0
3.6
V DDQ + 2. 0
0.8
V
V
V
1,2
1,3
1,4
V IH
V IL
V S S Q - 2.0
N o t e
1.All voltages are referenced to VS S
2 . V D D ( m i n ) o f H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 5 5 / 6 / 7 i s 3 . 1 3 5 V
:
=
0 V
3.V IH (max) is acceptable 5. 6V AC pulse width with £ 3ns of duration
4.V IL (min) is acceptable -2. 0V AC pulse width with £ 3ns of duration
Note2
AC OPERATING CONDITION ( T A = 0 t o 7 0 °C , V D D=3. 3 ± 0 . 3 V
, V S S = 0 V )
P a r a m e t e r
S y m b o l
Value
Unit
N o t e
A C I n p u t H i g h / L o w L e v e l V o l t a g e
V IH / V IL
Vtrip
2.4/0.4
1.4
V
V
I n p u t T i m i n g M e a s u r e m e n t R e f e r e n c e L e v e l V o l t a g e
I n p u t R i s e / F a l l T i m e
tR / tF
Voutref
C L
1
n s
V
O u t p u t T i m i n g M e a s u r e m e n t R e f e r e n c e L e v e l
O u t p u t L o a d C a p a c i t a n c e f o r A c c e s s T i m e M e a s u r e m e n t
1.4
5 0
pF
1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
2 . V D D ( m i n ) o f H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 5 5 / 6 / 7 i s 3 . 1 3 5 V
R e v . 1 . 9 / A p r . 0 1
4
HY57V651620B
CAPACITANCE ( T A = 2 5°C , f = 1 M H z )
P a r a m e t e r
P i n
S y m b o l
M i n
M a x
Unit
Input capacitance
C L K
C I1
CI 2
2
4
5
pF
pF
A 0 ~ A 1 1 , B A 0 , B A 1 , C K E , C S , R A S ,
C A S , W E , U D Q M , L D Q M
2.5
Data input / output capacitance
D Q 0
~
D Q 1 5
C I/O
2
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 W
Output
Output
50pF
50 pF
DC Output Load Circuit
A C O u t p u t L o a d C i r c u i t
Note3
DC CHARACTERISTICS I ( T A = 0 t o 7 0 ° C , V DD =3.3 ± 0 . 3 V
)
P a r a m e t e r
S y m b o l
Min.
M a x
Unit
N o t e
I n p u t L e a k a g e C u r r e n t
O u t p u t L e a k a g e C u r r e n t
O u t p u t H i g h V o l t a g e
O u t p u t L o w V o l t a g e
ILI
-1
-1
1
1
u A
u A
V
1
2
IL O
V O H
V O L
2.4
-
-
IO H = - 4 m A
IO L = + 4 m A
0.4
V
Note :
1.V IN = 0 to 3.6V, All other pins are not tested under V IN = 0 V
2.DO U T is disabled, V O U T =0 to 3.6
3 . . V D D ( m i n ) o f H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 5 5 / 6 / 7 i s 3 . 1 3 5 V
R e v . 1 . 9 / A p r . 0 1
5
HY57V651620B
Note5
DC CHARACTERISTICS II ( T A = 0 t o 7 0 °C , V D D =3.3 ± 0 . 3 V
, V S S = 0 V )
S p e e d
P a r a m e t e r
S y m b o l
Test Condition
Unit
N o t e
- 5 5
- 6
-7
- 7 5
-8
- 1 0 P -10S
-10
Burst length=1, One bank active
tRC tR C(min), IO L = 0 m A
Operating Current
ID D 1
120
110
100
9 0
80
7 0
700
80
m A
1
³
ID D 2 P
C K E £ V IL(max), tC K = min
C K E £ V IL(max), tC K = ¥
2
2
m A
m A
P r e c h a r g e S t a n d b y C u r r e n t
i n P o w e r D o w n M o d e
ID D 2 P S
C K E ³ V IH (min), C S ³ V IH (min), tC K
= min
ID D 2 N
Input signals are changed one time
during 2clks. All other pins ³ V DD -
0. 2V or £ 0 . 2 V
1 5
m A
P r e c h a r g e S t a n d b y C u r r e n t
i n N o n P o w e r D o w n M o d e
C K E
³ V IH (min), tC K = ¥
ID D 2 N S
1 5
m A
Input signals are stable.
C K E £ V IL(max), tC K = min
C K E £ V IL(max), tC K = ¥
ID D 3 P
5
5
m A
m A
Active Standby Current
i n P o w e r D o w n M o d e
ID D 3 P S
C K E ³ V IH (min), C S ³ V IH (min), tC K
= min
ID D 3 N
Input signals are changed one time
during 2clks. All other pins ³ V DD -
0. 2V or £ 0 . 2 V
3 0
3 0
m A
Active Standby Current
i n N o n P o w e r D o w n M o d e
C K E
³ V IH (min), tC K = ¥
ID D 3 N S
m A
Input signals are stable.
tCK
³
tCK (min),
C L = 3
C L = 2
150
9 0
140
90
130
9 0
120
9 0
110
90
9 0
9 0
9 0
9 0
90
90
m A
m A
1
B u r s t M o d e O p e r a t i n g C u r r e n t
A u t o R e f r e s h C u r r e n t
ID D 4
ID D 5
ID D 6
IO L = 0 m A
All banks active
tR R C
³
tR R C (min), All banks active
200
200
200
200
200
180
180
150
m A
m A
uA
2
3
4
2
Self Refresh Current
C K E £ 0 . 2 V
500
N o t e
:
1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh R A S c y c l e t i m e ) i s s h o w n a t A C C H A R A C T E R I S T I C S I I
3 . H Y 5 7 V 6 5 1 6 2 0 B T C - 5 5 / 6 / 7 / 7 5 / 8 / 1 0 P / 1 0 S / 1 0
4 . H Y 5 7 V 6 5 1 6 2 0 B L T C - 5 5 / 6 / 7 / 7 5 / 8 / 1 0 P / 1 0 S / 1 0
5 . . V D D ( m i n ) o f H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 5 5 / 6 / 7 i s 3 . 1 3 5 V
R e v . 1 . 9 / A p r . 0 1
6
HY57V651620B
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-55
-6
-7
- 7 5
-8
- 1 0 P
-10S
-10
P a r a m e t e r
S y m b o l
Unit
N o
Min
55
M a x
Min
6
M a x
Min
7
M a x
M i n
7. 5
10
M a x
M i n
8
M a x
M i n
M a x
Min
10
12
3
M a x
Min
1 0
1 2
3
M a x
C A S Lat enc y
=
=
3
2
tCK3
tCK2
t C H W
tCLW
tAC3
tAC2
t O H
10
10
3
3
-
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
S y s t e m c l o c k
cycle time
1000
1000
1 0 0 0
1000
1000
1000
1 0 0 0
1 0 0 0
C A S Lat enc y
10
10
1 0
2. 5
2. 5
-
10
3
Clock high pulse width
Clock low pulse width
2 . 7 5
2 . 7 5
-
-
2. 5
2. 5
-
-
-
2. 5
2. 5
-
-
-
-
-
-
-
-
-
-
1
1
-
-
-
-
3
3
3
C A S Lat enc y
=
=
3
2
5. 4
5. 4
5. 4
5.4
-
6
6
-
6
6
-
-
6
6
-
-
8
8
-
A c c e s s t i m e f r o m
clock
2
C A S Lat enc y
-
6
-
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
D a t a - o u t h o l d t i m e
2. 5
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1
2. 7
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1
2. 7
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1. 5
2. 7
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1. 5
0. 8
1
-
3
3
2
1
2
1
2
1
2
1
1
3
3
3
3
Data-Input setup time
Data-Input hold time
A d d r e s s s e t u p t i m e
A d d r e s s h o l d t i m e
t D S
-
2
-
-
2
-
3
-
1
1
1
1
1
1
1
1
t D H
-
1
-
-
1
-
1
-
t A S
-
2
-
-
2
-
3
-
t A H
-
1
-
-
1
-
1
-
C K E s e t u p t i m e
tCKS
tCKH
t C S
-
2
-
-
2
-
3
-
C K E h o l d t i m e
-
1
-
-
1
-
1
-
C o m m a n d s e t u p t i m e
C o m m a n d h o l d t i m e
C L K t o d a t a o u t p u t i n l o w Z - t i m e
-
-
2
-
-
2
-
3
-
t C H
1
-
-
1
-
1
-
tOLZ
t O H Z 3
t O H Z 2
-
1
-
-
1
-
1
-
C A S Lat enc y
=
=
3
2
2. 7
3
5.4
6
3
6
6
6
6
3
6
6
3
8
8
C L K t o d a t a o u t p u t
5. 4
5. 4
5. 4
in high Z-time
C A S Lat enc y
3
3
3
Note :
1. Assume tR / tF (input rise and fall time ) is 1ns
2. Access times to be measured with input signals of 1v/ns edge rate
R e v . 1 . 9 / A p r . 0 1
7
HY57V651620B
AC CHARACTERISTICS I
-55
-6
-7
-75
-8
- 1 0 P
-10S
- 1 0
P a r a m e t e r
S y m b o l
Unit
N o t e
M i n
M a x
Min
60
60
18
42
18
12
1
M a x
Min
70
702
20
42
20
14
1
Max
Min
65
65
20
45
20
15
1
M a x
Min
6 8
6 8
2 0
4 8
2 0
1 6
1
M a x
Min
70
70
20
50
20
20
1
M a x
M i n
M a x
Min
80
96
30
50
30
20
1
M a x
Operation
55
-
-
-
-
-
-
-
-
-
-
7 0
7 0
2 0
5 0
2 0
2 0
1
-
-
n s
n s
tR C
R A S Cycle Time
A u t o R e f r e s h
60
-
-
-
-
-
-
tR R C
tR C D
tR A S
tR P
R A S to C A S D e l a y
R A S Active Time
16.5
-
-
-
-
-
-
n s
38.5
100K
1 0 0 K
120K
1 0 0 K
100K
1 0 0 K
100K
1 0 0 K
n s
R A S P r e c h a r g e T i m e
16.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
n s
R A S to R A S Bank Active Delay
C A S to C A S D e l a y
11
1
0
2
5
2
0
2
3
2
1
1
-
-
-
n s
tR R D
tC C D
tW T L
tD P L
-
-
-
-
-
-
-
-
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
m s
W r i t e C o m m a n d t o D a t a - I n D e l a y
D a t a - I n t o P r e c h a r g e C o m m a n d
D a t a - I n t o A c t i v e C o m m a n d
D Q M t o D a t a - O u t H i - Z
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
-
2
-
1
-
2
-
2
-
1
-
1
-
1
-
-
5
-
4
-
5
-
5
-
3
-
3
-
4
-
tD A L
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
tD Q Z
tD Q M
tM R D
tP R O Z 3
tP R O Z 2
tP D E
tS R E
tR E F
D Q M t o D a t a - I n M a s k
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
M R S t o N e w C o m m a n d
-
2
-
1
-
2
-
2
-
2
-
2
-
2
-
C A S Lat enc y
C A S Lat enc y
=
=
3
2
-
3
-
3
-
3
-
3
-
3
-
3
-
3
-
Precharge to
Data Output Hi-Z
-
-
2
-
2
-
-
2
-
2
-
2
-
2
-
2
-
P o w e r D o w n E x i t T i m e
S e l f R e f r e s h E x i t T i m e
R e f r e s h T i m e
1
-
1
1
-
1
-
1
-
1
-
1
-
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
6 4
-
64
-
6 4
-
64
-
64
-
64
-
64
-
64
Note :
1 . A n e w c o m m a n d c a n b e g i v e n t R R C a f t e r s e l f r e f r e s h e x i t
R e v . 1 . 9 / A p r . 0 1
8
HY57V651620B
DEVICE OPERATING OPTION TABLE
H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 5 5
C A S L a t e n c y
t R C D
t R A S
tRC
t R P
t A C
t O H
1 8 3 M H z ( 6 n s )
1 6 6 M H z ( 7 n s )
1 4 3 M H z ( 7 n s )
3 C L K s
3 C L K s
3 C L K s
3 C L K s
3 C L K s
3 C L K s
7 C L K s
7 C L K s
7 C L K s
1 0 C L K s
1 0 C L K s
1 0 C L K s
3 C L K s
3 C L K s
3 C L K s
5 . 4 n s
5 . 4 n s
5 . 4 n s
2 . 7 n s
2 . 7 n s
2 . 7 n s
H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 6
C A S L a t e n c y
3 C L K s
t R C D
t R A S
tRC
t R P
t A C
t O H
1 6 6 M H z ( 6 n s )
1 4 3 M H z ( 7 n s )
1 3 3 M H z ( 7 . 5 n s )
3 C L K s
3 C L K s
3 C L K s
7 C L K s
7 C L K s
6 C L K s
1 0 C L K s
1 0 C L K s
9 C L K s
3 C L K s
3 C L K s
3 C L K s
5 . 4 n s
5 . 4 n s
5 . 4 n s
2 . 7 n s
2 . 7 n s
2 . 7 n s
3 C L K s
3 C L K s
H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 7
C A S L a t e n c y
3 C L K s
t R C D
t R A S
tRC
t R P
t A C
t O H
1 4 3 M H z ( 7 n s )
1 3 3 M H z ( 7 . 5 n s )
1 2 5 M H z ( 8 n s )
3 C L K s
3 C L K s
3 C L K s
7 C L K s
6 C L K s
6 C L K s
1 0 C L K s
9 C L K s
9 C L K s
3 C L K s
3 C L K s
2 C L K s
5 . 4 n s
5 . 4 n s
6 n s
2 . 7 n s
2 . 7 n s
3 n s
3 C L K s
3 C L K s
H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 7 5
C A S L a t e n c y
t R C D
t R A S
tRC
t R P
t A C
t O H
1 3 3 M H z ( 7 . 5 n s )
1 2 5 M H z ( 8 n s )
1 0 0 M H z ( 1 0 n s )
3 C L K s
3 C L K s
2 C L K s
3 C L K s
3 C L K s
2 C L K s
6 C L K s
6 C L K s
5 C L K s
9 C L K s
9 C L K s
7 C L K s
3 C L K s
3 C L K s
2 C L K s
5 . 4 n s
6 n s
2 . 7 n s
3 n s
6 n s
3 n s
H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 8
C A S L a t e n c y
3 C L K s
t R C D
t R A S
tRC
t R P
t A C
t O H
1 2 5 M H z ( 8 n s )
1 0 0 M H z ( 1 0 n s )
8 3 M H z ( 1 2 n s )
3 C L K s
2 C L K s
3 C L K s
7 C L K s
5 C L K s
6 C L K s
1 0 C L K s
7 C L K s
9 C L K s
3 C L K s
3 C L K s
2 C L K s
6 n s
6 n s
6 n s
3 n s
3 n s
3 n s
2 C L K s
3 C L K s
H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 1 0 P
C A S L a t e n c y
t R C D
t R A S
tRC
t R P
t A C
t O H
1 0 0 M H z ( 1 0 n s )
8 3 M H z ( 1 2 n s )
6 6 M H z ( 1 5 n s )
2 C L K s
2 C L K s
2 C L K s
2 C L K s
2 C L K s
2 C L K s
5 C L K s
5 C L K s
4 C L K s
7 C L K s
7 C L K s
6 C L K s
2 C L K s
2 C L K s
2 C L K s
6 n s
6 n s
6 n s
3 n s
3 n s
3 n s
R e v . 1 . 9 / A p r . 0 1
9
H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 1 0 S
C A S
t R C D
t R A S
t R C
t R P
tAC
t O H
L a t e n c y
1 0 0 M H z ( 1 0 n s )
8 3 M H z ( 1 2 n s )
6 6 M H z ( 1 5 n s )
3 C L K s
2 C L K s
2 C L K s
3 C L K s
2 C L K s
2 C L K s
5 C L K s
5 C L K s
4 C L K s
8 C L K s
7 C L K s
6 C L K s
3 C L K s
2 C L K s
2 C L K s
6 n s
6 n s
6 n s
3 n s
3 n s
3 n s
5 7 V 6 5 1 6 2 0 B ( L ) T C - 1 0
C A S
t R C D
t R A S
t R C
t R P
tAC
t O H
L a t e n c y
1 0 0 M H z ( 1 0 n s )
8 3 M H z ( 1 2 n s )
6 6 M H z ( 1 5 n s )
3 C L K s
2 C L K s
2 C L K s
3 C L K s
2 C L K s
2 C L K s
5 C L K s
5 C L K s
4 C L K s
8 C L K s
7 C L K s
6 C L K s
3 C L K s
2 C L K s
2 C L K s
8 n s
6 n s
6 n s
3 n s
3 n s
3 n s
HY57V651620B
COMMAND TRUTH TABLE
A 1 0 /
A P
A D D R
C o m m a n d
C K E n - 1
C K E n
C S
R A S
C A S
W E
D Q M
BA
N o t e
M o d e R e g i s t e r S e t
H
H
H
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
O P c o d e
No Operation
X
X
X
X
X
X
X
Bank Active
L
R A
V
V
Read
L
H
L
L
L
H
H
L
L
L
H
L
C A
C A
X
R e a d w i t h A u t o p r e c h a r g e
Write
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
P r e c h a r g e s e l e c t e d B a n k
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
D Q M
Auto Refresh
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
Entry
L
1
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
Self Refresh
Exit
L
H
L
H
L
X
X
X
H
L
Entry
P r e c h a r g e
p o w e r d o w n
H
L
Exit
H
H
L
Entry
C l o c k
H
L
L
X
X
S u s p e n d
Exit
H
X
N o t e
:
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2 . X = D o n¢t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,
O p c o d e = O p e r a n d C o d e , N O P = N o O p e r a t i o n
R e v . 1 . 9 / A p r . 0 1
1 1
HY57V651620B
PACKAGE INFORMATION
4 0 0 m i l 5 4 p i n T h i n S m a l l O u t l i n e P a c k a g e
U N I T : m m ( i n c h )
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0. 150(0. 0059)
0. 050(0. 0020)
1. 194(0. 0470)
0. 991(0. 0390)
5 d e g
0 d e g
0. 210(0. 0083)
0. 120(0. 0047)
0. 597(0. 0235)
0. 406(0. 0160)
0. 400(0. 016)
0. 80(0. 0315)BSC
0. 300(0. 012)
R e v . 1 . 9 / A p r . 0 1
1 2
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