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HY5DU121622DTP-J [HYNIX]

DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66;
HY5DU121622DTP-J
型号： HY5DU121622DTP-J
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66

动态存储器 双倍数据速率
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HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
512Mb DDR SDRAM  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume  
any responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.0/Feb. 2003  
1
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
Revision History  
1. Rev 0.0 (Feb. 19)  
1) Datasheet Release in Preliminary version  
Rev. 0.0/Feb. 2003  
2
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
PRELIMINARY  
DESCRIPTION  
The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data  
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density  
and high bandwidth.  
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the  
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,  
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-  
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible  
with SSTL_2.  
FEATURES  
•
•
VDD, VDDQ = 2.5V +/- 0.2V  
•
All addresses and control inputs except data, data  
strobes and data masks latched on the rising edges  
of the clock  
All inputs and outputs are compatible with SSTL_2  
interface  
•
•
Programmable /CAS latency 2 / 2.5/ 3 supported  
•
•
•
Fully differential clock inputs (CK, /CK) operation  
Double data rate interface  
Programmable burst length 2 / 4 / 8 with both  
sequential and interleave mode  
Source synchronous - data transaction aligned to  
bidirectional data strobe (DQS)  
•
Internal four bank operations with single pulsed  
/RAS  
•
•
x16 device has two bytewide data strobes (UDQS,  
LDQS) per each x8 I/O  
•
•
•
•
Auto refresh and self refresh supported  
tRAS lock out function supported  
8192 refresh cycles / 64ms  
Data outputs on DQS edges when read (edged DQ)  
Data inputs on DQS centers when write (centered  
DQ)  
JEDEC standard 400mil 66pin TSOP-II with 0.65mm  
pin pitch  
•
•
On chip DLL align DQ and DQS transition with CK  
transition  
•
Full and Half strength driver option controlled by  
EMRS  
DM mask write data-in at the both rising and falling  
edges of the data strobe  
ORDERING INFORMATION  
OPERATING FREQUENCY  
Remark  
(CL-tRCD-tRP)  
Part No.  
Configuration  
Package  
Grade  
CL3  
HY5DU12422A(L)T-X*  
HY5DU12822A(L)T-X*  
HY5DU121622A(L)T-X*  
128Mx4  
64Mx8  
400mil  
66pin  
- D4  
200MHz  
200MHz  
DDR400 (3-4-4)  
DDR400 (3-3-3)  
- D43  
32Mx16  
TSOP-II  
* Note : D of speed indicates DDR400.  
Rev. 0.0 / Feb. 2003  
3
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
PIN CONFIGURATION  
x4  
x8  
x16  
x16  
x8  
x4  
VSS  
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VDDQ  
DQ8  
NC  
VSS  
DQ7  
VSSQ  
NC  
1
2
VDD  
NC  
VDD  
DQ0  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
VSSQ  
DQ7  
NC  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
VSS  
NC  
3
VDDQ  
NC  
VDDQ  
NC  
VSSQ  
NC  
4
DQ6  
VDDQ  
NC  
5
DQ0  
VSSQ  
NC  
DQ1  
VSSQ  
NC  
DQ3  
VDDQ  
NC  
6
7
DQ5  
VSSQ  
NC  
8
NC  
DQ2  
VDDQ  
NC  
NC  
9
VDDQ  
NC  
VSSQ  
NC  
10  
DQ4  
VDDQ  
NC  
DQ1  
VSSQ  
NC  
DQ3  
VSSQ  
NC  
DQ2  
VDDQ  
NC  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
NC  
NC  
NC  
NC  
VSSQ  
UDQS  
NC  
VSSQ  
DQS  
NC  
VDDQ  
NC  
VDDQ  
NC  
VDDQ  
LDQS  
NC  
400mil X 875mil  
66pin TSOP -II  
0.65mm pin pitch  
VSSQ  
DQS  
NC  
NC  
NC  
VREF  
VSS  
UDM  
/CK  
VREF  
VSS  
DM  
VDD  
NC  
VDD  
NC  
VDD  
NC  
VREF  
VSS  
DM  
NC  
NC  
LDM  
/WE  
/CK  
CK  
/WE  
/CAS  
/RAS  
/CS  
/WE  
/CAS  
/RAS  
/CS  
/CK  
CK  
CK  
/CAS  
/RAS  
/CS  
CKE  
NC  
CKE  
NC  
CKE  
NC  
A12  
A12  
A11  
A9  
NC  
NC  
NC  
A12  
A11  
A9  
A11  
BA0  
BA1  
A10/AP  
A0  
BA0  
BA1  
A10/AP  
A0  
BA0  
BA1  
A10/AP  
A0  
A9  
A8  
A8  
A8  
A7  
A7  
A7  
A6  
A6  
A1  
A1  
A1  
A6  
A5  
A5  
A2  
A2  
A2  
A5  
A4  
A4  
A3  
A3  
A3  
A4  
VSS  
VSS  
VDD  
VDD  
VDD  
VSS  
ROW AND COLUMN ADDRESS TABLE  
ITEMS  
128Mx4  
64Mx8  
32Mx16  
Organization  
Row Address  
32M x 4 x 4banks  
A0 - A12  
16M x 8 x 4banks  
A0 - A12  
A0-A9, A11  
BA0, BA1  
A10  
8M x 16 x 4banks  
A0 - A12  
A0-A9  
Column Address  
Bank Address  
Auto Precharge Flag  
Refresh  
A0-A9, A11, A12  
BA0, BA1  
A10  
BA0, BA1  
A10  
8K  
8K  
8K  
Rev. 0.0/Feb. 2003  
4
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
PIN DESCRIPTION  
PIN  
TYPE  
DESCRIPTION  
Clock: CK and /CK are differential clock inputs. All address and control input signals are  
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output  
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).  
CK, /CK  
Input  
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and  
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER  
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row  
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF  
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE  
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding  
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are  
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW  
level after Vdd is applied.  
CKE  
Input  
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-  
mands are masked when CS is registered high. CS provides for external bank selection on  
systems with multiple banks. CS is considered part of the command code.  
/CS  
Input  
Input  
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-  
CHARGE command is being applied.  
BA0, BA1  
Address Inputs: Provide the row address for ACTIVE commands, and the column address  
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the  
memory array in the respective bank. A10 is sampled during a precharge command to  
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10  
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The  
address inputs also provide the op code during a MODE REGISTER SET command. BA0  
and BA1 define which mode register is loaded during the MODE REGISTER SET command  
(MRS or EMRS).  
A0 ~ A12  
Input  
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being  
entered.  
/RAS, /CAS, /WE  
Input  
Input  
Input Data Mask: DM is an input mask signal for write data. Input data is masked when  
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled  
on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ  
and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre-  
sponds to the data on DQ8-Q15.  
DM  
(LDM,UDM)  
Data Strobe: Output with read data, input with write data. Edge aligned with read data,  
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the  
data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.  
DQS  
(LDQS,UDQS)  
I/O  
DQ  
VDD/VSS  
VDDQ/VSSQ  
VREF  
I/O  
Data input / output pin : Data bus  
Supply  
Supply  
Supply  
NC  
Power supply for internal circuits and input buffers.  
Power supply for output buffers for noise immunity.  
Reference voltage for inputs for SSTL interface.  
No connection.  
NC  
Rev. 0.0/Feb. 2003  
5
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
FUNCTIONAL BLOCK DIAGRAM (128Mx4)  
4Banks x 32Mbit x 4 I/O Double Data Rate Synchronous DRAM  
4
Write Data Register  
2-bit Prefetch Unit  
DS  
8
Bank  
Control  
CLK  
/CLK  
CKE  
/CS  
/RAS  
/CAS  
/WE  
DM  
32Mx4/Bank0  
32Mx4/Bank1  
32Mx4/Bank2  
32Mx4/Bank3  
8
4
Command  
Decoder  
DQ [0:3]  
Mode  
Register  
Row  
Decoder  
Column Decoder  
DQS  
A0~A12  
Address  
Buffer  
Column Address  
Counter  
Data Strobe  
Transmitter  
BA0, BA1  
CLK_DLL  
Data Strobe  
Receiver  
DS  
CLK  
/CLK  
DLL  
Block  
Mode  
Register  
Rev. 0.0/Feb. 2003  
6
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
FUNCTIONAL BLOCK DIAGRAM (64Mx8)  
4Banks x 16Mbit x 8 I/O Double Data Rate Synchronous DRAM  
8
Write Data Register  
2-bit Prefetch Unit  
DS  
16  
Bank  
Control  
CLK  
/CLK  
CKE  
/CS  
/RAS  
/CAS  
/WE  
DM  
16Mx8/Bank0  
16Mx8/Bank1  
16Mx8/Bank2  
16Mx8/Bank3  
16  
8
Command  
Decoder  
DQ [0:7]  
Mode  
Register  
Row  
Decoder  
Column Decoder  
DQS  
A0~A12  
BA0,BA1  
Address  
Buffer  
Column Address  
Counter  
Data Strobe  
Transmitter  
CLK_DLL  
Data Strobe  
Receiver  
DS  
CLK  
/CLK  
DLL  
Block  
Mode  
Register  
Rev. 0.0/Feb. 2003  
7
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
FUNCTIONAL BLOCK DIAGRAM (32Mx16)  
4Banks x 8Mbit x 16 I/O Double Data Rate Synchronous DRAM  
16  
Write Data Register  
2-bit Prefetch Unit  
DS  
32  
CLK  
/CLK  
CKE  
Bank  
Control  
8Mx16/Bank0  
8Mx16/Bank1  
8Mx16/Bank2  
8Mx16/Bank3  
32  
16  
/CS  
Command  
Decoder  
/RAS  
/CAS  
/WE  
LDM  
UDM  
DQ[0:15]  
Mode  
Register  
Row  
Decoder  
Column Decoder  
A0~A12  
LDQS, UDQS  
Address  
Buffer  
Column Address  
Counter  
Data Strobe  
Transmitter  
BA0, BA1  
CLK_DLL  
LDQS  
UDQS  
Data Strobe  
Receiver  
CLK  
/CLK  
DLL  
Block  
Mode  
Register  
Rev. 0.0/Feb. 2003  
8
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
SIMPLIFIED COMMAND TRUTH TABLE  
A10/  
AP  
Command  
CKEn-1  
CKEn  
CS  
RAS  
CAS  
WE  
ADDR  
BA  
Note  
Extended Mode Register Set  
Mode Register Set  
Device Deselect  
No Operation  
H
H
X
X
L
L
L
L
L
L
L
L
OP code  
OP code  
1,2  
1,2  
H
L
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active  
L
RA  
V
V
1
1
Read  
L
H
L
L
L
L
H
H
L
L
L
H
L
CA  
CA  
X
Read with Autoprecharge  
Write  
1,3  
1
H
H
X
X
V
Write with Autoprecharge  
Precharge All Banks  
Precharge selected Bank  
Read Burst Stop  
Auto Refresh  
H
H
L
1,4  
1,5  
1
X
V
H
L
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry  
L
L
L
1
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
Self Refresh  
Exit  
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry  
Precharge Power  
Down Mode  
H
L
Exit  
H
H
L
Entry  
H
L
L
Active Power  
Down Mode  
Exit  
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )  
Note :  
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.  
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.  
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP  
period from Prechagre command.  
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented  
to activated bank until CK(n+BL/2+tRP).  
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented  
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time  
(tWR) is needed to guarantee that the last data has been completely written.  
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be  
precharged.  
Rev. 0.0/Feb. 2003  
9
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
WRITE MASK TRUTH TABLE  
/CS, /RAS,  
/CAS, /WE  
A10/  
ADDR  
Function  
CKEn-1  
CKEn  
DM  
BA  
Note  
AP  
Data Write  
Data-In Mask  
H
H
X
X
X
X
L
X
X
1
1
H
Note :  
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related  
with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15)  
respectively.  
Rev. 0.0/Feb. 2003  
10  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
OPERATION COMMAND TRUTH TABLE-I  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
NOP or power down3  
NOP or power down3  
ILLEGAL4  
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DSEL  
NOP  
X
X
BST  
ILLEGAL4  
H
BA, CA, AP  
READ/READAP  
IDLE  
ILLEGAL4  
Row Activation  
NOP  
L
L
L
L
L
H
L
L
H
L
L
H
H
L
L
H
L
BA, CA, AP  
WRITE/WRITEAP  
ACT  
BA, RA  
L
BA, AP  
PRE/PALL  
AREF/SREF  
MRS  
Auto Refresh or Self Refresh5  
L
H
L
X
L
L
OPCODE  
Mode Register Set  
X
H
H
X
H
H
X
H
L
X
X
X
DSEL  
NOP  
NOP  
NOP  
ILLEGAL4  
Begin read : optional AP6  
Begin write : optional AP6  
ILLEGAL4  
BST  
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
ROW  
ACTIVE  
H
H
L
H
L
Precharge7  
L
PRE/PALL  
ILLEGAL11  
L
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
Continue burst to end  
Continue burst to end  
Terminate burst  
X
X
NOP  
BST  
Term burst, new read:optional AP8  
ILLEGAL  
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
L
READ  
ILLEGAL4  
H
H
L
H
L
L
PRE/PALL  
AREF/SREF  
Term burst, precharge  
ILLEGAL11  
L
H
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
Continue burst to end  
Continue burst to end  
L
WRITE  
ILLEGAL4  
Term burst, new read:optional AP8  
Term burst, new write:optional AP  
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, CA, AP  
READ/READAP  
WRITE/WRITEAP  
Rev. 0.0/Feb. 2003  
11  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
OPERATION COMMAND TRUTH TABLE-II  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
ILLEGAL4  
L
L
L
L
L
L
H
H
L
H
L
BA, RA  
BA, AP  
X
ACT  
PRE/PALL  
AREF/SREF  
Term burst, precharge  
WRITE  
ILLEGAL11  
H
ILLEGAL11  
Continue burst to end  
Continue burst to end  
ILLEGAL  
L
H
L
L
X
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
H
H
H
X
X
NOP  
L
BST  
ILLEGAL10  
ILLEGAL10  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL11  
L
H
BA, CA, AP  
READ/READAP  
READ  
WITH  
AUTOPRE-  
CHARGE  
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, RA  
BA, AP  
X
WRITE/WRITEAP  
ACT  
PRE/PALL  
AREF/SREF  
H
ILLEGAL11  
Continue burst to end  
Continue burst to end  
ILLEGAL  
L
H
L
L
X
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
H
H
H
X
X
NOP  
L
BST  
ILLEGAL10  
ILLEGAL10  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL11  
L
H
BA, CA, AP  
READ/READAP  
WRITE  
AUTOPRE-  
CHARGE  
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, RA  
BA, AP  
X
WRITE/WRITEAP  
ACT  
PRE/PALL  
AREF/SREF  
H
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP-Enter IDLE after tRP  
NOP-Enter IDLE after tRP  
ILLEGAL4  
ILLEGAL4,10  
ILLEGAL4,10  
L
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
READ/READAP  
WRITE/WRITEAP  
ACT  
PRE-  
CHARGE  
ILLEGAL4,10  
H
H
L
H
L
L
PRE/PALL  
AREF/SREF  
MRS  
NOP-Enter IDLE after tRP  
ILLEGAL11  
ILLEGAL11  
L
H
L
X
L
L
OPCODE  
Rev. 0.0/Feb. 2003  
12  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
OPERATION COMMAND TRUTH TABLE-III  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
H
L
X
H
H
X
H
H
X
H
L
X
X
X
DSEL  
NOP  
BST  
NOP - Enter ROW ACT after tRCD  
NOP - Enter ROW ACT after tRCD  
ILLEGAL4  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL4,9,10  
ILLEGAL4,10  
ILLEGAL11  
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
ROW  
ACTIVATING  
H
H
L
H
L
L
PRE/PALL  
L
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
X
NOP - Enter ROW ACT after tWR  
NOP - Enter ROW ACT after tWR  
NOP  
ILLEGAL4  
ILLEGAL  
ILLEGAL  
X
BST  
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
READ/READAP  
WRITE/WRITEAP  
ACT  
WRITE  
RECOVERING  
L
ILLEGAL4,10  
ILLEGAL4,11  
ILLEGAL11  
H
H
L
L
L
L
H
L
L
BA, AP  
X
PRE/PALL  
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP - Enter precharge after tDPL  
NOP - Enter precharge after tDPL  
ILLEGAL4  
ILLEGAL4,8,10  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL4,11  
ILLEGAL11  
L
WRITE  
RECOVERING  
WITH  
AUTOPRE-  
CHARGE  
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
H
H
L
H
L
L
PRE/PALL  
L
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP - Enter IDLE after tRC  
NOP - Enter IDLE after tRC  
REFRESHING  
ILLEGAL11  
ILLEGAL11  
L
L
H
L
H
BA, CA, AP  
READ/READAP  
Rev. 0.0/Feb. 2003  
13  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
OPERATION COMMAND TRUTH TABLE-IV  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, RA  
BA, AP  
X
WRITE/WRITEAP  
ACT  
WRITE  
PRE/PALL  
AREF/SREF  
H
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP - Enter IDLE after tMRD  
NOP - Enter IDLE after tMRD  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
L
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
READ/READAP  
WRITE/WRITEAP  
ACT  
MODE  
REGISTER  
ACCESSING  
H
H
L
H
L
L
PRE/PALL  
AREF/SREF  
MRS  
L
H
L
X
L
L
OPCODE  
Note :  
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,  
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.  
2. All entries assume that CKE was active(high level) during the preceding clock cycle.  
3. If both banks are idle and CKE is inactive(low level), then in power down mode.  
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of  
that bank.  
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.  
6. Illegal if tRCD is not met.  
7. Illegal if tRAS is not met.  
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
9. Illegal if tRRD is not met.  
10. Illegal for single bank, but legal for other banks in multi-bank devices.  
11. Illegal for all banks.  
Rev. 0.0/Feb. 2003  
14  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
CKE FUNCTION TRUTH TABLE  
Current  
State  
CKEn-  
1
CKEn  
/CS  
/RAS  
/CAS  
/WE  
/ADD  
Action  
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID  
Exit self refresh, enter idle after tSREX  
Exit self refresh, enter idle after tSREX  
ILLEGAL  
L
SELF  
REFRESH1  
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL  
L
L
X
X
X
X
H
H
L
ILLEGAL  
L
X
X
H
L
X
X
X
H
H
H
L
NOP, continue self refresh  
INVALID  
H
L
X
H
H
H
H
H
L
Exit power down, enter idle  
Exit power down, enter idle  
ILLEGAL  
L
POWER  
DOWN2  
L
L
L
L
X
X
X
X
H
X
H
L
ILLEGAL  
L
L
X
X
X
L
ILLEGAL  
L
X
X
L
X
X
L
NOP, continue power down mode  
See operation command truth table  
Enter self refresh  
Exit power down  
Exit power down  
ILLEGAL  
H
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
L
X
H
H
L
L
ALL BANKS  
IDLE4  
L
L
L
L
X
X
L
ILLEGAL  
L
L
H
L
ILLEGAL  
L
L
L
ILLEGAL  
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP  
H
H
L
H
L
See operation command truth table  
ANY STATE  
OTHER  
THAN  
ILLEGAL5  
INVALID  
INVALID  
H
L
ABOVE  
L
Note :  
When CKE=L, all DQ and DQS must be in Hi-Z state.  
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.  
2. All command can be stored after 2 clocks from low to high transition of CKE.  
3. Illegal if CK is suspended or stopped during the power down mode.  
4. Self refresh can be entered only from the all banks idle state.  
5. Disabling CK may cause malfunction of any bank which is in active state.  
Rev. 0.0/Feb. 2003  
15  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
SIMPLIFIED STATE DIAGRAM  
MRS  
SREF  
SREX  
MODE  
REGISTER  
SET  
SELF  
REFRESH  
IDLE  
PDEN  
PDEX  
AREF  
ACT  
POWER  
DOWN  
AUTO  
REFRESH  
POWER  
DOWN  
PDEN  
BST  
PDEX  
BANK  
ACTIVE  
READ  
WRITE  
READ  
READAP  
WRITE  
WITH  
READ  
WITH  
READAP  
WRITE  
READ  
AUTOPRE-  
CHARGE  
AUTOPRE-  
CHARGE  
WRITEAP  
WRITEAP  
WRITE  
PRE(PALL)  
PRE(PALL)  
PRE-  
CHARGE  
Command Input  
POWER-UP  
Automatic Sequence  
POWER APPLIED  
Rev. 0.0/Feb. 2003  
16  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
POWER-UP SEQUENCE AND DEVICE INITIALIZATION  
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those  
specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF  
(and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent dam-  
age to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT.  
Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect  
an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to  
guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal oper-  
ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR  
SDRAM requires a 200us delay prior to applying an executable command.  
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be  
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED  
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE  
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating  
parameters. 200 clock cycles are required between the DLL reset and any command. During the 200 cycles of CK, for  
DLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200  
clock cycles, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.  
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command  
for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the  
DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.  
1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-  
MOS low state. (All the other input pins may be undefined.)  
• VDD and VDDQ are driven from a single power converter output.  
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.  
• VREF tracks VDDQ/2.  
• A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the  
input current from the VTT supply into any pin.  
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-  
ship must be adhered to during power up.  
Voltage description  
VDDQ  
Sequencing  
Voltage relationship to avoid latch-up  
< VDD + 0.3V  
After or with VDD  
After or with VDDQ  
After or with VDDQ  
VTT  
< VDDQ + 0.3V  
VREF  
< VDDQ + 0.3V  
2. Start clock and maintain stable clock for a minimum of 200usec.  
3. After stable power and clock, apply NOP condition and take CKE high.  
4. Issue Extended Mode Register Set (EMRS) to enable DLL.  
5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200  
cycles of clock are required for locking DLL)  
6. Issue Precharge commands for all banks of the device.  
Rev. 0.0/Feb. 2003  
17  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
7. Issue 2 or more Auto Refresh commands.  
8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low  
Power-Up Sequence  
VDD  
VDDQ  
tVTD  
VTT  
VREF  
/CLK  
CLK  
tIS tIH  
CKE  
NOP  
PRE  
EMRS  
MRS  
NOP  
PRE  
AREF  
MRS  
CMD  
DM  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
ADDR  
A10  
BA0,BA1  
DQS  
DQ’s  
T=200usec  
tMRD  
200 cycles of CK*  
tRP  
tRFC  
tRP  
Power up  
EMRS Set  
MRS Set  
Reset DLL  
(with A8=H)  
2 or more  
MRS Set  
Precharge All  
Precharge All  
VDD and CK stable  
Auto Refresh (with A8=L)  
*200 cycles of CK are required (for DLL locking) before any executable command can be applied.  
Rev. 0.0/Feb. 2003  
18  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
MODE REGISTER SET (MRS)  
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,  
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the  
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and  
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to  
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is  
determined, the information will be held until resetted by another MRS command.  
BA1 BA0 A12 A11 A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
BT  
A2  
A1  
A0  
0
0
RFU  
DR  
TM  
CAS Latency  
Burst Length  
BA0  
0
MRS Type  
MRS  
A8  
0
DLL Reset  
No  
A7  
0
Test Mode  
Normal  
Test  
1
EMRS  
1
Yes  
1
Burst Length  
Sequential Interleave  
A2  
A1  
A0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
2
Reserved  
2
A6  
0
A5  
0
A4  
CAS Latency  
Reserved  
Reserved  
2
0
1
0
1
0
1
0
1
4
4
0
0
8
8
0
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
1
3
1
0
Reserved  
Reserved  
2.5  
1
0
1
1
1
1
Reserved  
A3  
0
Burst Type  
Sequential  
Interleave  
1
Rev. 0.0/Feb. 2003  
19  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
BURST DEFINITION  
Burst Length  
2
Starting Address (A2,A1,A0)  
Sequential  
0, 1  
Interleave  
XX0  
XX1  
X00  
X01  
X10  
X11  
000  
001  
010  
011  
100  
101  
110  
111  
0, 1  
1, 0  
1, 0  
0, 1, 2, 3  
0, 1, 2, 3  
1, 2, 3, 0  
1, 0, 3, 2  
4
2, 3, 0, 1  
2, 3, 0, 1  
3, 0, 1, 2  
3, 2, 1, 0  
0, 1, 2, 3, 4, 5, 6, 7  
1, 2, 3, 4, 5, 6, 7, 0  
2, 3, 4, 5, 6, 7, 0, 1  
3, 4, 5, 6, 7, 0, 1, 2  
4, 5, 6, 7, 0, 1, 2, 3  
5, 6, 7, 0, 1, 2, 3, 4  
6, 7, 0, 1, 2, 3, 4, 5  
0, 1, 2, 3, 4, 5, 6, 7  
0, 1, 2, 3, 4, 5, 6, 7  
1, 0, 3, 2, 5, 4, 7, 6  
2, 3, 0, 1, 6, 7, 4, 5  
3, 2, 1, 0, 7, 6, 5, 4  
4, 5, 6, 7, 0, 1, 2, 3  
5, 4, 7, 6, 1, 0, 3, 2  
6, 7, 4, 5, 2, 3, 0, 1  
7, 6, 5, 4, 3, 2, 1, 0  
8
BURST LENGTH & TYPE  
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst  
length determines the maximum number of column locations that can be accessed for a given Read or Write com-  
mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.  
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.  
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All  
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is  
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2 -Ai when the burst length  
is set to four and by A3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit  
for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location  
within the block. The programmed burst length applies to both Read and Write bursts.  
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the  
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the  
burst type and the starting column address, as shown in Burst Definitionon Table  
Rev. 0.0/Feb. 2003  
20  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
CAS LATENCY  
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the  
availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.  
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident  
with clock edge n + m.  
Reserved states should not be used as unknown operation or incompatibility with future versions may result.  
DLL RESET  
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-  
ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically  
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any  
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally  
applied clock before an any command can be issued.  
OUTPUT DRIVER IMPEDANCE CONTROL  
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver  
option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will  
reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver  
and the half strength driver are included in this document.  
Rev. 0.0/Feb. 2003  
21  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
EXTENDED MODE REGISTER SET (EMRS)  
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-  
tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits  
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)  
and will retain the stored information until it is programmed again or the device loses power.  
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller  
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will  
result in unspecified operation.  
BA1 BA0 A12 A11 A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
DS  
A0  
0
1
RFU*  
0**  
DLL  
A0  
DLL enable  
Enable  
BA0  
0
MRS Type  
MRS  
0
1
Diable  
1
EMRS  
A1  
Output Driver  
Impedance Control  
Full Strength Driver  
Half Strength Driver  
0
1
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage  
** This part do not support /QFC function, A2 must be programmed to Zero.  
Rev. 0.0/Feb. 2003  
22  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Ambient Temperature  
Storage Temperature  
Symbol  
TA  
Rating  
0 ~ 70  
Unit  
oC  
oC  
V
TSTG  
-55 ~ 125  
Voltage on Any Pin relative to VSS  
Voltage on VDD relative to VSS  
Voltage on VDDQ relative to VSS  
Output Short Circuit Current  
Power Dissipation  
VIN, VOUT  
VDD  
-0.5 ~ 3.6  
-0.5 ~ 3.6  
-0.5 ~ 3.6  
50  
V
VDDQ  
IOS  
V
mA  
W
PD  
1
oC Þ sec  
Soldering Temperature Þ Time  
TSOLDER  
260 Þ 10  
Note : Operation at above absolute maximum rating can adversely affect device reliability  
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min  
Typ.  
Max  
Unit  
Note  
Power Supply Voltage  
Power Supply Voltage  
Input High Voltage  
Input Low Voltage  
Termination Voltage  
Reference Voltage  
VDD  
VDDQ  
VIH  
2.5  
2.5  
2.6  
2.7  
V
V
V
V
V
V
2.6  
2.7  
1
2
3
VREF + 0.15  
-0.3  
-
-
VDDQ + 0.3  
VREF - 0.15  
VREF + 0.04  
0.51*VDDQ  
VIL  
VTT  
VREF - 0.04  
0.49*VDDQ  
VREF  
VREF  
0.5*VDDQ  
Note :  
1. VDDQ must not exceed the level of VDD.  
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.  
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.  
Peak to peak noise on VREF may not exceed +/- 2% of the DC value.  
DC CHARACTERISTICS I (TA=0 to 70 oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min.  
Max  
Unit  
Note  
Input Leakage Current  
Output Leakage Current  
Output High Voltage  
Output Low Voltage  
ILI  
ILO  
-2  
2
uA  
uA  
V
1
-5  
5
2
VOH  
VOL  
VTT + 0.76  
-
-
IOH = -15.2mA  
IOL = +15.2mA  
VTT - 0.76  
V
Note : 1. VIN = 0 to 2.7V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V  
Rev. 0.0/Feb. 2003  
23  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)  
128Mx4  
Speed  
Parameter  
Operating Current  
Operating Current  
Symbol  
IDD0  
Test Condition  
Unit Note  
-D4 -D43  
One bank; Active - Precharge ; tRC=tRC(min);  
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice  
per clock cycle; address and control inputs changing  
once per clock cycle  
150  
200  
mA  
mA  
One bank; Active - Read - Precharge;  
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address  
and control inputs changing once per clock cycle  
IDD1  
Precharge Power Down  
Standby Current  
All banks idle; Power down mode; CKE=Low,  
tCK=tCK(min)  
IDD2P  
IDD2N  
10  
35  
mA  
mA  
Idle Standby Current  
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM  
/CS=High, All banks idle; tCK=tCK(min);  
CKE=High; address and control inputs changing once per  
clock cycle.  
Idle Standby Current  
IDD2F  
35  
mA  
VIN=VREF for DQ, DQS and DM  
/CS>=Vih(min); All banks idle; CKE>=Vih(min);  
Addresses and other control inputs stable, Vin=Vref for  
DQ, DQS and DM  
Idle Quiet Standby Current  
IDD2Q  
IDD3P  
25  
12  
mA  
mA  
Active Power Down  
Standby Current  
One bank active; Power down mode; CKE=Low,  
tCK=tCK(min)  
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;  
tRC=tRAS(max); tCK=tCK(min);  
Active Standby Current  
IDD3N  
DQ, DM and DQS inputs changing twice per clock cycle;  
Address and other control inputs changing once per  
clock cycle  
50  
mA  
Burst=2; Reads; Continuous burst; One bank active;  
Address and control inputs changing once per clock  
cycle; tCK=tCK(min); IOUT=0mA  
Operating Current  
Operating Current  
IDD4R  
IDD4W  
270  
270  
Burst=2; Writes; Continuous burst; One bank active;  
Address and control inputs changing once per clock  
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing  
twice per clock cycle  
mA  
Auto Refresh Current  
Self Refresh Current  
IDD5  
IDD6  
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz  
300  
5
Normal  
mA  
mA  
CKE =< 0.2V; External clock on;  
tCK=tCK(min)  
Low Power  
2.5  
Operating Current - Four  
Bank Operation  
Four bank interleaving with BL=4, Refer to the following  
page for detailed test condition  
IDD7  
540  
540  
mA  
4banks active read with activate every 20ns, AP(Auto  
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0  
mA, 100% DQ, DM and DQS inputs changing twice per  
clock cycle; 100% addresses changing once per clock  
cycle  
Random Read Current  
IDD7A  
mA  
Rev. 0.0/Feb. 2003  
24  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)  
64Mx8  
Speed  
Parameter  
Operating Current  
Operating Current  
Symbol  
IDD0  
Test Condition  
Unit Note  
-D4  
-D43  
One bank; Active - Precharge ; tRC=tRC(min);  
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per  
clock cycle; address and control inputs changing once per  
clock cycle  
150  
200  
mA  
mA  
One bank; Active - Read - Precharge;  
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address  
and control inputs changing once per clock cycle  
IDD1  
Precharge Power  
Down Standby  
Current  
All banks idle; Power down mode; CKE=Low,  
tCK=tCK(min)  
IDD2P  
IDD2N  
10  
35  
mA  
mA  
Idle Standby Current  
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM  
/CS=High, All banks idle; tCK=tCK(min);  
CKE=High; address and control inputs changing once per  
clock cycle.  
Idle Standby Current  
IDD2F  
35  
mA  
VIN=VREF for DQ, DQS and DM  
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses  
and other control inputs stable, Vin=Vref for DQ, DQS and  
DM  
Idle Quiet Standby  
Current  
IDD2Q  
IDD3P  
25  
12  
mA  
mA  
Active Power Down  
Standby Current  
One bank active; Power down mode; CKE=Low,  
tCK=tCK(min)  
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;  
tRC=tRAS(max); tCK=tCK(min);  
DQ, DM and DQS inputs changing twice per clock cycle;  
Address and other control inputs changing once per clock  
cycle  
Active Standby  
Current  
IDD3N  
50  
mA  
Burst=2; Reads; Continuous burst; One bank active;  
Address and control inputs changing once per clock cycle;  
tCK=tCK(min); IOUT=0mA  
Operating Current  
Operating Current  
IDD4R  
IDD4W  
280  
280  
Burst=2; Writes; Continuous burst; One bank active;  
Address and control inputs changing once per clock cycle;  
tCK=tCK(min); DQ, DM and DQS inputs changing twice per  
clock cycle  
mA  
Auto Refresh Current  
Self Refresh Current  
IDD5  
IDD6  
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz  
300  
5
Normal  
mA  
mA  
CKE =< 0.2V; External clock on;  
tCK=tCK(min)  
Low Power  
2.5  
Operating Current -  
Four Bank Operation  
Four bank interleaving with BL=4, Refer to the following  
page for detailed test condition  
IDD7  
540  
mA  
4banks active read with activate every 20ns, AP(Auto  
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,  
100% DQ, DM and DQS inputs changing twice per clock  
cycle; 100% addresses changing once per clock cycle  
Random Read  
Current  
IDD7A  
540  
mA  
Rev. 0.0/Feb. 2003  
25  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)  
32Mx16  
Speed  
Parameter  
Operating Current  
Operating Current  
Symbol  
IDD0  
Test Condition  
Unit Note  
-D4  
-D43  
One bank; Active - Precharge ; tRC=tRC(min);  
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per  
clock cycle; address and control inputs changing once per  
clock cycle  
150  
200  
mA  
mA  
One bank; Active - Read - Precharge;  
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address  
and control inputs changing once per clock cycle  
IDD1  
Precharge Power  
Down Standby  
Current  
All banks idle; Power down mode; CKE=Low,  
tCK=tCK(min)  
IDD2P  
IDD2N  
10  
35  
mA  
mA  
Idle Standby Current  
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM  
/CS=High, All banks idle; tCK=tCK(min);  
CKE=High; address and control inputs changing once per  
clock cycle.  
Idle Standby Current  
IDD2F  
35  
mA  
VIN=VREF for DQ, DQS and DM  
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses  
and other control inputs stable, Vin=Vref for DQ, DQS and  
DM  
Idle Quiet Standby  
Current  
IDD2Q  
IDD3P  
25  
12  
mA  
mA  
Active Power Down  
Standby Current  
One bank active; Power down mode; CKE=Low,  
tCK=tCK(min)  
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;  
tRC=tRAS(max); tCK=tCK(min);  
DQ, DM and DQS inputs changing twice per clock cycle;  
Address and other control inputs changing once per clock  
cycle  
Active Standby  
Current  
IDD3N  
50  
mA  
Burst=2; Reads; Continuous burst; One bank active;  
Address and control inputs changing once per clock cycle;  
tCK=tCK(min); IOUT=0mA  
Operating Current  
Operating Current  
IDD4R  
IDD4W  
280  
330  
Burst=2; Writes; Continuous burst; One bank active;  
Address and control inputs changing once per clock cycle;  
tCK=tCK(min); DQ, DM and DQS inputs changing twice per  
clock cycle  
mA  
Auto Refresh Current  
Self Refresh Current  
IDD5  
IDD6  
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz  
300  
5
Normal  
mA  
mA  
CKE =< 0.2V; External clock on;  
tCK=tCK(min)  
Low Power  
2.5  
Operating Current -  
Four Bank Operation  
Four bank interleaving with BL=4, Refer to the following  
page for detailed test condition  
IDD7  
540  
mA  
4banks active read with activate every 20ns, AP(Auto  
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,  
100% DQ, DM and DQS inputs changing twice per clock  
cycle; 100% addresses changing once per clock cycle  
Random Read  
Current  
IDD7A  
540  
mA  
Rev. 0.0/Feb. 2003  
26  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7  
IDD1 : Operating current: One bank operation  
1. Typical Case : VDD = 2.6V, T=25 oC  
2. Worst Case : VDD = 2.7V, T= 0 oC  
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are  
changing once per clock cycle. lout = 0mA  
4. Timing patterns  
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK  
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random add  
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP  
IDD7 : Operating current: Four bank operation  
1. Typical Case : VDD = 2.6V, T=25 oC  
2. Worst Case : VDD = 2.7V, T= 0 oC  
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not  
changing. lout = 0mA  
4. Timing patterns  
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge  
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing  
50% of data changing at every burst  
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP  
Rev. 0.0/Feb. 2003  
27  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min  
Max  
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals  
Input Differential Voltage, CK and /CK inputs  
VIH(AC)  
VIL(AC)  
VID(AC)  
VIX(AC)  
VREF + 0.31  
V
V
V
V
VREF - 0.31  
VDDQ + 0.6  
0.7  
1
2
Input Crossing Point Voltage, CK and /CK inputs  
0.5*VDDQ-0.2  
0.5*VDDQ+0.2  
Note :  
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.  
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.  
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Parameter  
Value  
Unit  
Reference Voltage  
Termination Voltage  
VDDQ x 0.5  
V
V
VDDQ x 0.5  
AC Input High Level Voltage (VIH, min)  
AC Input Low Level Voltage (VIL, max)  
Input Timing Measurement Reference Level Voltage  
Output Timing Measurement Reference Level Voltage  
Input Signal maximum peak swing  
VREF + 0.31  
V
VREF - 0.31  
V
VREF  
VTT  
1.5  
1
V
V
V
Input minimum Signal Slew Rate  
V/ns  
W
W
pF  
Termination Resistor (RT)  
50  
Series Resistor (RS)  
25  
Output Load Capacitance for Access Time Measurement (CL)  
30  
Rev. 0.0/Feb. 2003  
28  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)  
DDR400 (D4)  
DDR400 (D43)  
Parameter  
Symbol  
Unit  
Note  
Min  
60  
Max  
Min  
55  
Max  
Row Cycle Time  
tRC  
tRFC  
tRAS  
-
-
-
-
ns  
ns  
ns  
Auto Refresh Row Cycle Time  
Row Active Time  
70  
70  
40  
70K  
40  
70K  
tRCD or  
tRASmin  
tRCD or  
tRASmin  
Active to Read with Auto Precharge Delay  
tRAP  
-
-
ns  
16  
Row Address to Column Address Delay  
Row Active to Row Active Delay  
Column Address to Column Address Delay  
Row Precharge Time  
tRCD  
tRRD  
tCCD  
tRP  
18  
10  
1
-
-
-
-
-
-
15  
10  
1
-
-
-
-
-
-
ns  
ns  
CK  
ns  
ns  
CK  
18  
15  
2
15  
15  
2
Write Recovery Time  
tWR  
Internal Write to Read Command Delay  
tWTR  
(tWR/tCK)  
+
(tRP/tCK)  
(tWR/tCK)  
+
(tRP/tCK)  
Auto Precharge Write Recovery + Precharge Time  
tDAL  
-
-
CK  
15  
System Clock Cycle Time  
CL = 3  
tCK  
tCH  
5
10  
5
10  
ns  
CK  
CK  
ns  
ns  
ns  
Clock High Level Width  
0.45  
0.45  
-0.7  
-0.55  
-
0.55  
0.55  
0.7  
0.45  
0.45  
-0.7  
-0.55  
-
0.55  
0.55  
0.7  
Clock Low Level Width  
tCL  
Data-Out edge to Clock edge Skew  
DQS-Out edge to Clock edge Skew  
DQS-Out edge to Data-Out edge Skew  
tAC  
tDQSCK  
tDQSQ  
0.55  
0.4  
0.55  
0.4  
tHP  
-tQHS  
tHP  
-tQHS  
Data-Out hold time from DQS  
tQH  
tHP  
-
-
-
-
ns  
ns  
1,10  
min  
(tCL,tCH)  
min  
(tCL,tCH)  
Clock Half Period  
1,9  
10  
Data Hold Skew Factor  
tQHS  
tHZ  
tLZ  
tIS  
-
0.5  
-
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Data-out high-impedance window from CK,/CK  
Data-out low-impedance window from CK, /CK  
Input Setup Time (fast slew rate)  
tAC(Max)  
tAC(Max)  
17  
-0.7  
0.6  
0.6  
0.7  
0.7  
0.7  
-0.7  
0.6  
0.6  
0.7  
0.7  
0.7  
-
-
-
-
-
-
-
-
2,3,5,6  
2,4,5,6  
Input Hold Time (fast slew rate)  
tIH  
tIS  
Input Setup Time (slow slew rate)  
Input Hold Time (slow slew rate)  
tIH  
Rev. 0.0/Feb. 2003  
29  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
-Continue-  
DDR400 (D4)  
DDR400 (D43)  
Parameter  
Symbol  
Unit  
Note  
Min  
2.2  
0.35  
0.35  
0.72  
0.2  
0.2  
0.4  
0.4  
1.75  
0.9  
0.4  
0
Max  
Min  
2.2  
0.35  
0.35  
0.72  
0.2  
0.2  
0.4  
0.4  
1.75  
0.9  
0.4  
0
Max  
Input Pulse Width  
tIPW  
tDQSH  
tDQSL  
tDQSS  
tDSS  
-
-
ns  
CK  
CK  
CK  
CK  
CK  
ns  
6
Write DQS High Level Width  
-
-
-
-
Write DQS Low Level Width  
Clock to First Rising edge of DQS-In  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Data-In Setup Time to DQS-In (DQ & DM)  
Data-in Hold Time to DQS-In (DQ & DM)  
DQ & DM Input Pulse Width  
1.28  
1.28  
tDSH  
tDS  
-
-
-
-
6,7,11  
,
12,13  
tDH  
ns  
tDIPW  
tRPRE  
tRPST  
tWPRES  
tWPREH  
tWPST  
tMRD  
tXSC  
-
-
ns  
6
Read DQS Preamble Time  
1.1  
0.6  
-
1.1  
0.6  
-
CK  
CK  
CK  
CK  
CK  
CK  
CK  
us  
Read DQS Postamble Time  
Write DQS Preamble Setup Time  
Write DQS Preamble Hold Time  
Write DQS Postamble Time  
0.25  
0.4  
2
-
0.25  
0.4  
2
-
0.6  
-
0.6  
-
Mode Register Set Delay  
Exit Self Refresh to Any Execute Command  
Average Periodic Refresh Interval  
200  
-
-
200  
-
-
8
tREFI  
7.8  
7.8  
Note :  
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.  
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.  
3. For command/address input slew rate >=1.0V/ns  
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns  
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.  
Input Setup / Hold Slew-rate Derating Table.  
Input Setup / Hold Slew-rate  
Delta tIS  
ps  
Delta tIH  
V/ns  
0.5  
ps  
0
0
0.4  
+50  
+100  
0
0.3  
0
Rev. 0.0/Feb. 2003  
30  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
5. CK, /CK slew rates are >=1.0V/ns  
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by  
design or tester correlation.  
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.  
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete  
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.  
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this  
value can be greater than the minimum specification limits for tCL and tCH).  
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of  
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to  
n-channel variation of the output drivers.  
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.  
Input Setup / Hold Slew-rate Derating Table.  
Input Setup / Hold Slew-rate  
Delta tDS  
ps  
Delta tDH  
V/ns  
0.5  
ps  
0
0
0.4  
+75  
+150  
+75  
+150  
0.3  
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF  
+/-310mV for a duration of up to 2ns.  
I/O Input Level  
Delta tDS  
ps  
Delta tDH  
ps  
mV  
+280  
+50  
+50  
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and  
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 =  
0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.  
(1/SlewRate1)-(1/SlewRate2)  
Delta tDS  
ps  
Delta tDH  
ns/V  
0
ps  
0
0
+/-0.25  
+/- 0.5  
+50  
+100  
+50  
+100  
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-  
sitions through the DC region must be monotonic.  
15. tDAL = 2 clocks + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.  
tCK is equal to the actual system clock cycle time.  
Example: For DDR400(D4) at CL=3 and tCK = 5 ns,  
tDAL = (15 ns / 5ns) + (18 ns / 5 ns) = (3.0) + (3.6)  
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 7 clocks  
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x  
tCK.  
Rev. 0.0/Feb. 2003  
31  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
CAPACITANCE (TA=25oC, f=100MHz )  
Parameter  
Pin  
Symbol  
Min  
Max  
Unit  
Input Clock Capacitance  
Delta Input Clock Capacitance  
Input Capacitance  
CK, /CK  
CK, /CK  
CI1  
Delta CI1  
CI1  
2.0  
-
3.0  
0.25  
3.0  
0.5  
5.0  
0.5  
pF  
pF  
pF  
pF  
pF  
pF  
All other input-only pins  
All other input-only pins  
DQ, DQS, DM  
2.0  
-
Delta Input Capacitance  
Input / Output Capacitanc  
Delta Input / Output Capacitance  
Delta CI2  
CIO  
4.0  
-
DQ, DQS, DM  
Delta CIO  
Note :  
1. VDD = min. to max., VDDQ = 2.5V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V  
2. Pins not under test are tied to GND.  
3. These values are guaranteed by design and are tested on a sample basis only.  
OUTPUT LOAD CIRCUIT  
VTT  
RT=50Ω  
Output  
Zo=50Ω  
VREF  
CL=30pF  
Rev. 0.0/Feb. 2003  
32  
HY5DU12422A(L)T  
HY5DU12822A(L)T  
HY5DU121622A(L)T  
PACKAGE INFORMATION  
400mil 66pin Thin Small Outline Package  
Unit : mm(Inch)  
11.94 (0.470)  
11.79 (0.462)  
10.26 (0.404)  
10.05 (0.396)  
BASE PLANE  
22.33 (0.879)  
22.12 (0.871)  
0 ~ 5 Deg.  
0.35 (0.0138)  
0.65 (0.0256) BSC  
0.25 (0.0098)  
SEATING PLANE  
1.194 (0.0470)  
0.991 (0.0390)  
0.15 (0.0059)  
0.05 (0.0020)  
0.597 (0.0235)  
0.406 (0.0160)  
0.210 (0.0083)  
0.120 (0.0047)  
Rev. 0.0/Feb. 2003  
33  

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