HY5DU1298022TC-80 [HYNIX]
DDR DRAM, 16MX8, 1.5ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66;型号: | HY5DU1298022TC-80 |
厂家: | HYNIX SEMICONDUCTOR |
描述: | DDR DRAM, 16MX8, 1.5ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 动态存储器 双倍数据速率 光电二极管 |
文件: | 总19页 (文件大小:154K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
* The contents of this document are subject to change without notice
DATA SHEET
HY5DU1294022-75/80/10
HY5DU1298022-75/80/10
HY5DU1291622-75/80/10
HY5DV1294022-75/80/10
HY5DV1298022-75/80/10
HY5DV1291622-75/80/10
Sep., 98
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
DESCRIPTION
HY5DU(V)1294022-75/80/10, HY5DU(V)1298022-75/80/10 and HY5DU(V)1291623-75/80/10 are high speed
2.5V(U-part) and 3.3V(V-part) (I/O VDDQ=2.5V for all U,V-parts) 128M Double Data Rate(DDR) Synchronous
DRAM’s fabricated with the Hyundai high performance CMOS process. While all address and control inputs
are latched on the rising edge of the clock(falling edge of the /clock), data, data strobe and data mask inputs
are sampled on both rising and falling edge of the clock. The data path is internally pipelined and 2-bit pre-
fetched to achieve higher bandwidth. Because data rate is doubled through reading and writing at both rising
and falling edge of the clock, 2X higher data bandwidth can be achieved.
FEATURES
- 2.5V VDD(U-part), 3.3V VDD(V-part) and 2.5V VDDQ power supply for both parts
- Internal 4 banks with single pulsed RAS
- Fully differential clock operation with clock frequency 100MHz/125MHz/133MHz
- Data output on data strobe(DQS) edge when read (edged DQ)
- Data input on data strobe(DQS) center when write (centered DQ)
- Data strobe synchronized with output data for read and input data for write
- Programmable CAS latency 2.0/2.5/3.0 supported
- Programmable burst length 2/4/8 with both sequential and interleave mode
- Delay Locked Loop(DLL) installed with DLL reset mode
- SSTL_2 interface for all inputs and outputs
- Write mask byte control with LDM and UDM
- Bytewide data strobe with LDQS and UDQS
- Auto refresh and self refresh supported
- 4K/64ms refresh cycle
- 400mil 66 pin 0.65mm pin pitch TSOP-II package
BLOCK DIAGRAM (x16)
16
Write Data Register
2-bit Prefetch Unit
DS
32
CLK
/CLK
2M x 16/ Bank 0
2M x 16/ Bank 1
2M x 16/ Bank 2
2M x 16/ Bank 3
Bank
Control
CKE
/CS
Command
Decoder
32
16
/RAS
/CAS
DQ[0:15]
DQS
/WE
DM
Row
Decoder
Mode
Register
Column Decoder
CLK_DLL
A0-11
BA0-1
DLL
Block
Address
Buffer
Data Strobe
Transmitter
Column Address
Counter
CLK
DS
Data Strobe
Receiver
Mode Register
Sep., 98
page 1 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
ORDERING INFORMATION
HY 5D U 129 40 2 2 L TC - 10
HYUNDAI
SPEED
Memory Products
75 - 7.5ns(133MHz)
80 - 8ns(125MHz)
10 - 10ns(100MHz)
12 - 12ns(83MHz)
15 - 15ns(66MHz)
10P - PC/100, CL=2/3
10S - PC/100, CL=2
PRODUCT GROUP
55 - FP DRAM
56 - EDO DRAM
57 - SDRAM
5D - DDR SDRAM
PROCESS & POWER SUPPLY
PACKAGE
BLANK - CMOS 5.0V VDD
JC - 400mil SOJ
V
U
- CMOS 3.3V VDD
- CMOS 2.5V VDD
TC - 400mil TSOP-II
POWER CONSUMPTION
BLANK - Normal
DENSITY & REFRESH CYCLE
L
- Low power
64 - 64M bits, 8K refresh
65 - 64M bits, 4K refresh
128 - 128M bits, 8K refresh
129 - 128M bits, 4K refresh
DIE GENERATION
BLANK - 1st Gen.
DATA WIDTH
A
B
C
- 2nd Gen.
- 3rd Gen.
- 4th Gen.
40 - x4
80 - x8
16 - x16
32 - x32
INTERFACE
0 - LVTTL
1 - SSTL-3
NUMBER OF BANKS
1 - 2 banks
2 - 4 banks
2 - SSTL-2
3 - Mixed Interface
Sep., 98
page 2 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
PIN CONFIGURATION & DESCRIPTION
x4
x8
x16
VDD
NC
VDD
DQ0
VDDQ
NC
VDD
DQ0
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQ7
VSSQ
NC
VSS
NC
2
TOP VIEW
VDDQ
NC
VDDQ
DQ1
3
VSSQ
NC
4
DQ0
VSSQ
NC
DQ1
VSSQ
NC
DQ2
5
DQ6
VDDQ
NC
DQ3
VDDQ
NC
VSSQ
DQ3
6
7
NC
DQ2
VDDQ
NC
DQ4
8
DQ5
VSSQ
NC
NC
VDDQ
NC
VDDQ
DQ5
9
VSSQ
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DQ1
VSSQ
NC
DQ3
VSSQ
NC
DQ6
DQ4
VDDQ
NC
DQ2
VDDQ
NC
400mil X 875mil
66 Pin TSOP-II
VSSQ
DQ7
NC
NC
NC
NC
NC
VDDQ
NC
VDDQ
NC
VDDQ
LDQS
NC
VSSQ
UDQS
NC
VSSQ
DQS
NC
VSSQ
DQS
NC
Pin Pitch = 0.65mm
NC
NC
VDD
VDD
VDD
VREF
VSS
UDM
/CLK
CLK
CKE
NC
VREF
VSS
DM
VREF
VSS
DM
NC, /QFC NC, /QFC NC, /QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
/CLK
CLK
CKE
NC
/CLK
CLK
CKE
NC
NC
NC
NC
A11
A11
A9
A11
A9
A9
A10/AP A10/AP A10/AP
A8
A8
A8
A0
A1
A0
A1
A0
A1
A7
A7
A7
A6
A6
A6
( Normal Bend )
A2
A2
A2
A5
A5
A5
A3
A3
A3
A4
A4
A4
VDD
VDD
VDD
VSS
VSS
VSS
Pin
A0 - A11
BA0, BA1
DQ0 - DQ15
/CS
Description
Row / Column Address
Bank Select Address
Data Input/Output
Chip Select
/RAS
Row Address Strobe
Column Address Strobe
Write Enable
/CAS
/WE
LDM, UDM
CLK, /CLK
CKE
Write Mask(Lower/Upper Byte)
Clock Input
Clock Enable
LDQS, UDQS
VREF
Data Strobe(Lower/Upper Byte)
Reference Voltage
Power, Ground
VDD, VSS
VDDQ, VSSQ
/QFC
I/O Power, I/O Ground
DQ FET Switch Control(optional)
No Connection
NC
Sep., 98
page 3 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
ADDRESS MAPPING TABLE
Column Address
A0~A9, A11
A0~A9
Organization
Bank Select
BA0, BA1
Row Address
A0 ~ A11
Autoprecharge
x4
x8
A10
A10
A10
A0 ~ A11
BA0, BA1
x16
BA0, BA1
A0 ~ A11
A0~A8
COMMAND TRUTH TABLE
CKEn-1 CKEn
Function
Device Deselect
No Operation
Symbol
/CS /RAS /CAS /WE A11 A10 BA A9-0
DSEL
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
L
L
L
L
L
L
L
L
L
H
X
H
L
X
H
H
H
H
H
L
X
H
L
X
H
H
H
L
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
L
X
X
L
X
X
V
V
V
V
V
V
X
X
X
X
X
X
X
V
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
V
NOP
Read
READ
Read w/ Autoprecharge
Write
READAP
WRITE
WRITEAP
ACT
L
H
L
L
Write w/ Autoprecharge
Bank Activate
L
L
H
V
L
H
H
H
H
L
H
L
Precharge Selected Bank PRE
L
Precharge All Banks
Read Burst Stop
Auto Refresh
PALL
BST
L
L
H
X
X
X
X
X
X
L
H
L
L
AREF
SREF
SREX
PDEN
PDEX
MRS
H
H
X
X
X
L
Self Refresh Entry
Self Refresh Exit
Power Down Entry
Power Down Exit
Mode Register Set
L
L
H
L
X
X
X
L
X
X
X
L
H
L
H
X
H
WRITE DATA MASK TRUTH TABLE
Function
CKEn-1
CKEn
UDM
LDM
Data Write/Output Enable
H
H
H
H
X
X
X
X
L
H
L
L
H
H
L
Data Mask/Output Disable
Upper Byte Write Enable / Lower Byte Mask
Lower Byte Write Enable / Upper Byte Mask
H
Notes : ‘H’ - Logic High Level, ‘L’ - Logic Low Level, ‘X’ - Don’t Care, ‘V’ - Valid Data Input
Sep., 98
page 4 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
OPERATION COMMAND TRUTH TABLE
Current State
/CS /RAS /CAS /WE
Address
Command
Action
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSEL
NOP or power down 3
X
X
NOP
BST
NOP or power down 3
ILLEGAL4
H
L
BA, CA, A10
READ/READAP
ILLEGAL4
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL4
IDLE
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
Row Activation
L
BA, A10
NOP
L
H
L
X
Auto Refresh or Self Refresh 5
Mode Register Set
NOP
L
L
OPCODE
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSEL
X
X
NOP
NOP
BST
ILLEGAL4
H
L
BA, CA, A10
READ/READAP
Begin read : optional AP 6
ROW
ACTIVE
L
BA, CA, A10 WRITE/WRITEAP Begin write : optional AP 6
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4
L
BA, A10
Precharge 7
L
H
L
X
ILLEGAL11
L
L
OPCODE
ILLEGAL11
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSEL
Continue burst to end
Continue burst to end
Terminate burst
Term burst, new read:optional AP 8
X
X
NOP
BST
H
L
BA, CA, A10
READ/READAP
READ
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4
L
BA, A10
Term burst, precharge
ILLEGAL11
L
H
L
X
L
L
OPCODE
ILLEGAL11
X
H
H
H
H
X
H
H
L
X
H
L
X
DSEL
Continue burst to end
Continue burst to end
ILLEGAL4
X
X
NOP
WRITE
BST
H
L
BA, CA, A10
READ/READAP
Term burst, new read:optional AP 8
L
BA, CA, A10 WRITE/WRITEAP Term burst, new write:optional AP
Sep., 98
page 5 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
OPERATION COMMAND TRUTH TABLE
Current State
/CS /RAS /CAS /WE
Address
BA, RA
Command
ACT
Action
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
ILLEGAL4
BA, A10
PRE/PALL
Term burst, precharge
ILLEGAL11
WRITE
L
H
L
X
AREF/SREF
MRS
L
L
OPCODE
ILLEGAL11
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSEL
Continue burst to end
Continue burst to end
ILLEGAL
X
X
NOP
BST
H
L
BA, CA, A10
READ/READAP
ILLEGAL10
READ
WITH
AUTOPRE-
CHARGE
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL10
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4,10
L
BA, A10
ILLEGAL4,10
L
H
L
X
ILLEGAL11
L
L
OPCODE
ILLEGAL11
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSEL
Continue burst to end
Continue burst to end
ILLEGAL
X
X
NOP
BST
H
L
BA, CA, A10
READ/READAP
ILLEGAL10
WRITE
WITH
AUTOPRE-
CHARGE
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL10
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4,10
L
BA, A10
ILLEGAL4,10
L
H
L
X
ILLEGAL11
L
L
OPCODE
ILLEGAL11
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSEL
NOP - Enter IDLE after tRP
NOP - Enter IDLE after tRP
ILLEGAL4
X
X
NOP
BST
H
L
BA, CA, A10
READ/READAP
ILLEGAL4,10
PRE-
CHARGE
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL4,10
H
H
L
H
L
BA, RA
BA, A10
X
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4,10
L
NOP - Enter IDLE after tRP
ILLEGAL11
L
H
L
L
L
OPCODE
ILLEGAL11
Sep., 98
page 6 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
OPERATION COMMAND TRUTH TABLE
Current State
/CS /RAS /CAS /WE
Address
Command
DSEL
Action
NOP - Enter ROW ACT after tRCD
NOP - Enter ROW ACT after tRCD
ILLEGAL4
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
NOP
BST
H
L
BA, CA, A10 READ/READAP
ILLEGAL4,10
ROW
ACTIVAT-
ING
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL4,10
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4,9,10
L
BA, A10
ILLEGAL4,10
ILLEGAL11
L
H
L
X
L
L
OPCODE
ILLEGAL11
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DSEL
NOP - Enter ROW ACT after tDPL
NOP - Enter ROW ACT after tDPL
ILLEGAL4
NOP
BST
H
L
BA, CA, A10 READ/READAP
ILLEGAL
WRITE
RECOVER-
ING
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4,10
L
BA, A10
ILLEGAL4,11
L
H
L
X
ILLEGAL11
L
L
OPCODE
ILLEGAL11
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DSEL
NOP - Enter precharge after tDPL
NOP - Enter precharge after tDPL
ILLEGAL4
NOP
BST
WRITE
H
L
BA, CA, A10 READ/READAP
ILLEGAL4,8,10
RECOVER-
ING WITH
AUTOPRE-
CHARGE
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL4,10
H
H
L
H
L
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL4,10
L
BA, A10
ILLEGAL4,11
L
H
L
X
ILLEGAL11
ILLEGAL11
L
L
OPCODE
X
H
H
H
X
H
H
L
X
H
L
X
X
X
DSEL
NOP - Enter IDLE after tRC
NOP - Enter IDLE after tRC
ILLEGAL11
NOP
REFRESH-
ING
BST
H
BA, CA, A10 READ/READAP
ILLEGAL11
Sep., 98
page 7 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
OPERATION COMMAND TRUTH TABLE
Current State
/CS /RAS /CAS /WE
Address
Command
Action
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL11
BA, RA
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL11
ILLEGAL11
ILLEGAL11
ILLEGAL11
REFRESH-
ING
L
BA, A10
L
H
L
X
L
L
OPCODE
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSEL
NOP - Enter IDLE after tMRD
NOP - Enter IDLE after tMRD
ILLEGAL11
X
X
NOP
BST
H
L
BA, CA, A10
READ/READAP
ILLEGAL11
MODE
REGISTER
ACCESSING
L
BA, CA, A10 WRITE/WRITEAP ILLEGAL11
H
H
L
H
L
BA, RA
BA, A10
X
ACT
PRE/PALL
AREF/SREF
MRS
ILLEGAL11
ILLEGAL11
ILLEGAL11
ILLEGAL11
L
L
H
L
L
L
OPCODE
Notes :
1. ‘H’ - Logic High Level, ‘L’ - Logic Low Level, ‘X’ - Don’t Care, ‘V’ - Valid Data Input, BA - Bank Address
AP - Auto Precharge, CA - Column Address, RA - Row Address, NOP - NO Operation
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA),
depending on the state of that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Sep., 98
page 8 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
CKE FUNCTION TRUTH TABLE
Current State CKEn-1 CKEn
/CAS
X
X
H
H
L
/CS /RAS
/WE ADD
Action
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit self refresh, enter idle after tSREX
Exit self refresh, enter idle after tSREX 3
ILLEGAL
L
SELF1
REFRESH
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
H
H
L
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
NOP, continue self refresh
INVALID
H
L
X
H
H
H
H
H
L
Exit power down, enter idle
Exit power down, enter idle
ILLEGAL
L
POWER2
DOWN
L
L
L
L
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
L
ILLEGAL
L
X
X
L
X
X
L
NOP, continue power down mode
See operation command truth table
Enter self refresh
Enter power down
Enter power down
ILLEGAL
H
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
L
X
H
H
L
L
ALL4
BANKS
IDLE
L
L
L
L
X
X
L
ILLEGAL
L
L
H
L
ILLEGAL
L
L
L
ILLEGAL
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
H
H
L
H
L
See operation command truth table
ILLEGAL5
Any State
other
than above
H
L
INVALID
L
INVALID
Notes :
When CKE=L, all DQ and DQS must be in Hi-Z state
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command
2. All command can be stored after 2 clocks from low to high transition of CKE
3. Illegal if CLK is suspended or stopped during the power down mode
4. Self refresh can be entered only from the all banks idle state
5. Disabling CLK may cause malfunction if any bank is in active state
Sep., 98
page 9 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
SIMPLIFIED STATE DIAGRAM
MRS
SREF
MODE
REGISTER
SET
SELF
REFRESH
IDLE
SREX
AREF
PDEN
PDEX
ACT
AUTO
REFRESH
POWER
DOWN
POWER
DOWN
PDEN
BST
PDEX
BANK
ACTIVE
READ
WRITE
READ
READAP
WRITEAP
WRITE
WITH
AUTOPRE-
CHARGE
READ
WITH
AUTOPRE-
CHARGE
READAP
READ
WRITE
WRITEAP
WRITE
PRE(PALL)
PRE(PALL)
PRE-
CHARGE
Command Input
Automatic Sequence
POWER
-UP
POWER APPLIED
Sep., 98
page 10 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
MODE REGISTER TABLE
The mode register of DDR SDRAM provides a variety of different options. The mode register can be pro-
grammed by the Mode Register Set(MRS) command. Once mode register field is determined, the informa-
tion will be held until resetted by another MRS command.
BA0
BA1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
RFU*
DR*
TM*
CAS Latency(CL)
BT*
Burst Length(BL)
*BT=Burst Type, TM=Test Mode, DR=DLL Reset, RFU=Reserved for Future Use
RFU Address fields (A11,A10, A9) must be “0” during MRS entry
A8
0
DLL Reset
No
A6
0
A5
A4
CAS Latency
Reserved
Reserved
2.0
A2
0
A1
0
A0 Sequential Interleave
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved Reserved
1
Yes
0
0
0
2
4
8
2
4
8
A7
0
Test Mode
0
0
1
Normal Operation
Test Mode Entry
0
3.0
0
1
1
1
Reserved
(1.5)
1
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
A3
0
Burst Type
Sequential
Interleave
1
1
0
1
2.5
1
1
1
Reserved
1
1
1
BURST SEQUENCE TABLE
The burst type can be determined either sequential or interleave by MRS command. DDR SDRAM provides
any starting address for bursting read and write data as SDR SDRAM.
Start Address
A0=0
Sequential
Interleave
0, 1
0,1
A0=1
1,0
1, 0
A1=0, A0=0
A1=0, A0=1
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
A1=1, A0=0
2, 3, 0, 1
2, 3, 0, 1
A1=1, A0=1
3, 0, 1, 2
3, 2, 1, 0
A2=0, A1=0, A0=0
A2=0, A1=0, A0=1
A2=0, A1=1, A0=0
A2=0, A1=1, A0=1
A2=1, A1=0, A0=0
A2=1, A1=0, A0=1
A2=1, A1=1, A0=0
A2=1, A1=1, A0=1
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Sep., 98
page 11 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
EXTENDED MODE REGISTER TABLE - refer to page 17 for details, field for BA=1 is still reserved
BA0
BA1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
RFU
QFC
ZO
DLL
A1
Output Impedance Control
Full SSTL_2 Class II Driver
Half SSTL_2 Class II Driver
A0
DLL ON/OFF
DLL Enable
DLL Disable
A2 DQ FET Switch Control
0
1
0
1
0
1
/QFC Disable
/QFC Enable
Output Impedance Control
Detailed requirements for half strength driver will be supplemented
DQ FET Switch Control
Detailed timing requirements will be supplemented
Sep., 98
page 12 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
TA
Parameters
Ambient temperature
Rating
0 ~ 70
Unit
oC
TSTG
Storage temperature
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-1.0 ~ 4.6
-0.5 ~ 3.6
50
oC
VIN, VOUT
VDD (U-part)
VDD (V-part)
VDDQ
Voltage on any pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output short circuit current
Power dissipation
Volts
Volts
Volts
Volts
mA
IOS
PD
1
W
TSOLDER
Soldering temperature X time
260 X10
oC X sec
Notes : Operation other than above table can adversely affect the device reliability
( TA = 0 to 70 oC)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Power supply voltage
Power supply voltage
Power supply voltage
Power supply voltage
Input DC low voltage
Input DC high voltage
Input AC low voltage
Input AC high voltage
Output low voltage
Output high voltage
Termination voltage
Reference voltage
Minimum
Typical
Maximum
Unit
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Ohms
Ohms
VDD (U-part)
3.0
3.3
3.6
VDD (V-part)
2.3
2.5
2.7
1
VDDQ
2.3
2.5
2.7
VSS, VSSQ
VIL(DC)2
VIH(DC)
VIL(AC)
0
0
0
-0.3
-
VREF - 0.18
VREF + 0.18
-
VDDQ + 0.3
-
-
-
VREF - 0.35
VIH(AC)
VREF + 0.35
-
3
VOL
-
-
VTT - 0.76
4
VOH
VTT + 0.76
-
-
VTT
VREF - 0.04
VREF
1.25
50
25
VREF + 0.04
5
VREF
1.15
1.35
RT
RS
Termination resistor
Series resistor
-
-
-
-
Notes : 1. VDDQ must not exceed the level of VDD
2. VIL,min (AC) = -1.5V (pulse width < 5ns)
3. IOL =15.2mA, 4. IOH = -15.2mA 5. The value of VREF is approximately equal to 0.5VDDQ
( TA = 25 oC, f = 1MHz)
CAPACITANCE
Symbol
Parameter
Pin
Min.
2.5
Max.
3.5
Unit
pF
CIN
CCLK
CIO
Input capacitance
Clock capacitance
I/O capacitance
Addresses, all inputs
CLK, /CLK
2.5
3.5
pF
DQ0 - DQ15, DQS, DM
4.0
5.5
pF
Sep., 98
page 13 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
DC CHARACTERISTICS
Symbol
ILI
Parameter
Test Condition
Maximum
Unit
uA
Vapplied=0 to 3.6V w/ all other pins=0V
Vapplied=0 to 2.7V w/ DOUT is disabled
Input leakage current
Output leakage current
5
5
ILO
uA
No CAS activity, 1 bank active
tRC=minimum cycle
Operating current
TBD
TBD
TBD
TBD
mA
mA
mA
mA
ICC1
ICC2N
ICC2P
ICC3N
Precharge standby current
( Non-power down mode )
CKE > VIH(min) in all banks idle state
tCK=minimum cycle
Precharge standby current
( Power down mode )
CKE < VIL(max) in all banks idle state
tCK=minimum cycle
Active standby current
( Non-power down mode )
CKE > VIH(min) in all banks active state
tCK=minimum cycle
Active standby current
( Power down mode )
CKE < VIL(max) in all banks active state
tCK=minimum cycle
TBD
TBD
TBD
TBD
mA
mA
mA
mA
ICC3P
Burst operating current
Refresh current
With CAS activity, tCK=minimum cycle
ICC4
ICC5
ICC6
tRC=minimum cycle
with auto refresh mode
Self refresh current
CKE < 0.2V at self refresh mode
AC CHARACTERISTICS I - TIMING
- 7.5
- 8
- 10
Symbol
Parameter
Unit
Min.
8
Max.
15
15
15
266
-
Min.
10
Max.
15
15
15
250
-
Min.
Max.
15
15
15
200
-
CL=2.0
CL=2.5
CL=3.0
10
8
ns
tCK
Clock cycle time
7.5
7.5
ns
ns
7.5
7.5
8
rD
tCH
Maximum data rate
Clock high level width
Clock low level width
-
-
-
Mb/s
tCK
tCK
tCK
tCK
tCK
tCK
ns
0.45
0.45
- 0.1
- 0.1
- 0.1
0.45
0.45
- 0.1
- 0.1
- 0.1
0.45
0.45
- 0.1
- 0.1
- 0.1
-
-
-
tCL
tAC
DQ edge to clock edge skew
DQS edge to clock edge skew
DQ edge to clock edge skew
DQS edge to DQ edge skew
DQ output Lo-Z to Hi-Z delay
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
tDQSCK
tDQCK
tDQSQ
tHZQ
- 0.075 0.075 - 0.075 0.075 - 0.075 0.075
-
3
-
3
-
4
Sep., 98
page 14 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
AC CHARACTERISTICS I - TIMING
- 7.5
- 8
- 10
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tDV
tDQSV
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tDQSS
tIS1
Data valid window
0.35
0.35
0.9
-
0.35
0.35
0.9
0.4
0
-
0.35
0.35
0.9
0.4
0
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
-
Data strobe valid window
Read DQS preamble time
Read DQS postamble time
Write DQS preamble setup time
Write DQS preamble hold time
DQS last falling edge to Hi-Z
CLK to first rising edge of DQS
Input setup time to clock
Input hold time to clock
-
-
1.1
1.1
1.1
0.4
0.6
0.6
0.6
0
-
-
-
0.25
0.4
-
0.25
0.4
0.75
0.15
0.15
0.075
0.075
0.075
0.075
1
-
0.25
0.4
0.75
0.15
0.15
0.075
0.075
0.075
0.075
1
-
0.6
0.6
0.6
0.75
0.15
0.15
1.25
1.25
1.25
-
-
-
tIH1
-
-
-
tDDQSS2
tDDQSH2
DQ setup time to DQS
0.075
0.075
0.075
0.075
1
-
-
-
DQ hold time to DQS
-
-
-
tDMDQSS2 DM setup time to DQS
tDMDQSH2 DM hold time to DQS
-
-
-
-
-
-
tDRL
tDPL
tRAS
tRP
Last data-in to read command
Last data-in to precharge
RAS active time
-
-
-
10
-
10
-
10
-
45
100K
48
100K
50
100K
ns
RAS precharge time
RAS cycle time
15
-
-
15
-
-
20
-
-
ns
tRC
60
63
70
ns
tRFC
tRCD
tRRD
tCCD
tMRD
tPDEX
tSREX
tT
Auto-refresh command cycle
RAS to CAS delay
75
-
80
-
80
-
ns
15/20
2
-
15/20
2
-
20
-
ns
RAS to RAS delay
-
-
2
-
tCK
tCK
tCK
ns
CAS to CAS delay
1
-
1
-
1
-
Mode register set delay
Power down exit time
Self-refresh exit time
Input transition time
Refresh time
2
-
2
-
2
-
10
-
10
-
10
-
200
0.5
-
-
200
0.5
-
-
200
0.5
-
-
ns
-
-
-
ns
tREF
64
64
64
ms
Notes :
1. Data sampled at the rising edge of the clock : Addresses, CKE, /CS, /RAS, /CAS, /WE
2. Data sampled at both the rising edge and falling edge of data strobe : DQ, DM
3. tRCD=15ns/20ns each one represents different parts
Sep., 98
page 15 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
AC CHARACTERISTICS II - TEST LOAD
(VDDQ=2.5V, TA = 0~70 oC)
Parameter
Reference voltage, VREF
Termination voltage, VTT
Timing measurement reference level
Input signal level
Condition
VDDQ x 0.5
VDDQ x 0.5
VREF
Unit
Volts
Volts
Volts
Volts
V/ns
0.4 / 2.4
1
Input signal slew rate
Output load
See test load circuits below
-
AC CHARACTERISTICS III - REFERENCE TEST LOAD CIRCUITS
VTT
VTT
DDR SDRAM
RT=50Ohms
RT
DUT
DQ
DQS
RS=25Ohms
Zo = 50Ohms
VREF
CL= 30pF
VDDQ
VDDQ
VREF
VREF
Sep., 98
page 16 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
AC CHARACTERISTICS IV - TIMING DIAGRAM
tCK
tCH
tCL
VREF
CLK
tCK/2
/CLK
tIS
tIH
Control &
Address
command
READ OPERATION
READ
tDQSCKmin
tDQSCKmax
VTT
DQS
(@ CL=2.0)
tRPRE
tACmin
tRPST
tQSV
tDQSQmin
VTT
Data
Output
tACmax
Don’t care
tDV
tDQSQmax
tIS
tIH
Control &
Address
command
WRITE OPERATION
WRITE
tDQSS
VTT
DQS
tWPRES
(@ tDQSS=tCK)
tWPREH
tWPST
tDQSV
tDDQSS
Data
Input
VTT
(DQ/DM)
Don’t care
tDDQSH
Notes : CAS Latency (CL) is defined as the number of ticks of clock from the rising edge of the
command CLK to the first edge of DQS which transits from low to high level.
Sep., 98
page 17 of 28
Rev. 0-A
Hyundai
Electronics
Industries
128M DDR SDRAM
PRELIMINARY
HYUNDAI 4 Banks X 8/4/2M X 4/8/16 bits DDR SDRAM
PACKAGE INFORMATION
Unit : mm(inch)
11.94 (0.470)
11.79 (0.462)
10.26 (0.404)
10.05 (0.396)
BASE PLANE
22.33 (0.879)
22.12 (0.871)
0.35 (0.0138)
0.25 (0.0098)
0.65 (0.0256) BSC
SEATING PLANE
1.194 (0.0470)
0.991 (0.0390)
0.15 (0.0059)
0.05 (0.0020)
Sep., 98
page 18 of 28
Rev. 0-A
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