HY5DU56822DLT-J_技术文档

HY5DU56422D(L)T

HY5DU56822D(L)T

HY5DU561622D(L)T

256Mb DDR SDRAM

HY5DU56422D(L)T

HY5DU56822D(L)T

HY5DU561622D(L)T

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Apr. 2006

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1HY5DU56422D(L)T

HY5DU56822D(L)T

HY5DU561622D(L)T

Revision History

Revision No.

History

Draft Date Remark

First Version Release - Merged HY5DU564(8,16)22D(L)T and

HY5DU564(8,16)22D(L)T-D into HY5DU564(8,16)22D(L)T.

1.0

Oct. 2004

1) Changed all notes in AC CHARACTERISTICS

2) Added ‘SYSTEM CHARACTERISTICS for DDR SDRAMS’

3) Editorial Changes

1.1

1.2

Feb. 2005

Apr. 2006

State Diagram modified

Rev. 1.2 /Apr. 2006

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1HY5DU56422D(L)T

HY5DU56822D(L)T

HY5DU561622D(L)T

DESCRIPTION

The HY5DU56422D(L)T, HY5DU56822D(L)T and HY5DU561622D(L)T are a 268,435,456-bit CMOS Double Data

Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density

and high bandwidth.

This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

FEATURES

•

All addresses and control inputs except data, data

strobes and data masks latched on the rising edges

of the clock

•

VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333

VDD, VDDQ = 2.6V ± 0.1V for DDR400

•

All inputs and outputs are compatible with SSTL_2

interface

•

Programmable CAS latency 2/2.5 (DDR200, 266,

333) and 3 (DDR400) supported

•

Fully differential clock inputs (CK, /CK) operation

Double data rate interface

Programmable burst length 2/4/8 with both sequen-

tial and interleave mode

Source synchronous - data transaction aligned to

bidirectional data strobe (DQS)

Internal four bank operations with single pulsed

/RAS

•

x16 device has two bytewide data strobes (UDQS,

LDQS) per each x8 I/O

•

Auto refresh and self refresh supported

tRAS lock out function supported

8192 refresh cycles / 64ms

Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

JEDEC standard 400mil 66pin TSOP-II with 0.65mm

pin pitch

•

On chip DLL align DQ and DQS transition with CK

transition

•

Full and Half strength driver option controlled by

EMRS

DM mask write data-in at the both rising and falling

edges of the data strobe

ORDERING INFORMATION

OPERATING FREQUENCY

Remark

(CL-tRCD-tRP)

Part No.

Configuration Package

Grade

Clock Rate

HY5DU56422D(L)T-X*

HY5DU56822D(L)T-X*

64M x 4

32M x 8

16M x 16

400mil

66pin

-D43

- J

200MHz@CL3

DDR400B (3-3-3)

133MHz@CL2 166MHz@CL2.5 DDR333 (2.5-3-3)

133MHz@CL2 133MHz@CL2.5 DDR266A (2-3-3)

100MHz@CL2 133MHz@CL2.5 DDR266B (2.5-3-3)

- K

HY5DU561622D(L)T-X*

TSOP-II

- H

- L

100MHz@CL2

DDR200 (2-2-2)

* X means speed grade

Rev. 1.2 /Apr. 2006

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HY5DU56822D(L)T

HY5DU561622D(L)T

PIN CONFIGURATION

x4

x8

x16

x8

x4

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

NC

VSSQ

UDQS

NC

VREF

VSS

UDM

/CK

CK

CKE

NC

A12

A11

A9

A8

A7

A6

VSS

DQ7

VSSQ

NC

DQ6

VDDQ

NC

DQ5

VSSQ

NC

DQ4

VDDQ

NC

1

2

3

4

5

6

7

8

9

VDD

NC

VDDQ

NC

DQ0

VSSQ

NC

VDDQ

NC

DQ1

VSSQ

NC

VDDQ

NC

VDD

NC

VDD

DQ0

VDDQ

NC

DQ1

VSSQ

NC

DQ2

VDDQ

NC

DQ3

VSSQ

NC

VDDQ

NC

VDD

NC

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

VDDQ

LDQS

NC

VDD

NC

LDM

/WE

/CAS

/RAS

/CS

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

VSS

NC

VSSQ

NC

DQ3

VDDQ

NC

VSSQ

NC

DQ2

VDDQ

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

NC

VSSQ

DQS

NC

VREF

VSS

DM

/CK

CK

CKE

NC

A12

A11

A9

A8

A7

400mil X 875mil

66pin TSOP -II

VSSQ

DQS

NC

VREF

VSS

DM

/CK

CK

CKE

NC

A12

A11

A9

A8

A7

0.65mm pin pitch

NC

/WE

/CAS

/RAS

/CS

/WE

/CAS

/RAS

/CS

NC

BA0

BA1

A10/AP

A0

A1

A2

A3

VDD

BA0

BA1

A10/AP

A0

A1

A2

A3

VDD

BA0

BA1

A10/AP

A0

A1

A2

A3

VDD

A6

A5

A4

VSS

A6

A5

A4

VSS

A5

A4

VSS

ROW AND COLUMN ADDRESS TABLE

ITEMS

64Mx4

32Mx8

16Mx16

Organization

Row Address

16M x 4 x 4banks

A0 - A12

A0-A9, A11

BA0, BA1

A10

8M x 8 x 4banks

A0 - A12

A0-A9

4M x 16 x 4banks

A0 - A12

A0-A8

Column Address

Bank Address

Auto Precharge Flag

Refresh

BA0, BA1

A10

BA0, BA1

A10

8K

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HY5DU56822D(L)T

HY5DU561622D(L)T

PIN DESCRIPTION

TYPE

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

Input

CK, /CK

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are dis-

abled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level

after VDD is applied.

CKE

Input

Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

/CS

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

BA0, BA1

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0 and

BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS

or EMRS).

A0 ~ A12

Input

Command Inputs:/ RAS, /CAS and /WE (along with /CS) define the command being

entered.

Input

/RAS, /CAS ,/WE

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM

is sampled HIGH along with that input data during a WRITE access. DM is sampled on both

edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS

loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the

data on DQ8-Q15.

DM

(LDM,UDM)

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. For the x16, LDQS corresponds to the

data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.

DQS

(LDQS,UDQS)

I/O

DQ

VDD/VSS

VDDQ/VSSQ

VREF

I/O

Data input / output pin: Data bus

Supply

NC

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

NC

Rev. 1.2 /Apr. 2006

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HY5DU56822D(L)T

HY5DU561622D(L)T

FUNCTIONAL BLOCK DIAGRAM(64Mx4)

4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM

4

Write Data Register

2-bit Prefetch Unit

DQS

DM

8

Bank

Control

16Mx4 / Bank0

CLK

/CLK

CKE

/CS

/RAS

/CAS

/WE

16Mx4 / Bank1

16Mx4 / Bank2

16Mx4 / Bank3

8

4

Command

Decoder

DQ[0:3]

Mode

Register

Row

Decoder

Column Decoder

DQS

ADD

BA

Address

Buffer

Column Address

Counter

Data Strobe

Transmitter

CLK_DLL

Data Strobe

Receiver

DQS

CLK,

/CLK

DLL

Block

Mode

Register

Rev. 1.2 /Apr. 2006

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HY5DU56822D(L)T

HY5DU561622D(L)T

FUNCTIONAL BLOCK DIAGRAM (32Mx8)

4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM

8

Write Data Register

2-bit Prefetch Unit

DQS

DM

16

Bank

Control

8Mx8 / Bank0

8Mx8 / Bank1

8Mx8 / Bank2

8Mx8 / Bank3

CLK

/CLK

CKE

/CS

/RAS

/CAS

/WE

16

8

Command

Decoder

DQ[0:7]

Mode

Register

Row

Decoder

Column Decoder

DQS

ADD

BA

Address

Buffer

Column Address

Counter

Data Strobe

Transmitter

CLK_DLL

Data Strobe

Receiver

DQS

CLK,

/CLK

DLL

Block

Mode

Register

Rev. 1.2 /Apr. 2006

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HY5DU56822D(L)T

HY5DU561622D(L)T

FUNCTIONAL BLOCK DIAGRAM (16Mx16)

4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM

16

Write Data Register

2-bit Prefetch Unit

LDQS, UDQS

LDM, UDM

32

Bank

Control

4Mx16 / Bank0

CLK

/CLK

CKE

/CS

/RAS

/CAS

/WE

4Mx16 / Bank1

4Mx16 / Bank2

4Mx16 / Bank3

32

16

Command

Decoder

DQ[0:15]

Mode

Register

Row

Decoder

Column Decoder

LDQS, UDQS

ADD

BA

Address

Buffer

Column Address

Counter

Data Strobe

Transmitter

CLK_DLL

LDQS

UDQS

Data Strobe

Receiver

CLK,

/CLK

DLL

Block

Mode

Register

Rev. 1.2 /Apr. 2006

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SIMPLIFIED COMMAND TRUTH TABLE

A10/

AP

Command

CKEn-1 CKEn

CS

RAS

CAS

WE

ADDR

BA

Extended Mode Register Set^1,2

Mode Register Set^1,2

Device Deselect¹

H

X

L

OP code

H

L

X

H

L

X

H

X

H

X

No Operation¹

Bank Active¹

L

RA

V

Read¹

L

H

L

H

L

H

L

CA

X

Read with Autoprecharge^1,3

Write¹

H

X

V

Write with Autoprecharge^1,4

Precharge All Banks^1,5

Precharge selected Bank¹

Read Burst Stop¹

H

L

X

V

H

L

H

X

H

L

H

L

H

L

X

Auto Refresh¹

Entry

H

X

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

X

Self Refresh¹

Exit

Entry

Exit

L

H

L

H

L

H

L

Precharge Power

Down Mode¹

X

H

L

H

L

Entry

Exit

H

L

Active Power

Down Mode¹

H

X

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note:

1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Precharge command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time (tWR) is needed to guarantee that the last data has been

completely written.

5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

*For more information about Truth Table, refer to “Device Operation” section in Hynix website.

Rev. 1.2 /Apr. 2006

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WRITE MASK TRUTH TABLE

/CS, /RAS,

/CAS, /WE

Function

Data Write¹

CKEn-1

CKEn

DM

ADDR A10/AP

BA

H

X

L

X

Data-In Mask¹

H

Note:

1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In

case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.

Rev. 1.2 /Apr. 2006

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SIMPLIFIED STATE DIAGRAM

P o w er

A p p lied

Pow er

O n

P recharg

e

P R E A LL

S elf

R efresh

R E FS

R E FS X

R E FA

M R S

EM R S

A uto

R efresh

Id le

C KE L

C K E H

A ctive

Precharg

Pow er

D o w n

e

A C T

Pow er

D o w n

C K E H

C K E L

B urst

S to p

R o w

A ctive

W rite

R ead

W rite

R ead

W rite

A

R ead

A

W rite

R ead

W rite

A

R ead A

R ead

A

W rite

A

R ead A

PR E

P R E

P recharg

e

PR EA LL

P R E

A uto m atic S eq uence

C o m m and S eq uence

P R E A LL = P recharg e A ll B anks

M R S = M od e R eg ister S et

E M R S = E xtend ed M od e R eg ister S et

R E FS = E nter S elf R efresh

R E FS X = E xit S elf R efresh

R E FA = A uto R efresh

C K E L = E nter P o w er D ow n

C K E H = E xit P ow er D ow n

A C T = A ctive

W rite A = W rite w ith A uto precharg e

R ead A = R ead w ith A utop recharge

P R E = P recharg e

Rev. 1.2 /Apr. 2006

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POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF

(and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent dam-

age to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT.

Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an

LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to

guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal oper-

ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR

SDRAM requires a 200us delay prior to applying an executable command.

Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be

brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED

MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE

REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating

parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-

ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command

for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting

the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-

MOS low state. (All the other input pins may be undefined.)

• VDD and VDDQ are driven from a single power converter output.

• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.

• VREF tracks VDDQ/2.

• A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the

input current from the VTT supply into any pin.

• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-

ship must be adhered to during power up.

Voltage description

Sequencing

Voltage relationship to avoid latch-up

< VDD + 0.3V

VDDQ

VTT

After or with VDD

After or with VDDQ

< VDDQ + 0.3V

VREF

< VDDQ + 0.3V

2. Start clock and maintain stable clock for a minimum of 200usec.

3. After stable power and clock, apply NOP condition and take CKE high.

4. Issue Extended Mode Register Set (EMRS) to enable DLL.

5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200

cycles(tXSRD) of clock are required for locking DLL)

6. Issue Precharge commands for all banks of the device.

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HY5DU561622D(L)T

7. Issue 2 or more Auto Refresh commands.

8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low

Power-Up Sequence

VDD

VDDQ

tVTD

VTT

VREF

/CLK

CLK

tIS tIH

LVCMOS Low Level

CKE

NOP

PRE

EMRS

MRS

NOP

PRE

AREF

MRS

ACT

RD

CMD

DM

CODE

ADDR

A10

BA0, BA1

DQS

CODE

DQ'S

T=200usec

tRP

tMRD

tRP

tRFC

tMRD

tXSRD*

Power UP

VDD and CK stable

EMRS Set

MRS Set

(with A8=L)

MRS Set

Reset DLL

(with A8=H)

READ

Precharge All

Non-Read

Command

2 or more

Auto Refresh

Precharge All

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

Rev. 1.2 /Apr. 2006

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HY5DU561622D(L)T

MODE REGISTER SET (MRS)

The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,

burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the

low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and

CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to

write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is

determined, the information will be held until reset by another MRS command.

BA1

0

BA0

0

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

Operating Mode

CAS Latency

Burst Length

A6

0

A5

0

A4

0

CAS Latency

Reserved

2

A3

0

Burst Type

Sequential

Interleave

BA0

MRS Type

MRS

0

1

0

1

EMRS

0

1

0

1

3

1

0

Reserved

1.5

1

0

1

Burst Length

A2

A1

A0

1

0

2.5

Sequential

Reserved

2

Interleave

Reserved

2

1

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

A12~A9 A8

A7 A6~A0

Operating Mode

8

0

-

0

1

0

-

0

1

-

Valid

Normal Operation

Reserved

Valid

VS

-

Normal Operation/ Reset DLL

Vendor specific Test Mode

All other states reserved

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HY5DU561622D(L)T

BURST DEFINITION

Burst Length

Starting Address

Sequential

Interleave

(A2,A1,A0)

XX0

0, 1

2

XX1

1, 0

X00

0, 1, 2, 3

X01

1, 2, 3, 0

1, 0, 3, 2

4

X10

2, 3, 0, 1

X11

3, 0, 1, 2

3, 2, 1, 0

000

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

001

010

011

8

100

101

110

111

BURST LENGTH & TYPE

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst

length determines the maximum number of column locations that can be accessed for a given Read or Write com-

mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is

reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2 -Ai when the burst length

is set to four and by A3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit

for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location

within the block. The programmed burst length applies to both Read and Write bursts.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the

burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the

burst type and the starting column address, as shown in Burst Definition Table

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CAS LATENCY

The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the

availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR200/266/333 and

3 clocks for DDR400.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-

ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically

disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any

time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally

applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver

option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will

reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver

and the half strength driver are included in this document.

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EXTENDED MODE REGISTER SET (EMRS)

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-

tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits

shown below. The Extended Mode Register is programmed via the Mode Register Set command (BA0=1 and BA1=0)

and will retain the stored information until it is programmed again or the device loses power.

The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller

must wait the specified time before initiating any subsequent operation. Violating either of these requirements wil

result in unspecified operation.

BA1 BA0 A12 A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

0*

A1

DS

A0

0

1

Operating Mode

DLL

A0

0

DLL enable

Enable

BA0

0

MRS Type

MRS

1

Disable

1

EMRS

Output Driver

A1

Impedance Control

Full Strength Driver

Half Strength Driver

0

1

An~A3

A2~A0

Operating Mode

Normal Operation

0

_

Valid

_

All other states reserved

* This part do not support/QFC function, A2 must be programmed to Zero.

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ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

^oC

Operating Temperature (Ambient)

TA

0 ~ 70

^oC

V

Storage Temperature

TSTG

VDD

VDDQ

VINPUT

VIO

IOS

TSOLDER

-55 ~ 150

-1.0 ~ 3.6

-0.5 ~3.6

50

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Voltage on inputs relative to VSS

Voltage on I/O pins relative to VSS

Output Short Circuit Current

Soldering Temperature ⋅ Time

V

mA

^oC ⋅ Sec

260 ⋅ 10

Note: Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min

Typ.

Max

Unit

Power Supply Voltage (DDR200, 266, 333)

Power Supply Voltage (DDR200, 266, 333)¹

VDD

VDDQ

2.3

2.5

2.7

V

Power Supply Voltage (DDR400)

Power Supply Voltage (DDR400)¹

Input High Voltage

VDD

VDDQ

2.5

2.6

2.7

V

VIH

VIL

VREF + 0.15

-0.3

-

VDDQ + 0.3

VREF - 0.15

V

Input Low Voltage²

Termination Voltage

Reference Voltage³

VTT

VREF

VREF - 0.04

0.49*VDDQ 0.5*VDDQ 0.51*VDDQ

VREF

VREF + 0.04

V

Input Voltage Level, CK and CK inputs

VIN(DC)

VID(DC)

VI(RATIO)

ILI

-0.3

0.36

0.71

-2

-

VDDQ+0.3

VDDQ+0.6

V

Input Differential Voltage, CK and CK inputs⁴

V-I Matching: Pullup to Pulldown Current Ratio⁵

Input Leakage Current⁶

1.4

2

-

uA

Output Leakage Current⁷

ILO

-5

5

Output High Current

(min VDDQ, min VREF, min VTT)

Output Low Current

(min VDDQ, max VREF, max VTT)

Output High Current

(min VDDQ, min VREF, min VTT)

Output Low Current

Normal Strength Out-

put Driver

(VOUT=VTT ± 0.84)

IOH

IOL

IOH

IOL

-16.8

16.8

-13.6

13.6

-

mA

Half Strength Output

Driver

(VOUT=VTT ± 0.68)

(min VDDQ, max VREF, max VTT)

Note:

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.

Peak to peak noise on VREF may not exceed ± 2% of the DC value.

4. VID is the magnitude of the difference between the input level on CK and the input level on /CK.

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-

ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum

difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to mini-

mum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

6. VIN=0 to VDD, All other pins are not tested under VIN =0V.

7. DQs are disabled, VOUT=0 to VDDQ

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IDD SPECIFICATION AND CONDITIONS (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)

Test Conditions

Test Condition

Symbol

Operating Current:

One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice

per clock cycle; address and control inputs changing once per clock cycle

IDD0

Operating Current:

One bank; Active - Read - Precharge;

Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock

cycle

IDD1

IDD2P

IDD2F

Precharge Power Down Standby Current:

All banks idle; Power down mode; CKE=Low, tCK=tCK(min)

Idle Standby Current:

/CS=High, All banks idle; tCK=tCK(min);

CKE=High; address and control inputs changing once per clock cycle.

VIN=VREF for DQ, DQS and DM

Idle Quiet Standby Current:

/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref

for DQ, DQS and DM

IDD2Q

IDD3P

Active Power Down Standby Current:

One bank active; Power down mode; CKE=Low, tCK=tCK(min)

Active Standby Current:

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min);

DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing

once per clock cycle

IDD3N

Operating Current:

Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per

clock cycle; tCK=tCK(min); IOUT=0mA

IDD4R

IDD4W

Operating Current:

Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per

clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle

Auto Refresh Current:

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz;

distributed refresh

IDD5

tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz

Self Refresh Current:

CKE =< 0.2V; External clock on; tCK=tCK(min)

IDD6

IDD7

Operating Current - Four Bank Operation:

Four bank interleaving with BL=4, Refer to the following page for detailed test condition

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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7

IDD1: Operating current: One bank operation

1. Typical Case: VDD = 2.5V, T=25 ^oC for DDR200, 266, 333; VDD = 2.6V, T=25 ^oC for DDR400

2. Worst Case: VDD = 2.7V, T= 0 ^oC

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are

changing once per clock cycle. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRC = 10*tCK, tRAS = 5*tCK

Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing

50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

50% of data changing at every burst

- DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

50% of data changing at every burst

- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK

Read: A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing

50% of data changing at every burst

- DDR400(200Mhz, CL=3): tCK = 5ns, CL=3, BL=4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK

Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing

50% of data changing at every burst

Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP

IDD7: Operating current: Four bank operation

1. Typical Case: VDD = 2.5V, T=25 ^oC for DDR200, 266, 333; VDD = 2.6V, T=25 ^oC for DDR400

2. Worst Case: VDD = 2.7V, T= 0 ^oC

3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not

changing. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with Autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing

50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

50% of data changing at every burst

- DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

50% of data changing at every burst

- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

50% of data changing at every burst

- DDR400(200Mhz, CL=3): tCK = 5ns, CL = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

50% of data changing at every burst

Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP

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IDD Specification

64Mx4

Speed

DDR400B DDR333 DDR266A DDR266B DDR200

Parameter

Symbol

Unit

Operating Current

IDD0

IDD1

90

80

70

90

65

80

mA

Operating Current

100

Precharge Power Down Standby Current

Idle Standby Current

IDD2P

IDD2F

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

10

15

60

50

40

30

Active Power Down Standby Current

Active Standby Current

Operating Current

50

45

40

35

160

150

140

120

130

Operating Current

mA

Auto Refresh Current

150

Normal

Self Refresh Current

3

mA

IDD6

IDD7

Low Power

1.5

Operating Current - Four Bank Operation

250

240

220

200

32Mx8

Speed

Parameter

Symbol

Unit

DDR400B DDR333 DDR266A DDR266B DDR200

Operating Current

IDD0

IDD1

90

80

70

90

65

80

mA

100

Precharge Power Down Standby Current IDD2P

10

15

Idle Standby Current

Active Power Down Standby Current

Active Standby Current

Operating Current

IDD2F

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

60

50

40

30

50

45

40

35

180

160

150

140

130

Operating Current

mA

Auto Refresh Current

150

Normal

Self Refresh Current

Low Power

3

mA

IDD6

1.5

Operating Current - Four Bank Operation IDD7

230

220

200

180

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16Mx16

Speed

DDR400B DDR333 DDR266A DDR266B DDR200

Parameter

Symbol

Unit

Operating Current

IDD0

IDD1

90

80

70

90

65

80

mA

Operating Current

100

Precharge Power Down Standby Current

Idle Standby Current

IDD2P

IDD2F

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

10

15

60

50

40

30

Active Power Down Standby Current

Active Standby Current

Operating Current

50

45

40

35

200

190

170

140

150

130

Operating Current

mA

Auto Refresh Current

150

Normal

Self Refresh Current

3

mA

IDD6

IDD7

Low Power

1.5

Operating Current - Four Bank Operation

250

240

220

200

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AC OPERATING CONDITIONS (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min

Max

Unit

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC)

VREF + 0.31

-

V

-

VREF - 0.31

VDDQ + 0.6

Input Differential Voltage, CK and /CK inputs¹

Input Crossing Point Voltage, CK and /CK inputs²

VID(AC)

VIX(AC)

0.7

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

Note:

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

*For more information about AC Overshoot/Undershoot Specifications, refer to “Device Operation” section in hynix website.

AC OPERATING TEST CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Parameter

Value

Unit

Reference Voltage

Termination Voltage

VDDQ x 0.5

V

VDDQ x 0.5

AC Input High Level Voltage (VIH, min)

AC Input Low Level Voltage (VIL, max)

Input Timing Measurement Reference Level Voltage

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

VREF + 0.31

V

VREF - 0.31

V

VREF

VTT

1.5

1

V

Input minimum Signal Slew Rate

V/ns

Termination Resistor (RT)

50

Ω

W

pF

Series Resistor (RS)

25

Output Load Capacitance for Access Time Measurement (CL)

30

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AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted)

DDR400B

DDR333

Min Max

DDR266A

DDR266B

DDR200

Parameter

Symbol

UNIT

Min

Max

Min

Max

Min

Max

Min

Max

Row Cycle Time

tRC

55

-

60

72

42

-

65

-

65

-

70

-

ns

Auto Refresh Row

Cycle Time

tRFC

tRAS

tRAP

70

40

75

45

-

120K

-

75

45

-

120K

-

80

50

-

120K

-

Row Active Time

70K

-

70K

-

Active to Read with

Auto Precharge Delay

tRCD or

tRASmin

tRCD or

tRASmin

tRCD or

tRASmin

tRCD or

tRASmin

tRCD or

tRASmin

Row Address to

Column Address Delay

tRCD

tRRD

tCCD

15

10

1

-

18

12

1

-

20

15

1

-

20

15

1

-

20

15

1

-

ns

Row Active to Row

Active Delay

Column Address to

Column Address Delay

tCK

Row Precharge Time

Write Recovery Time

tRP

15

-

18

15

-

20

15

-

20

15

-

20

15

-

ns

tWR

Internal Write to Read

Command Delay

tWTR

2

-

1

-

1

-

1

-

1

-

tCK

(tWR/

tCK)

+

(tWR/

tCK)

+

(tWR/

tCK)

+

(tWR/

tCK)

+

(tWR/

tCK)

+

Auto Precharge Write

Recovery + Precharge

Time²²

tDAL

-

tCK

(tRP/tCK)

CL = 3

System

5

-

10

-

Clock Cycle

Time²⁴

CL = 2.5

tCK

6

12

7.5

12

7.5

12

8.0

10

12

ns

CL = 2

-

7.5

0.45

12

7.5

12

10

12

Clock High Level Width

Clock Low Level Width

tCH

tCL

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55 tCK

Data-Out edge to Clock

edge Skew

tAC

-0.7

-0.55

-

0.7

0.55

0.4

-0.7

-0.6

-

0.7

0.6

-0.75

-

0.75

0.5

-0.75

-

0.75

0.5

-0.75

-

0.75

0.6

ns

DQS-Out edge to Clock

edge Skew

tDQSCK

tDQSQ

DQS-Out edge to Data-

Out edge Skew²¹

0.45

Data-Out hold time

from DQS²⁰

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

tQH

tHP

-

ns

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

Clock Half Period^19,20

Data Hold Skew

Factor²⁰

tQHS

tDV

-

0.5

-

0.55

-

0.75

-

0.75

-

0.75

Valid Data Output

Window

tQH-tDQSQ

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- Continue

DDR400B

DDR333

DDR266A

Min Max

DDR266B

DDR200

Parameter

Symbol

UNIT

Min Max

Min

Max

Min

Max

Data-out high-impedance window

from CK,/CK¹⁰

tHZ

tLZ

tIS

tIH

tIS

-0.7

0.6

0.7

-0.7

0.75

0.8

0.7

-0.75 0.75

-0.75

0.75

-0.8

1.1

0.8

ns

Data-out low-impedance window

from CK, /CK¹⁰

0.7

-0.75

0.9

0.75

0.8

Input Setup Time (fast slew

rate)^14,16-18

-

0.9

1.0

-

Input Hold Time (fast slew

rate)^14,16-18

0.9

Input Setup Time (slow slew

rate)^15-18

1.0

Input Hold Time (slow slew

rate)^15-18

tIH

0.7

2.2

0.8

1.0

Input Pulse Width¹⁷

tIPW

-

2.2

-

2.2

-

2.2

-

2.5

-

ns

Write DQS High Level Width

Write DQS Low Level Width

tDQSH 0.35

tDQSL 0.35

0.35

tCK

Clock to First Rising edge of DQS-

In

tDQSS 0.72

1.25

0.75

0.2

1.25

0.75

0.2

1.25

0.75

0.2

1.25

0.75

0.2

1.25

tCK

DQS falling edge to CK setup time

tDSS

tDSH

0.2

-

DQS falling edge hold time from

CK

0.2

DQ & DM input setup time²⁵

DQ & DM input hold time²⁵

tDS

tDH

0.4

-

0.45

-

0.5

-

0.5

-

0.6

-

ns

DQ & DM Input Pulse Width¹⁷

Read DQS Preamble Time

Read DQS Postamble Time

tDIPW 1.75

-

1.1

0.6

-

1.75

0.9

0.4

0

-

1.1

0.6

-

1.75

0.9

0.4

0

-

1.1

0.6

-

1.75

0.9

0.4

0

-

1.1

0.6

-

2

0.9

0.4

0

-

1.1

0.6

-

ns

tRPRE

tRPST

0.9

0.4

0

tCK

ns

Write DQS Preamble Setup Time¹²

Write DQS Preamble Hold Time

tWPRES

tWPREH 0.25

-

0.25

0.4

2

-

0.25

0.4

2

-

0.25

0.4

2

-

0.25

0.4

2

-

tCK

Write DQS Postamble Time¹¹

Mode Register Set Delay

tWPST

tMRD

0.4

2

0.6

-

0.6

-

0.6

-

0.6

-

0.6

-

Exit Self Refresh to non-Read

command²³

tXSNR

tXSRD

tREFI

75

200

-

75

200

-

75

200

-

75

200

-

80

200

-

ns

tCK

us

Exit Self Refresh to Read

command

Average Periodic Refresh

Interval^13,25

7.8

Rev. 1.2 /Apr. 2006

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1HY5DU56422D(L)T

HY5DU56822D(L)T

HY5DU561622D(L)T

Note:

1. All voltages referenced to Vss.

2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,

but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to

be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production

tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.

Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-

tronics).

VDDQ

₅₀Ω

Output

(VOUT)

30 pF

Figure: Timing Reference Load

4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to

VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under

normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).

5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result

of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the

dc input LOW (HIGH) level.

6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is

recognized as LOW.

7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference

level for signals other than CK, /CK is VREF.

8. The output timing reference voltage level is VTT.

9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must

be powered down and then restarted through the specified initialization sequence before normal operation can continue.

10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to

a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but

system performance (bus turnaround) will degrade accordingly.

12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previ-

ously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could

be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

14. For command/address input slew rate ≥ 1.0 V/ns.

15. For command/address input slew rate ≥ 0.5 V/ns and ＜ 1.0 V/ns

16. For CK & /CK slew rate ≥ 1.0 V/ns (single-ended)

17. These parameters guarantee device timing, but they are not necessarily tested on each device.

They may be guaranteed by device design or tester correlation.

18. Slew Rate is measured between VOH(ac) and VOL(ac).

19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half

period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.

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20.tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The

pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the

worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects,

and p-channel to n-channel variation of the output drivers.

21. tDQSQ:

Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given

cycle.

22. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For DDR266B at CL=2.5 and tCK=7.5 ns

tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks

= ((2) + (3)) clocks

= 5 clocks

23. In all circumstances, tXSNR can be satisfied using

tXSNR = tRFCmin + 1*tCK

24. The only time that the clock frequency is allowed to change is during self-refresh mode.

25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid

READ can be executed.

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SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS

The following tables are described specification parameters that required in systems using DDR devices to ensure

proper performannce. These characteristics are for system simulation purposes and are guaranteed by design.

Input Slew Rate for DQ/DM/DQS (Table a.)

AC CHARACTERISTICS

PARAMETER

DDR400

DDR333

DDR266

DDR200

UNIT Note

Symbol

min

max

min

max

min

max

min

max

DQ/DM/DQS input slew rate

measured between VIH(DC),

VIL(DC) and VIL(DC), VIH(DC)

DCSLEW

0.5

4.0

0.5

4.0

0.5

4.0

0.5

4.0

V/ns

1,12

Address & Control Input Setup & Hold Time Derating (Table b.)

Input Slew Rate

0.5 V/ns

Delta tIS

0

Delta tIH

UNIT

Note

0

ps

9

0.4 V/ns

+50

0.3 V/ns

+100

DQ & DM Input Setup & Hold Time Derating (Table c.)

Input Slew Rate

0.5 V/ns

Delta tDS

0

Delta tDH

UNIT

ps

Note

11

0

0.4 V/ns

+75

ps

11

0.3 V/ns

+150

ps

11

DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate (Table d.)

Input Slew Rate

Delta tDS

0

Delta tDH

UNIT

ps

Note

10

0

± 0.0 ns/V

+50

+100

ps

10

± 0.25 ns/V

± 0.5 ns/V

+100

ps

10

Output Slew Rate Characteristics (for x4, x8 Devices) (Table e.)

Typical Range (V/

Slew Rate Characteristic

Minimum (V/ns)

Maximum (V/ns)

Note

ns)

Pullup Slew Rate

1.2 - 2.5

1.0

4.5

1,3,4,6,7,8

2,3,4,6,7,8

Pulldown Slew Rate

Output Slew Rate Characteristics (for x16 Device) (Table f.)

Typical Range (V/

Slew Rate Characteristic

Minimum (V/ns)

Maximum (V/ns)

Note

ns)

Pullup Slew Rate

1.2 - 2.5

1.0

4.5

1,3,4,6,7,8

2,3,4,6,7,8

Pulldown Slew Rate

Output Slew Rate Matching Ratio Characteristics (Table g.)

Slew Rate Characteristic

Parameter

DDR266A

DDR266B

DDR200

Note

min

max

min

max

min

max

Output Slew Rate Matching Ratio

(Pullup to Pulldown)

-

0.71

1.4

5,12

Rev. 1.2 /Apr. 2006

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Note:

1. Pullup slew rate is characterized under the test conditions as shown in below Figure.

Test Point

Output

(VOUT)

Ω

50

VSSQ

Figure: Pullup Slew rate

2. Pulldown slew rate is measured under the test conditions shown in below Figure.

VDDQ

Ω

50

Output

(VOUT)

Test Point

Figure: Pulldown Slew rate

3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250mV)

Pulldown slew rate is measured between (VDDQ/2 + 320mV ± 250mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example: For typical slew, DQ0 is switching

For minimum slew rate, all DQ bits are switching worst case pattern

For maximum slew rate, only one DQ is switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

4. Evaluation conditions

Typical: 25 ^oC (Ambient), VDDQ = nominal, typical process

Minimum: 70 ^oC (Ambient), VDDQ = minimum, slow-slow process

Maximum: 0 ^oC (Ambient), VDDQ = Maximum, fast-fast process

5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature

and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process

variation.

6. Verified under typical conditions for qualification purposes.

7. TSOP-II package devices only.

8. Only intended for operation up to 256 Mbps per pin.

9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b.

The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), sim-

ilarly for rising transitions.

10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c

& d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on

the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The

delta rise/fall rate is calculated as:

{1/(Slew Rate1)} - {1/(slew Rate2)}

For example:

If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would

result in the need for an increase in tDS and tDH of 100ps.

11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the

lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by

either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.

12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-

sitions through the DC region must be monotonic.

Rev. 1.2 /Apr. 2006

29

1HY5DU56422D(L)T

HY5DU56822D(L)T

HY5DU561622D(L)T

CAPACITANCE (TA=25^oC, f=100MHz)

Parameter

Symbol

Min

Max

Unit

Input Clock Capacitance

Delta Input Clock Capacitance

Input Capacitance

CK, /CK

CI1

Delta CI1

CI1

2.0

-

3.0

0.25

3.0

pF

All other input-only pins

DQ, DQS, DM

2.0

-

Delta Input Capacitance

Input / Output Capacitance

Delta Input / Output Capacitance

Delta CI2

CIO

0.5

5.0

0.5

4.0

-

DQ, DQS, DM

Delta CIO

Note:

1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V

2. Pins not under test are tied to GND.

3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

VTT

RT=50Ω

Output

Zo=50Ω

VREF

CL=30pF

Rev. 1.2 /Apr. 2006

30

1HY5DU56422D(L)T

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HY5DU561622D(L)T

PACKAGE INFORMATION

400mil 66pin Thin Small Outline Package

max

min

,

Unit : mm(Inch)

11.94 (0.470)

11.79 (0.462)

10.26 (0.404)

10.05 (0.396)

BASE PLANE

22.33 (0.879)

22.12 (0.871)

0 ~ 5 Deg.

0.35 (0.0138)

0.65 (0.0256) BSC

0.25 (0.0098)

SEATING PLANE

1.194 (0.0470)

0.991 (0.0390)

0.15 (0.0059)

0.05 (0.0020)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

Rev. 1.2 /Apr. 2006

31


型号：	HY5DU56822DLT-J
厂家：	HYNIX SEMICONDUCTOR
描述：	DDR DRAM, 32MX8, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件：	总31页 (文件大小：255K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY5DU56822DLT-J [HYNIX]

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