HY5PS1G1631CLFP-C4 [HYNIX]
1Gb DDR2 SDRAM; 1GB DDR2 SDRAM
| 型号： | HY5PS1G1631CLFP-C4 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 1Gb DDR2 SDRAM |
| 文件： | 总37页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
1Gb DDR2 SDRAM
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Dec 2006
1
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Revision Details
Rev.
History
Draft Date
0.1
0.2
Nov. 2006
Initial data sheet released
IDD Values added
Dec. 2006
Rev. 0.2 /Dec 2006
2
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Φεατυρεσ
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default χηαραχτεριστιχσ
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 0.2 / Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD = 1.8V +/- 0.1V
• VDDQ = 1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• 8 banks
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal eight bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) , 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
Operating Frequency
Ordering Information
Grade tCK(ns)
CL
3
tRCD
tRP
3
Unit
Part No.
Configuration Package
E3
C4
Y5
S5
Clk
5
3.75
3
3
4
5
5
HY5PS1G431C(L)FP-XX*
256Mx4
60 Ball
Clk
Clk
Clk
4
4
HY5PS1G831C(L)FP-XX*
HY5PS1G1631C(L)FP-XX*
128Mx8
5
5
84 Ball
64Mx16
2.5
5
5
Note:
-XX* is the speed bin, refer to the Operation Frequency table for complete Part No.
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
1.2 Pin Configuration & Address Table
256Mx4 DDR2 Pin Configuration(Top view: see balls through package)
7
8
3
9
1
2
VSSQ
DQS
VSS
VDDQ
VDD
NC
NC
A
B
C
DQS
VDDQ
DQ2
VSSQ
DQ0
VSSQ
CK
DM
VDDQ
DQ3
VSS
NC
VDDQ
NC
VSSQ
DQ1
VDDQ
NC
VSSQ
VREF
CKE
D
E
VSSDL
RAS
VDD
ODT
VDDL
F
G
H
J
CK
WE
CAS
A2
CS
A0
BA1
A1
BA2
VSS
VDD
BA0
A10
A3
VDD
VSS
A6
A4
A5
K
A11
NC
A8
A9
A7
L
A13
NC
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS
256Mx4
# of Bank
Bank Address
Auto Precharge Flag
Row Address
8
BA0,BA1,BA2
A10/AP
A0 - A13
A0-A9, A11
1 KB
Column Address
Page size
Rev. 0.2 /Dec 2006
5
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
128Mx8 DDR2 PIN CONFIGURATION(Top view: see balls through package)
7
8
3
9
1
2
VSSQ
DQS
VSS
VDDQ
VDD
DQ6
NU/RDQS
A
B
C
DQS
VDDQ
DQ2
VSSQ
DQ0
VSSQ
CK
DM/RDQS
VDDQ
DQ3
DQ7
VDDQ
DQ5
VSSQ
DQ1
VDDQ
DQ4
VSSQ
VREF
CKE
D
E
VSSDL
RAS
VSS
VDD
VDDL
F
G
H
J
CK
WE
ODT
CAS
A2
CS
A0
BA1
A1
BA2
VSS
VDD
BA0
A10
A3
VDD
VSS
A6
A4
A5
K
A11
NC
A8
A9
A7
L
A13
NC
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS
128Mx8
# of Bank
Bank Address
Auto Precharge Flag
Row Address
8
BA0, BA1, BA2
A10/AP
A0 - A13
A0-A9
Column Address
Page size
1 KB
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
64Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
7
8
3
9
1
2
A
B
C
D
E
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
UDQS
VSSQ
DQ8
VSS
UDM
VDDQ
DQ11
VSS
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDD
DQ14
VDDQ
DQ12
VDD
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
LDQS
VSSQ
DQ0
F
LDM
DQ6
VSSQ
DQ1
VSSQ
G
VDDQ
DQ3
VDDQ
DQ5
VDDQ
DQ4
H
J
VSSQ
VSSDL
RAS
CK
CK
VSS
WE
VDD
ODT
VDDL
VREF
CKE
K
L
CAS
A2
CS
A0
BA1
A1
NC, BA2
VSS
BA0
A10/AP
A3
M
VDD
VSS
A6
A4
A5
N
P
A11
A8
A9
A7
NC, A15
NC, A13
NC, A14
VDD
A12
R
ROW AND COLUMN ADDRESS TABLE
ITEMS
64Mx16
# of Bank
8
BA0, BA1, BA2
A10/AP
Bank Address
Auto Precharge Flag
Row Address
A0 - A12
A0-A9
Column Address
Page size
2 KB
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
IDD0
Conditions
Units
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS =
t
mA
RAS min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are
SWITCHING;Data bus inputs are SWITCHING
Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
t
t
t
t
t
t
t
t
= 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH,
CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same
as IDD4W
IDD1
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control
IDD2P
IDD2Q
IDD2N
mA
mA
mA
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP
t
mA
mA
= RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4,
t
t
t
t
t
t
CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS
is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as
IDD4W
IDD4R
mA
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
ING; Data bus inputs are SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
t
t
t
t
t
t
t
t
= CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD),
IDD7
t
t
mA
RCD = 1* CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
Rev. 0.2 /Dec 2006
8
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Note:
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3
speed grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
6. Definitions for IDD
LOW is defined as Vin £ VILAC(max)
HIGH is defined as Vin Š VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock)for DQ signals not including masks or strobes.
Rev. 0.2 /Dec 2006
9
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
2. Maximum DC Ratings
2.1 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
- 1.0 V ~ 2.3 V
V
1
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
V
IN, VOUT
V
1
TSTG
°C
1, 2
Input leakage current; any input 0V VIN VDD;
all other balls not under test = 0V)
II
-2 uA ~ 2 uA
-5 uA ~ 5 uA
uA
uA
Output leakage current; 0V VOUT VDDQ; DQ
and ODT disabled
IOZ
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the χεντερ/top side of the DRAM. For the measurement
conditions. please refer to JESD51-2 standard.
2.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
0 to 95
°C
1,2
Operating Temperature
Note:
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measure-
ment conditions, please refer to JESD51-2 standard.
2. At 85~95° TOPER , Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this tem-
perature range, an EMRS command is required to change ιnternal refresh rate.
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions (SSTL_1.8)
Rating
Symbol
Parameter
Supply Voltage
Units
Notes
Min.
Typ.
Max.
VDD
VDDL
VDDQ
VREF
VTT
1.7
1.8
1.9
V
V
1
1.7
1.8
1.8
1.9
1,2
1,2
3,4
5
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
Note:
1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the
value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track varia-
tions in VDDQ
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
5. VTT of transmitting device must track VREF of receiving device.
3.1.2 ODT DC electrical characteristics
PARAMETER/CONDITION
SYMBOL MIN NOM MAX UNITS NOTES
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt1(eff)
60
120
40
75
150
50
90
180
60
ohm
ohm
ohm
%
1
1
1
1
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff)
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm
Deviation of VM with respect to VDDQ/2
Rtt3(eff)
delta VM
-6
+6
Note :
1. Test condition for Rtt measurements
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac))
and I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
VIH (ac) - VIL (ac)
Rtt(eff) =
I(VIH (ac)) - I(VIL (ac))
Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.
2 x Vm
delta VM =
- 1 x 100%
VDDQ
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
Notes
VIH(dc)
VREF + 0.125
VDDQ + 0.3
V
dc input logic high
dc input logic low
VIL(dc)
- 0.3
VREF - 0.125
V
3.2.2 Input AC Logic Level
DDR2 400,533
DDR2 667,800
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
V
IH (ac)
VREF + 0.250
-
VREF + 0.200
-
-
V
V
ac input logic high
ac input logic low
VIL (ac)
-
VREF - 0.250
VREF - 0.200
3.2.3 AC Input Test Conditions
Symbol
Condition
Input reference voltage
Value
Units
Notes
VREF
0.5 * VDDQ
1.0
V
V
1
VSWING(MAX)
SLEW
Input signal maximum peak to peak swing
Input signal minimum slew rate
1
1.0
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising
edges and the range from VREF to VIL(ac) max for falling edges as shown in the figure below.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VSWING(MAX)
V
IL(dc) max
VIL(ac) max
VSS
delta TF
delta TR
VREF - VIL(ac) max
delta TF
VIH(ac) min - VREF
Falling Slew =
Rising Slew =
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.2.4 Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
VDDQ + 0.6
Units Notes
VID (ac)
0.5
V
V
1
2
ac differential input voltage
ac differential cross point voltage
VIX (ac)
0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175
Note:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS)
level.
The minimum value is equal to VIH(DC) - V IL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input sig-
nal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is
expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.
3.2.5 Differential AC output parameters
Symbol
Parameter
Min.
Max.
Units Notes
VOX (ac)
0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is
expected to track variations in VDDQ. VOX(AC) indicates the voltage at ωηιχη differential output signals must
cross.
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.3 Output Buffer Characteristics
3.3.1 Output AC Test Conditions
Symbol
Parameter
SSTL_18 Class II
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Note:
1. The VDDQ of the device under test is referenced.
3.3.2 Output DC Current Drive
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18
- 13.4
Units
mA
Notes
1, 3, 4
2, 3, 4
13.4
mA
Note:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ
and VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test
device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are
delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating
point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement.
Rev. 0.2 /Dec 2006
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HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.3.3 OCD default characteristics
Description
Parameter
Min
Nom
Max
Unit
ohms
ohms
ohms
V/ns
Notes
Output impedance
-
0
-
-
1.5
4
1
6
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
0
1,2,3
Sout
1.5
-
5
1,4,5,6,7,8
Note :
1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-
VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be
less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
measured from AC to AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process
corners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved
if the OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
VTT
25 ohms
Reference
point
Output
(Vout)
7. DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
tDQSQ and tQHS specification.
Rev. 0.2 /Dec 2006
15
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.4 IDD Specifications & Test Conditions
IDD Specifications(max)
DDR2 533
DDR2 667
DDR2 800
Units
DDR2 400
Symbol
x4
x8
x4
x8
x16
x4
x8
x16
x4
x8
x16
IDD0
IDD1
60
60
65
65
85
70
70
90
75
75
95
mA
70
8
70
8
75
8
75
8
110
8
80
8
80
8
115
8
85
8
85
8
120
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
22
30
20
9
22
30
20
9
27
35
20
9
27
35
20
9
27
35
20
9
30
40
25
9
30
40
25
9
30
40
25
9
32
45
25
9
32
45
25
9
32
45
25
9
F
S
IDD3P
IDD3N
IDD4W
IDD4R
IDD5
35
100
100
165
8
35
100
100
165
8
45
125
125
165
8
45
125
125
165
8
45
160
160
165
8
50
150
150
175
8
50
150
150
175
8
50
195
195
175
8
55
170
170
175
8
55
170
170
175
8
55
225
225
175
8
Normal
IDD6
Low
power
5
5
5
5
5
5
5
5
5
5
5
mA
mA
IDD7
165
165
175
175
260
180
180
265
185
185
270
Rev. 0.2 /Dec 2006
16
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
IDD0
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS
min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCH-
ING;Data bus inputs are SWITCHING
mA
Operating one bank active-read-precharge χυρρεντ ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
t
t
t
t
t
t
t
t
= 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH,
CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same
as IDD4W
IDD1
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control
IDD2P
IDD2Q
IDD2N
mA
mA
mA
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP
t
mA
mA
= RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
t
t
t
t
t
t
= CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as
IDD4W
IDD4R
mA
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
ING; Data bus inputs are SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
t
t
t
t
t
t
t
t
= CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD),
IDD7
t
t
mA
RCD = 1* CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
Rev. 0.2 /Dec 2006
17
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Note :
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed
grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
6. Definitions for IDD
LOW is defined as Vin £ VILAC(max)
HIGH is defined as Vin Š VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
Rev. 0.2 /Dec 2006
18
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
For purposes of IDD testing, the following parameters are to be utilized
DDR2-800
DDR2-
667
DDR2-
533
DDR2-
400
Parameter
5-5-5
6-6-6
6
5-5-5
5
4-4-4
4
3-3-3
3
Units
CL(IDD)
5
tCK
t
12.5
15
15
15
15
RCD(IDD)
ns
ns
t
57.5
7.5
60
60
60
RC(IDD)
55
t
7.5
ns
ns
RRD(IDD)-x4/x8
7.5
7.5
7.5
t
10
5
RRD(IDD)-x16
10
10
10
3
10
t
2.5
2.5
3.75
CK(IDD)
RASmin(IDD)
ns
ns
t
45
70000
12.5
75
45
70000
15
45
70000
15
45
70000
15
40
t
70000
15
ns
ns
ns
ns
ns
ns
RASmax(IDD)
t
RP(IDD)
t
t
75
75
75
75
RFC(IDD)-256Mb
105
105
105
105
105
127.5
197.5
RFC(IDD)-512Mb
t
t
127.5
197.5
127.5
197.5
127.5
197.5
127.5
197.5
RFC(IDD)-1Gb
RFC(IDD)-2Gb
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
t
t
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control and
address bus inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-DDR2-533 5/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
Timing Patterns for 8 bank devices x4/8
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
Timing Patterns for 8 bank devices x16
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D
Rev. 0.2 /Dec 2006
19
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.5. Input/Output Capacitance
DDR2 400
DDR2 533
DDR2 667
DDR2 800
Parameter
Symbol
Units
Min
1.0
Max
2.0
Min
1.0
x
Max
2.0
Input capacitance, CK and CK
Input capacitance delta, CK and CK
CCK
CDCK
CI
pF
pF
pF
pF
pF
pF
x
1.0
x
0.25
2.0
0.25
2.0
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
CDI
0.25
4.0
0.25
3.5
CIO
2.5
x
2.5
x
CDIO
0.5
0.5
4. Electrical Characteristics & AC Timing Specification
( 0 ϒ⊃ ϒℜ T
ℜϒ 95ϒ⊃ ; V
= 1.8 V +/- 0.1V; V = 1.8V +/- 0.1V)
CASE
DDQ DD
Refresh Parameters by Device Density
Symbol
Parameter
256Mb 512Mb 1Gb
2Gb
4Gb Units
Refresh to Active/Refresh command
time
tRFC
75
105
127.5
195
327.5
ns
0 ϒ⊃ ϒℜ TCASE ϒℜ 95ϒ⊃
85ϒ⊃ ≤… TCASE ϒℜ 95ϒ⊃
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
ns
ns
Average periodic refresh interval
tREFI
DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin
Speed
DDR2-800
DDR2-667
DDR2-533 DDR2-400 Units
Bin(CL-tRCD-tRP)
5-5-5
6-6-6
min
6
4-4-4
5-5-5
min
5
4-4-4
min
4
3-3-3
min
3
Parameter
CAS Latency
tRCD
min
5
min
4
tCK
ns
12.5
12.5
45
15
12
12
45
57
15
15
15
tRPNote1
tRAS
15
15
15
15
ns
45
45
45
40
ns
tRC
57.5
60
60
60
55
ns
Note 1: 8 bank device Precharge All Allowance : tRP for a Precharge All command for an 8 Bank device will equal to
tRP+1*tCK, where tRP are the values for a single bank Πρεχηαργε, which are shown in the table above.
Rev. 0.2 /Dec 2006
20
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Timing Parameters by Speed Grade
DDR2-400
min
DDR2-533
Symbol
Unit
Note
Parameter
max
+600
+500
0.55
0.55
-
min
-500
-450
0.45
0.45
max
+500
+450
0.55
0.55
-
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-600
-500
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
ps
CK low-level width
tCL
tHP
min(tCL,
tCH)
min(tCL,
tCH)
11,12
CK half period
Clock cycle time, CL=x
tCK
5000
150
275
25
8000
3750
100
225
-25
8000
ps
ps
ps
ps
ps
15
DQ and DM input setup time(differential strobe)
DQ and DM input hold time(differential strobe)
DQ and DM input setup time(single ended strobe)
DQ and DM input hold time(single ended strobe)
tDS(base)
tDH(base)
tDS
-
-
-
-
-
-
-
-
6,7,8,20
6,7,8,21
6,7,8,20
6,7,8,21
tDH
25
-25
Control & Address input pulse width for each
input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
tDIPW
tHZ
0.35
-
-
0.35
-
-
tCK
ps
tAC max
tAC max
18
18
tLZ
(DQS)
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tAC min
2*tAC min
-
tAC max
tAC max
350
tAC min
2*tAC min
-
tAC max
tAC max
300
ps
ps
ps
tLZ
(DQ)
18
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
13
12
DQ hold skew factor
tQHS
tQH
-
tHP - tQHS
WL - 0.25
0.35
0.35
0.2
450
-
tHP - tQHS
WL - 0.25
0.35
0.35
0.2
400
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
-
-
ps
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIS
WL + 0.25
WL + 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
-
-
-
-
-
0.2
-
-
0.2
-
-
2
2
0.4
0.6
-
0.4
0.6
-
10
Write preamble
0.35
350
0.35
250
Address and control input setup time
Address and control input hold time
Read preamble
-
-
5,7,9,23
5,7,9,23
tIH
475
-
375
-
ps
tRPRE
tRPST
0.9
1.1
0.6
0.9
1.1
0.6
tCK
tCK
Read postamble
0.4
0.4
Active to active command period for 1KB
page size products (x4, x8)
ns
ns
4
4
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
Active to active command period for 2KB
page size products (x16)
Rev. 0.2 /Dec 2006
21
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
-Continued
DDR2-400
DDR2-533
Uni
t
Symbol
Note
Parameter
min
max
min
max
Four Active Window for 1KB page size
products
ns
tFAW
tFAW
37.5
50
-
37.5
50
-
Four Active Window for 2KB page size
products
-
-
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
2
tCK
ns
15
-
-
-
15
-
-
-
Auto precharge write recovery + precharge
time
tDAL
WR+tRP*
WR+tRP*
tCK
14
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWTR
tRTP
10
7.5
7.5
7.5
ns
ns
24
3
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
-
-
-
-
tCK
Exit precharge power down to any non-read
command
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
1
Exit active power down to read command
(Slow exit, Lower power)
6 - AL
6 - AL
1, 2
CKE minimum pulse width
(high and low pulse width)
tCKE
tAOND
tAON
3
2
3
2
tCK
tCK
ns
ODT turn-on delay
ODT turn-on
2
2
tAC(max)
+1
tAC(max)
+1
tAC(min)
tAC(min)
16
17
2tCK+tAC
(max)
+1
tAONP
D
tAC(min)+
2
tAC(min)+
2
2tCK+tAC
(max)+1
ODT turn-on(Power-Down mode)
ns
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
tAC(max)
+ 0.6
tAC(max)
+ 0.6
tAC(min)
tAC(min)
2.5tCK+t
AC(max)
+1
tAC(min)+
2
2.5tCK+tA
C(max)+1
tAC(min)+
2
tAOFPD
ODT turn-off (Power-Down mode)
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after
CKE asynchronously drops LOW
tIS+tCK+tI
H
tIS+tCK+tI
H
tDelay
ns
15
Rev. 0.2 /Dec 2006
22
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
DDR2-667
min
DDR2-800
Symbol
Unit
Note
Parameter
max
+450
+400
0.55
min
-400
-350
0.45
0.45
max
+400
+350
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
0.55
0.55
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
-
-
ps
11,12
Clock cycle time, CL=x
tCK
3000
8000
2500
ps
ps
15
DQ and DM input setup time
DQ and DM input hold time
tDS(base)
tDH(base)
100
-
50
-
6,7,8,20
6,7,8,21
175
-
125
-
ps
Control & Address input pulse width for each input tIPW
0.6
-
-
0.6
-
-
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDIPW
tHZ
0.35
0.35
-
tAC max
tAC max
tAC max
240
-
tAC max
tAC max
tAC max
200
18
18
18
13
12
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC min
ps
2*tAC min
2*tAC min
ps
-
-
ps
-
340
-
300
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
-
0.35
0.35
0.2
0.2
2
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
-
-
-
tDSH
-
-
tMRD
-
0.6
-
-
0.6
-
tWPST
tWPRE
tIS(base)
tIH(base)
tRPRE
tRPST
tRAS
0.4
0.35
200
275
0.9
0.4
45
0.4
0.35
175
250
0.9
0.4
45
10
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
-
-
5,7,9,22
-
-
ps
5,7,9,23
1.1
0.6
70000
1.1
0.6
70000
tCK
tCK
ns
19
19
3
Read postamble
Activate to precharge command
Active to active command period for 1KB page size
products (x4, x8)
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
ns
ns
4
4
Active to active command period for 2KB page size
products (x16)
Four Active Window for 1KB page size products
Four Active Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
37.5
-
-
37.5
-
-
ns
ns
50
2
50
2
tCK
ns
Write recovery time
15
-
-
15
-
-
Auto precharge write recovery + precharge time
tDAL
WR+tRP
WR+tRP
tCK
14
Rev. 0.2 /Dec 2006
23
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
-Continue-
DDR2-667
DDR2-800
Symbol
Unit
Note
Parameter
min
max
min
7.5
max
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWTR
tRTP
7.5
7.5
-
-
ns
ns
7.5
3
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
-
-
-
-
tCK
Exit precharge power down to any non-read
command
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
1
Exit active power down to read command
(Slow exit, Lower power)
7 - AL
8 - AL
1, 2
CKE minimum pulse width
(high and low pulse width)
t
3
2
3
2
tCK
tCK
ns
CKE
t
ODT turn-on delay
ODT turn-on
2
2
AOND
tAC(max)
+0.7
tAC(max)
+0.7
t
tAC(min)
tAC(min)
6,16
AON
2tCK+
tAC(min)
+2
2tCK+
t
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
ns
tCK
ns
AONPD
tAC(max)+1
tAC(max)+1
t
2.5
2.5
2.5
AOFD
tAC(max)
+0.6
t
ODT turn-off
tAC(min)
tAC(max)+ 0.6
tAC(min)
17
AOF
tAC(min)
+2
2.5tCK+
tAC(max)+1
tAC(min)
+2
2.5tCK+
tAC(max)+1
t
ODT turn-off (Power-Down mode)
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tIS+tCK
+tIH
tDelay
tIS+tCK+tIH
ns
15
Rev. 0.2 /Dec 2006
24
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between
DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is
not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to
VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV
to CK - CK = +500 mV
(250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or
between DQS and DQS for differential strobe.
2. DDR2 SDRAM AC timing reference load
The following figure represents the timing reference load used in defining the relevant timing parameters
of the part. It is not intended to be either a precise representation of the typical system environment nor a
depiction of the actual load presented by a production tester. System designers will use IBIS or other simula-
tion tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their
production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
DQS
Output
DUT
VTT = VDDQ/2
RDQS
RDQS
Timing
reference
point
25Ω
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-
ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown below.
VDDQ
DUT
DQ
Output
DQS, DQS
VTT = VDDQ/2
RDQS, RDQS
25Ω
Test point
Slew Rate Test Load
Rev. 0.2 /Dec 2006
25
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the
setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied
externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
V
(dc)
V
(ac)
IH
IH
DQ
DM
D
D
D
t
D
t
V
(ac)
V
(dc)
IL
IL
t
t
DS
DH
DH
DS
V
(dc)
V
(ac)
IH
IH
DMin
DMin
DMin
(ac)
DMin
(dc)
V
IL
V
IL
Figure -- Data input (write) timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
Rev. 0.2 /Dec 2006
26
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other
slew rate values.
6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0
V/ns. See System Derating for other slew rate values.
7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS sig-
nals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single
ended mode. See System Derating for other slew rate values.
8. tDS and tDH derating
tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table)
DQS, DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
△tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD
S
H
S
H
S
H
S
-
H
-
S
-
H
-
S
-
H
-
S
-
H
-
S
-
H
S
-
H
2.0 125 45 125 45 +125 +45
-
-
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
83
0
-
21
0
-
83
0
21 +83 +21 95
33
12
-2
-
-
-
-
-
-
-
-
-
-
-
0
0
0
12
1
24
13
-1
24
10
-7
-
-
-
-
-
-
-
DQ
Slew
rate
-11 -14 -11 -14
25
11
-7
22
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-25 -31 -13 -19
23
5
17
-6
-
-
-
-
-
-43 -54 -31 -42 -42 -19
-8
17
-7
6
-
-
V/ns
-
-
-67 -83
-110 -125
-175 -188
-
-
-
-
-
-
-43 -59 -31 -47 -19 -35
-23
5
-11
-
-
-
-
-
-
-74 -89 -62 -77 -50 -65 -38 -53
-127 -140 -115 -128 -103 -116
-
-
-
-
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating
value listed in Table x.
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac region’,
use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded
‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tDH) nominal slew rate for a rising signal is defined as the slew ρατε between the last crossing of Vil(dc) max and the first crossing
of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the
first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’,
the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Rev. 0.2 /Dec 2006
27
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Fig. a Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VREF to ac
region
VIL(ac)max
Vss
Delta TF
Delta TR
Setup Slew Rate
Falling Signal
VREF(dc)-VIL(ac)max
Delta TF
Setup Slew Rate
Rising Signal
VIH(ac)min-VREF(dc)
Delta TR
=
=
Rev. 0.2 /Dec 2006
28
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Fig. -b Illustration of tangent line for tIS,tDS
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
nominal
line
VIH(ac)min
VIH(dc)min
tangent
line
VREF(dc)
Tangent
line
VIL(dc)max
VREF to ac
region
VIL(ac)max
Nomial
line
Vss
Delta TR
Setup Slew Rate
Rising Signal
Tangent line[VIH(ac)min-VREF(dc)]
Delta TR
=
Delta TF
Tangent line[VREF(dc)-VIL(ac)max]
Delta TF
Setup Slew Rate
Falling Signal
=
Rev. 0.2 /Dec 2006
29
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Fig. -c Illustration of nominal line for tIH, tDH
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
dc to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Hold Slew Rate
Delta TF
VIH(dc)min - VREF(dc)
Delta TF
Hold Slew Rate
Rising Signal
VREF(dc)-VIL(dc)max
Delta TR
=
=
Falling Signal
Rev. 0.2 /Dec 2006
30
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Fig. -d Illustration of tangent line for tIH , tDH
CK, DQS
CK, DQS
tIS,
tDS
tIS,
tDS
tIH,
tDH
tIH,
tDH
VDDQ
VIH(ac)min
nominal
line
VIH(dc)min
tangent
line
VREF(dc)
dc to VREF
region
Tangent
line
nominal
line
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max]
=
Rising Signal
Delta TR
Tangent line[VIH(ac)min-VREF(dc)]
Delta TF
Hold Slew Rate
Falling Signal
=
Rev. 0.2 /Dec 2006
31
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
9. tIS and tIH (input setup and hold) derating
tIS, tIH Derating Values
CK, CK Differential Slew Rate
1.5 V/ns
2.0 V/ns
tIS
1.0 V/ns
tIS tIH
△
tIH
tIS
tIH
△
△
△
△
△
Units
Notes
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+187
+179
+167
+150
+125
+83
+94
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+89
+83
+75
+45
+21
0
+0
-11
-14
Command /
Address
Slew
-25
-31
-43
-54
rate(V/ns)
-67
-83
-100
-150
-223
-250
-500
-750
-1250
-125
-188
-292
-375
-500
-708
-1125
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the
datasheet value to the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
(dc) and the first crossing of V (ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as
REF
IH
the slew rate between the last crossing of VREF(dc) and the first crossing of V (ac)max. If the actual signal is
IL
always earlier than the nominal slew rate for line between shaded ‘V (dc) to ac region’, use nominal slew
REF
rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘V (dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level
REF
to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of V (dc). Hold(tIH) nominal slew rate for a falling signal is defined as the
REF
slew rate between the last crossing of V (dc). If the actual σιγναλ is always later than the nominal slew
REF
rate line between shaded ‘dc to V (dc) region’, use nominal slew rate for derating value(see Fig.c) If the
REF
actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to V (dc) region’, the
REF
slew rate of a tangent line to the actual signal from the dc level to V (dc) level is used for derating
REF
value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached
V
(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transi-
IH/IL
tion and reach V
(ac).
IH/IL
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Rev. 0.2 /Dec 2006
32
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value
for this parameter, but system performance (bus turnaround) will degrade accordingly.
11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as
provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH).
For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock
source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.
12. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the
next transition, both of which are, separately, due to data pin skew and output pattern effects, and
p-channel to n-channel variation of the output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given
cycle.
14. t DAL = (nWR) + ( tRP/tCK):
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the
application clock period. nWR refers to the t WR parameter stored in the MRS.
Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns)
clocks =4 +(4)clocks=8clocks.
15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode.
In case of clock frequency change during precharge power-down, a specific procedure is required as
described in section 2.9.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
17. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are
referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or
begins driving (tLZ). Below figure shows a method to calculate the point when device is no longer driving
(tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measure-
ment points are not critical as long as the calculation is consistenet.
Rev. 0.2 /Dec 2006
33
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the
device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calcu-
late these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows
a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by
measuring the signal at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent.
VOH + xmV
VTT + 2xmV
VTT + xmV
VOH + 2xmV
tHZ
tHZ
tRPST end point
tRPRE begin point
VOL + 1xmV
VOL + 2xmV
VTT -xmV
VTT - 2xmV
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input
signal crossing at the V (ac) level to the differential data strobe crosspoint for a rising signal, and from the
IH
input signal crossing at the V (ac) level to the differential data strobe crosspoint for a falling signal applied to
IL
the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input
signal crossing at the V (dc) level to the differential data strobe crosspoint for a rising signal and V (dc) to
IH
IL
the differential data strobe crosspoint for a falling signal applied to the device under test.
Differential Input waveform timing
DQS
DQS
tDS tDH
tDS tDH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
VSS
22. Input waveform timing is referenced from the input signal crossing at the V (ac) level for a rising signal
IH
and V (ac) for a falling signal applied to the device under test.
IL
23. Input waveform timing is referenced from the input signal crossing at the V (dc) level for a rising signal
IL
and V (dc) for a falling signal applied to the device under test.
IH
Rev. 0.2 /Dec 2006
34
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Rev. 0.2 /Dec 2006
35
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
5. Package Dimensions
Package Dimension(x4,x8)
60Ball Fine Pitch Ball Grid Array Outline
8.00 ± 0.10
A1 BALL MARK
2-R0.13MAX
< Top View>
< SIDE View>
1.10 ± 0.10
0.34 ± 0.05
0.80 X 8 = 6.40
2.10 ± 0.10
A1 BALL MARK
8
9
7
3 2 1
A
B
C
D
E
F
G
H
J
K
L
60X Φ0.45 ± 0.05
1.60 1.60
0.80
< Bottom View>
Note: All dimensions are in millimeters.
Rev. 0.2 /Dec 2006
36
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Package Dimension(x16)
84Ball Fine Pitch Ball Grid Array Outline
8.00 ± 0.10
A1 BALL MARK
2-R0.13MAX
< Top View>
< SIDE View>
1.10 ± 0.10
0.34 ± 0.05
0.80 X 8 = 6.40
2.10 ± 0.10
A1 BALL MARK
3 2 1
9
8 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
0.80
84X Φ0.45 ± 0.05
1.60 1.60
< Bottom View>
Note: All dimensions are in millimeters.
Rev. 0.2 /Dec 2006
37
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