HY5PS1G831F-C4_技术文档

HY5PS1G431(L)F

HY5PS1G831(L)F

1Gb DDR2 SDRAM

HY5PS1G431(L)F

HY5PS1G831(L)F

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.2 / Dec 2006

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Revision History

Rev.

History

Draft Date

0.1

0.2

Feb.2004

Preliminary

Corrected typos of Pin description & tRFC spec. ,

Added IDD spec.

Apr.2004

Editorial Clean up, Transfered Functional description, command truth table pages and

Some contents of Operating conditions to <Device Operation & timing diagram>

Jul. 2004

1.0

Feb. 2005

July 2006

Dec 2006

Updated IDD spec.

1.1

1.2

Corrected typo, and removed improper note in ODT DC spec.

Corrected Pinout Numbering

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Contents

1. Description

1.1 Device Features and Ordering Information

1.1.1 Key Feaures

1.1.2 Ordering Information

1.1.3 Ordering Frequency

1.2 Pin configuration

1.3 Pin Description

2. Maximum DC ratings

2.1 Absolute Maximum DC Ratings

2.2 Operating Temperature Condition

3. AC & DC Operating Conditions

3.1 DC Operating Conditions

5.1.1 Recommended DC Operating Conditions(SSTL_1.8)

5.1.2 ODT DC Electrical Characteristics

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

3.2.2 Input AC Logic Level

3.2.3 AC Input Test Conditions

3.2.4 Differential Input AC Logic Level

3.2.5 Differential AC output parameters

3.3 Output Buffer Levels

3.3.1 Output AC Test Conditions

3.3.2 Output DC Current Drive

3.3.3 OCD default chracteristics

3.4 IDD Specifications & Measurement Conditions

3.5 Input/Output Capacitance

4. AC Timing Specifications

5. Package Dimensions

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1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

• VDD=1.8V

• VDDQ=1.8V +/- 0.1V

• All inputs and outputs are compatible with SSTL_18 interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

• Differential Data Strobe (DQS, DQS)

• Data outputs on DQS, DQS edges when read (edged DQ)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising

edges of the clock

• Programmable CAS latency 3, 4, 5 and 6 supported

• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

• Programmable burst length 4/8 with both nibble sequential and interleave mode

• Internal eight bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 68ball FBGA(x4/x8)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Read Data Strobe suupported (x8 only)

• Self-Refresh High Temperature Entry

Operating Frequency

Ordering Information

Grade tCK(ns)

CL

3

tRCD

tRP

Unit

Part No.

Configuration Package

-E3

-E4

-C4

-C5

-Y5

-Y6

Clk

5

3

4

5

6

3

4

5

6

HY5PS1G431(L)F-X*

256Mx4

128Mx8

68Ball

Clk

4

HY5PS1G831(L)F-X*

3.75

3

4

5

Note: -X* is the speed bin, refer to the Operation

Frequency table for complete Part No.

3

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1.2 Pin Configuration & Address Table

256Mx4 DDR2 Pin Configuration

7

8

3

9

1

2

NC

A

B

C

D

NC

VSSQ

DQS

VSS

VDDQ

VDD

NC

E

F

DQS

VDDQ

DQ2

VSSQ

DQ0

VSSQ

CK

DM

VDDQ

DQ3

VSS

NC

VDDQ

NC

VSSQ

DQ1

VDDQ

NC

G

VSSQ

VREF

CKE

H

J

VSSDL

RAS

VDD

ODT

VDDL

K

L

CK

WE

CAS

A2

CS

A0

BA1

A1

BA2

VSS

VDD

BA0

A10

A3

M

N

P

VDD

VSS

A6

A4

A5

A11

NC

A8

A9

A7

R

A13

NC

A12

T

U

V

W

NC

ROW AND COLUMN ADDRESS TABLE

ITEMS

256Mx4

# of Bank

Bank Address

Auto Precharge Flag

Row Address

8

BA0,BA1,BA2

A10/AP

A0 - A13

A0-A9, A11

1 KB

Column Address

Page size

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128Mx8 DDR2 PIN CONFIGURATION

7

8

3

9

1

2

NC

A

B

C

D

NC

VSSQ

DQS

VSS

VDDQ

VDD

DQ6

NU/RDQS

E

F

DQS

VDDQ

DQ2

VSSQ

DQ0

VSSQ

CK

DM/RDQS

VDDQ

DQ3

DQ7

VDDQ

DQ5

VSSQ

DQ1

VDDQ

DQ4

G

VSSQ

VREF

CKE

H

J

VSSDL

RAS

VSS

VDD

VDDL

K

L

CK

WE

ODT

CAS

A2

CS

A0

BA1

A1

BA2

VSS

VDD

BA0

A10

A3

M

N

P

VDD

VSS

A6

A4

A5

A11

NC

A8

A9

A7

R

A13

NC

A12

T

U

V

W

NC

ROW AND COLUMN ADDRESS TABLE

ITEMS

128Mx8

# of Bank

8

BA0, BA1, BA2

A10/AP

Bank Address

Auto Precharge Flag

Row Address

A0 - A13

A0-A9

Column Address

Page size

1 KB

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1.3 PIN DESCRIPTION

TYPE

DESCRIPTION

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on

the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced

to the crossings of CK and CK (both directions of crossing).

CK, CK

Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device

input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF

REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is

synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous

for SELF REFRESH exit. After V_REFhas become stable during the power on and initialization

CKE

Input

sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh

entry and exit, V_REFmust be maintained to this input. CKE must be maintained high throughout

READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER

DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.

Chip Select : All commands are masked when CS is registered HIGH. CS provides for external bank

selection on systems with multiple banks. CS is considered part of the command code.

CS

Input

On Die Termination Control : ODT(registered HIGH) enables on die termination resistance internal

to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS, RDQS, and DM

signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ,

UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode

Register(EMRS(1)) is programmed to disable ODT.

ODT

RAS, CAS, WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is

sampled High coincident with that input data during a WRITE access. DM is sampled on both

edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading.

For x8 device, the function of DM or RDQS/ RDQS is enabled by EMRS command.

DM

(LDM, UDM)

Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE

command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank address also deter-

mines if the mode register or extended mode register is to be accessed during a MRS or EMRS

cycle.

BA0 - BA2

Input

Address Inputs: Provide the row address for ACTIVE commands, and the column address and

AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array

in the respective bank. A10 is sampled during a precharge command to determine whether the

PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be

precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code during

MODE REGISTER SET commands.

A0 -A15

DQ

Input/Output Data input / output : Bi-directional data bus

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-Continue-

TYPE

DESCRIPTION

Data Strobe : Output with read data, input with write data. Edge aligned with read data, cen-

tered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corre-

sponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled

via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may

be used in single ended mode or paired with optional complementary signals DQS,

LDQS,UDQS and RDQS to provide differential pair signaling to the system during both reads

and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals.

DQS, (DQS)

(UDQS),(UDQS)

(LDQS),(LDQS)

(RDQS),(RDQS)

In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of

EMRS(1)

Input/Output

x4 DQS/DQS

x8 DQS/DQS

x8 DQS/DQS, RDQS/RDQS,

if EMRS(1)[A11] = 0

if EMRS(1)[A11] = 1

x16 LDQS/LDQS and UDQS/UDQS

"single-ended DQS signals" refers to any of the following with A10 = 1 of

EMRS(1)

x4 DQS

x8 DQS

x8 DQS, RDQS,

if EMRS(1)[A11] = 0

if EMRS(1)[A11] = 1

x16 LDQS and UDQS

NC

VDDQ

VSSQ

VDDL

VSSDL

VDD

No Connect : No internal electrical connection is present.

DQ Ground

Supply

DQ Power Supply : 1.8V +/- 0.1V

DLL Power Supply : 1.8V +/- 0.1V

DLL Ground

Power Supply : 1.8V +/- 0.1V

Ground

VSS

VREF

Reference voltage for inputs for SSTL interface.

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2. Maximum DC Ratings

2.1 Absolute Maximum DC Ratings

Symbol

Parameter

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VDDL pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

Rating

Units

Notes

VDD

- 1.0 V ~ 2.3 V

V

1

VDDQ

VDDL

- 0.5 V ~ 2.3 V

-55 to +100

V

1

V_INV_OUT

,

V

1

T_STG

°C

1, 2

1. . Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

2. Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions.

Please refer to JESD51-2 standard.

2.2 Operating Temperature Condition

Symbol

Parameter

Operating Temperature

Rating

Units

Notes

Toper

0 to 85

°C

1,2

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,

please refer to JESD51-2 standard.

2. The operatin temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature

rang, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During

operation, the DRAM case temperature must be maintained between 0 ~ 85°C under all other specification parameters. However,

in some applications, it is desirable to operate the DRAM up to 95°C case temperature. Therefore 2 spec options may exist.

1) Supporting 0 - 85°C with full JEDEC AC & DC specifications. This is the minimum requirements for all oprating temperature

options.

2) Supporting 0 - 85°C and being able to extend to 95°C with doubling auto-refresh commands in frequency to a 32 ms

period(tRFI=3.9us).

Note; Currently the periodic Self-Refresh interval is hard coded within the DRAM to a specificic value.

There is a migration plan to support higher temperature Self-Refresh entry via the control of EMRS(2) bit A7. However, since

Self-Refresh control function is a migrated process. For our DDR2 module user, it is imperative to check SPD Byte 49 Bit 0

to ensure the DRAM parts support higer than 85°C case temperature Self-Refresh entry.

1) if SPD Byte 49 Bit 0 is a “0” means DRAM does not support Self-Refresh at higher than 85°C, then system have to ensure

the DRAM is at or below 85°C case temperature before initiating Self-Refresh operation.

2) if SPD Byte 49 Bit 0 is a “1” means DRAM supports Self-Refresh at higher than 85°C case temperature, then system can

use register bit A7 at EMRS(2) control DRAM to operate at proper Self-Refresh rate for higher temperature. Please also

refer to EMRS(2) register definition section and DDR2 DIMM SPD definition for details.

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3. AC & DC Operating Conditons

3.1 DC Operating Conditions

3.1.1 Recommended DC Operating Conditions (SSTL_1.8)

Rating

Symbol

Parameter

Units

Notes

Min.

Typ.

Max.

VDD

VDDL

VDDQ

VREF

VTT

1.7

1.8

1.9

V

Supply Voltage

1.7

1.8

1.9

4

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.9

V

0.49*VDDQ

VREF-0.04

0.50*VDDQ

VREF

0.51*VDDQ

VREF+0.04

mV

V

1, 2

3

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must

be less than or equal to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is

expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together

3.1.2 ODT DC electrical characteristics

PARAMETER/CONDITION

SYMBOL

MIN

NOM

MAX UNITS NOTES

Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm

Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm

Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm

Deviation of VM with respect to VDDQ/2

Rtt1(eff)

Rtt2(eff)

delta VM

60

75

90

ohm

1

120 150

40

-6

180 ohm

60

+6

50

ohm

%

Note 1: Test condition for Rtt measurements

Measurement Definition for Rtt(eff): Apply V_IH(ac) and V_IL(ac) to test pin separately, then measure current I(V_IH

(ac)) and I( V_IL(ac)) respectively. V_IH(ac), V_IL(ac), and VDDQ values defined in SSTL_18

V_IH(ac) - V_IL(ac)

Rtt(eff) =

I(V_IH(ac)) - I(V_IL(ac))

Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.

2 x Vm

- 1

x 100%

delta VM =

VDDQ

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3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

Symbol

Parameter

dc input logic high

dc input logic low

Min.

Max.

Units

Notes

V_IH(dc)

VREF + 0.125

VDDQ + 0.3

V

V_IL(dc)

- 0.3

VREF - 0.125

V

3.2.2 Input AC Logic Level

Symbol

Parameter

ac input logic high

ac input logic low

Min.

Max.

Units

Notes

V_IH(ac)

VREF + 0.250

-

V

V_IL(ac)

-

VREF - 0.250

V

3.2.3 AC Input Test Conditions

Symbol

V_REF

Condition

Input reference voltage

Value

Units

Notes

0.5 * V_DDQ

V

1

V_SWING(MAX)

SLEW

Input signal maximum peak to peak swing

Input signal minimum slew rate

1.0

V

V/ns

2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V_REFlevel applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from V_REFto V_IH(ac)min for rising edges and the range

from V_REFto V_IL(ac)max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to

VIL(ac) on the negative transitions.

V

DDQ

IH(ac)

IH(dc)

REF

min

V

SWING(MAX)

max

IL(dc)

IL(ac)

SS

delta TF

delta TR

Rising Slew =

V

min - V

REF

V

-

V

max

IL(ac)

IH(ac)

REF

Falling Slew =

delta TF

delta TR

< Figure : AC Input Test Signal Waveform>

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3.2.4 Differential Input AC logic Level

Symbol

Parameter

ac differential input voltage

ac differential cross point voltage

Min.

Max.

Units

Notes

V_ID(ac)

0.5

VDDQ + 0.6

V

1

V_IX(ac)

0.5 * VDDQ - 0.175

0.5 * VDDQ + 0.175

V

2

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and

UDQS.

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS

or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V

IL(DC).

V

DDQ

V

TR

Crossing point

V

ID

V

IX or OX

V

CP

V

SSQ

< Differential signal levels >

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS,

LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC)

- V IL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in

VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.

3.2.5 Differential AC output parameters

Symbol

Parameter

Min.

Max.

Units

Notes

V_OX(ac)

0.5 * VDDQ - 0.125

0.5 * VDDQ + 0.125

V

1

ac differential cross point voltage

Notes:

1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations

in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

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3.3 Output Buffer Characteristics

3.3.1 Output AC Test Conditions

Symbol

Parameter

SSTL_18 Class II

Units

Notes

V_OTR

Output Timing Measurement Reference Level

0.5 * V_DDQ

V

1

1. The VDDQ of the device under test is referenced.

3.3.2 Output DC Current Drive

Symbol

I_OH(dc)

Parameter

Output Minimum Source DC Current

Output Minimum Sink DC Current

SSTl_18

- 13.4

13.4

Units

mA

Notes

1, 3, 4

2, 3, 4

I_OL(dc)

mA

1.

2.

V

_DDQ= 1.7 V; V_OUT= 1420 mV. (V_OUT- V_DDQ)/I_OHmust be less than 21 ohm for values of V_OUTbetween V_DDQand V_DDQ- 280

mV.

_DDQ= 1.7 V; V_OUT= 280 mV. V_OUT/I_OLmust be less than 21 ohm for values of V_OUTbetween 0 V and 280 mV.

V

3. The dc value of V_REFapplied to the receiving device is set to V_TT

4. The values of I_OH(dc)and I_OL(dc)are based on the conditions given in Notes 1 and 2. They are used to test device drive current

capability to ensure V_IHmin plus a noise margin and V_ILmax minus a noise margin are delivered to an SSTL_18 receiver. The

actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define

a convenient driver current for measurement.

3.3.3 OCD defalut characteristics

Description

Parameter

Min

12.6

Nom

Max

23.4

Unit

Notes

Output impedance

18

ohms

1,2

Output impedance step size for OCD cali-

bration

0

1.5

ohms

6

Pull-up and pull-down mismatch

Output slew rate

0

4

5

ohms

V/ns

1,2,3

Sout

1.5

-

1,4,5,6,7,8

Note 1: Absolute Specifications (0°C ≤ T_CASE≤ +tbd°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.

Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less

than 23.4 ohms for values of VOUT between 0V and 280mV.

Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.

Note 4: Slew rate measured from vil(ac) to vih(ac).

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Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as

measured from AC to AC. This is guaranteed by design and characterization.

Note 6: This represents the step size when the OCD is near 18 ohms at nominal conditions across all process cor-

ners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the

OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.

Output Slew rate load:

VTT

25 ohms

Reference

point

Output

(Vout)

Note 7: DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.

Note 8: Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in

tDQSQ and tQHS specification.

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3.4 IDD Specifications & Test Conditions

IDD Specifications(max)

DDR2 400

Symbol

DDR2 533

DDR2 667

Units

x4/x8

mA

IDD0

IDD1

100

110

6

110

120

130

7

120

6

mA

IDD2P

IDD2Q

IDD2N

mA

40

45

25

7

50

55

30

8

60

65

35

9

F

S

IDD3P

60

160

130

270

8

70

190

170

270

8

80

240

230

270

8

IDD3N

IDD4W

IDD4R

IDD5

Normal

IDD6

IDD7

Low power

5

280

320

340

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IDD Test Conditions

(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)

Symbol

IDD0

Conditions

Units

t

Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS min(IDD) ;

CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are

SWITCHING

mA

Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;

t

IDD1

CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH

between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W

mA

t

Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and address

mA

IDD2P

IDD2Q

IDD2N

bus inputs are STABLE; Data bus inputs are FLOATING

t

Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

t

Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

t

mA

Active power-down current; All banks open; CK = CK(IDD); CKE is

LOW; Other control and address bus inputs are STABLE; Data bus inputs

are FLOATING

Fast PDN Exit MRS(12) = 0

Slow PDN Exit MRS(12) = 1

IDD3P

IDD3N

IDD4W

IDD4R

t

Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHING

mA

t

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK =

t

CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL

t

= 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid com-

mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W

t

Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is

HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

IDD5B

IDD6

mA

Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data

bus inputs are FLOATING

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =

t

RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is

IDD7

mA

HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-

tern is same as IDD4R; - Refer to the following page for detailed timing conditions

Note:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combina-

tions of EMRS bits 10 and 11.

5. Definitions for IDD

LOW is defined as Vin ≤ VILAC(max)

HIGH is defined as Vin ≥ VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and

inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.

Rev. 1.2 / Dec 2006

16

1HY5PS1G431(L)F

1HY5PS1G831(L)F

For purposes of IDD testing, the following parameters are to be utilized

DDR2-667

DDR2-533

DDR2-400

3-3-3

Parameter

5-5-5

5

4-4-4

4

Units

CL(IDD)

3

tCK

t

15

RCD(IDD)

ns

t

60

RC(IDD)

55

t

7.5

ns

RRD(IDD)-x4/x8

7.5

t

10

5

RRD(IDD)-x16

9

3

10

t

3.75

CK(IDD)

RASmin(IDD)

ns

t

45

70000

15

45

70000

15

40

t

70000

15

ns

RASmax(IDD)

t

RP(IDD)

t

75

RFC(IDD)-256Mb

RFC(IDD)-512Mb

105

127.5

197.5

t

127.5

197.5

127.5

197.5

RFC(IDD)-1Gb

RFC(IDD)-2Gb

Detailed IDD7

The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.

Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation

t

All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control and address bus

inputs are STABLE during DESELECTs. IOUT = 0mA

Timing Patterns for 4 bank devices x4/ x8/ x16

-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D

-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D

-DDR2-533 5/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

Timing Patterns for 8 bank devices x4/8

-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7

-DDR2-533 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

Timing Patterns for 8 bank devices x16

-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

-DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D

Rev. 1.2 / Dec 2006

17

1HY5PS1G431(L)F

1HY5PS1G831(L)F

3.5. Input/Output Capacitance

DDR2 400

DDR2 533

DDR2 667

DDR2 800

Parameter

Symbol

Units

Min

Max

2.0

Min

1.0

x

Max

2.0

Input capacitance, CK and CK

CCK

CDCK

CI

1.0

x

pF

Input capacitance delta, CK and CK

0.25

2.0

0.25

2.0

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS, DQS

Input/output capacitance delta, DQ, DM, DQS, DQS

1.0

x

1.0

x

CDI

0.25

4.0

0.25

3.5

CIO

2.5

x

2.5

x

CDIO

0.5

4. Electrical Characteristics & AC Timing Specification

( 0 ℃ ≤ T

≤ 95℃; V

= 1.8 V +/- 0.1V; V = 1.8V +/- 0.1V)

CASE

DDQ DD

Refresh Parameters by Device Density

Parameter

Symbol

256Mb 512Mb 1Gb

2Gb

4Gb

Units

Refresh to Active/Refresh command

time

tRFC

75

105

127.5

195

327.5

ns

0 ℃≤ T_CASE≤ 95℃

85℃＜ T_CASE≤ 95℃

7.8

ns

Average periodic refresh interval

tREFI

3.9

DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin

Speed

Bin(CL-tRCD-tRP)

Parameter

CAS Latency

tRCD

DDR2-667

DDR2-533

DDR2-400

Units

5-5-5

min

5

4-4-4

min

4

3-3-3

min

3

tCK

ns

15

tRPNote1

tRAS

15

ns

45

40

ns

tRC

60

55

ns

Note 1: 8 bank device Precharge All Allowance : tRP for a Precharge All command for and 8 Bank device

will equal to tRP+1*tCK, where tRP are the values for a single bank prechrarge, which are shown in the

above table.

Rev. 1.2 / Dec 2006

18

1HY5PS1G431(L)F

1HY5PS1G831(L)F

Timing Parameters by Speed Grade

DDR2-400

DDR2-533

Symbol

Unit

Note

Parameter

min

-600

-500

0.45

max

+600

+500

0.55

-

min

-500

-450

0.45

max

+500

+450

0.55

-

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

tAC

ps

tDQSCK

tCH

tCK

ps

CK low-level width

tCL

tHP

min(tCL,

tCH)

min(tCL,

tCH)

11,12

CK half period

Clock cycle time, CL=x

tCK

5000

150

275

0.6

8000

3750

100

225

0.6

8000

ps

15

DQ and DM input setup time

tDS

-

6,7,8,20

6,7,8,21

DQ and DM input hold time

tDH

-

ps

Control & Address input pulse width for each input

DQ and DM input pulse width for each input

Data-out high-impedance time from CK/CK

tIPW

tDIPW

tHZ

-

tCK

ps

0.35

-

0.35

-

tAC max

18

tLZ

(DQS)

DQS low-impedance time from CK/CK

DQ low-impedance time from CK/CK

tAC min

tAC max

tAC min

tAC max

ps

tLZ

(DQ)

2*tAC min

18

DQS-DQ skew for DQS and associated DQ signals

DQ hold skew factor

tDQSQ

tQHS

tQH

-

350

-

300

ps

13

12

450

400

DQ/DQS output hold time from DQS

Write command to first DQS latching transition

DQS input high pulse width

tHP - tQHS

WL - 0.25

0.35

0.2

-

tHP - tQHS

WL - 0.25

0.35

0.2

-

ps

tDQSS

tDQSH

tDQSL

tDSS

WL + 0.25

tCK

ps

-

DQS input low pulse width

-

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Mode register set command cycle time

Write postamble

-

tDSH

tMRD

tWPST

tWPRE

tIS

0.2

-

0.2

-

2

0.4

0.6

-

0.4

0.6

-

10

Write preamble

0.35

350

0.35

250

Address and control input setup time

Address and control input hold time

Read preamble

-

5,7,9,23

tIH

475

-

375

-

ps

tRPRE

tRPST

0.9

1.1

0.6

0.9

1.1

0.6

tCK

Read postamble

0.4

Active to active command period for 1KB page size

products

tRRD

7.5

-

7.5

-

ns

4

Active to active command period for 2KB page size

products

tRRD

tFAW

10

-

10

-

ns

Four Active Window for 1KB page size products

37.5

Rev. 1.2 / Dec 2006

19

1HY5PS1G431(L)F

1HY5PS1G831(L)F

-Continued

DDR2-400

DDR2-533

Symbol

Unit

Note

Parameter

min

50

2

max

min

max

Four Active Window for 2KB page size products

CAS to CAS command delay

tFAW

tCCD

tWR

-

50

2

-

tCK

ns

Write recovery time

15

-

15

-

Auto precharge write recovery + precharge time

Internal write to read command delay

Internal read to precharge command delay

Exit self refresh to a non-read command

Exit self refresh to a read command

tDAL

WR+tRP*

10

WR+tRP*

7.5

tCK

ns

14

24

3

tWTR

tRTP

7.5

ns

tXSNR

tXSRD

tRFC + 10

200

tRFC + 10

200

ns

-

tCK

Exit precharge power down to any non-read

command

tXP

2

tCK

Exit active power down to read command

tXARD

tXARDS

1

Exit active power down to read command

(Slow exit, Lower power)

6 - AL

1, 2

CKE minimum pulse width

(high and low pulse width)

t

3

2

3

2

tCK

ns

CKE

t

ODT turn-on delay

ODT turn-on

2

AOND

tAC(max)+

1

t

tAC(min)

tAC(max)+1

tAC(min)

16

AON

2tCK+tAC(

max)

2tCK+tAC(

max)+1

t

ODT turn-on(Power-Down mode)

tAC(min)+2

ns

AONPD

+1

t

ODT turn-off delay

ODT turn-off

2.5

tCK

ns

AOFD

tAC(max)+

0.6

tAC(max)+

0.6

t

tAC(min)

17

AOF

2.5tCK+tAC

(max)+1

2.5tCK+tA

C(max)+1

t

ODT turn-off (Power-Down mode)

tAC(min)+2

ns

AOFPD

ODT to power down entry latency

ODT power down exit latency

OCD drive mode output delay

tANPD

tAXPD

tOIT

3

8

0

3

8

0

tCK

ns

12

Minimum time clocks remains ON after CKE

asynchronously drops LOW

tDelay

tIS+tCK+tIH

ns

15

Rev. 1.2 / Dec 2006

20

1HY5PS1G431(L)F

1HY5PS1G831(L)F

DDR2-667

Symbol

Unit

Note

Parameter

min

-450

-400

0.45

max

+450

+400

0.55

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

tAC

ps

tDQSCK

tCH

tCK

CK low-level width

tCL

min(tCL,

tCH)

CK half period

tHP

-

ps

11,12

Clock cycle time, CL=x

tCK

3000

50

8000

ps

15

DQ and DM input setup time

tDS

-

6,7,8,20

6,7,8,21

DQ and DM input hold time

tDH

175

0.6

0.35

-

ps

Control & Address input pulse width for each input

DQ and DM input pulse width for each input

Data-out high-impedance time from CK/CK

tIPW

tDIPW

tHZ

-

tCK

ps

-

tAC max

18

tLZ

(DQS)

DQS low-impedance time from CK/CK

DQ low-impedance time from CK/CK

tAC min

tAC max

ps

tLZ

(DQ)

2*tAC min

18

DQS-DQ skew for DQS and associated DQ signals

DQ hold skew factor

tDQSQ

tQHS

-

240

ps

13

12

340

DQ/DQS output hold time from DQS

Write command to first DQS latching transition

DQS input high pulse width

tQH

tHP - tQHS

WL - 0.25

0.35

-

ps

tDQSS

tDQSH

tDQSL

tDSS

WL + 0.25

tCK

ps

-

DQS input low pulse width

0.35

-

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Mode register set command cycle time

Write postamble

0.2

-

tDSH

0.2

-

tMRD

tWPST

tWPRE

2

-

0.4

0.6

10

*^W: t^rR^iteA^pS^re(^am^mi^bn^le) , tRC(min) specification for DDR2-400 4-4-4 is 45ns, 60ns respectively.

0.35

-

Address and control input setup time

Address and control input hold time

Read preamble

tIS

150

275

0.9

0.4

45

-

5,7,9,22

tIH

-

ps

5,7,9,23

tRPRE

tRPST

tRAS

tRRD

tFAW

1.1

tCK

ns

19

3

Read postamble

0.6

Activate to precharge command

70000

Active to active command period for 1KB page size products

Active to active command period for 2KB page size products

Four Active Window for 1KB page size products

7.5

10

-

ns

4

ns

4

37.5

ns

Rev. 1.2 / Dec 2006

21

1HY5PS1G431(L)F

1HY5PS1G831(L)F

-Continued

DDR2-667

Symbol

Unit

Note

Parameter

min

max

Four Active Window for 2KB page size products

CAS to CAS command delay

tFAW

50

-

ns

tCK

ns

tCCD

tWR

2

Write recovery time

15

-

Auto precharge write recovery + precharge time

Internal write to read command delay

Internal read to precharge command delay

Exit self refresh to a non-read command

Exit self refresh to a read command

tDAL

WR+tRP

tCK

ns

14

3

tWTR

tRTP

tXSNR

tXSRD

tXP

7.5

ns

tRFC + 10

ns

200

2

-

tCK

Exit precharge power down to any non-read command

Exit active power down to read command

tXARD

2

1

Exit active power down to read command

(Slow exit, Lower power)

tXARDS

6 - AL

3

tCK

1, 2

CKE minimum pulse width

(high and low pulse width)

t

tCK

CKE

t

ODT turn-on delay

ODT turn-on

2

tCK

ns

AOND

t

tAC(min)

tAC(max)+0.7

6,16

AON

2tCK+tAC(max)

+1

t

ODT turn-on(Power-Down mode)

tAC(min)+2

ns

AONPD

t

ODT turn-off delay

ODT turn-off

2.5

tCK

ns

AOFD

t

tAC(min)

tAC(max)+ 0.6

17

AOF

2.5tCK+tAC(ma

x)+1

t

ODT turn-off (Power-Down mode)

tAC(min)+2

ns

AOFPD

ODT to power down entry latency

ODT power down exit latency

OCD drive mode output delay

tANPD

tAXPD

tOIT

3

8

0

tCK

ns

12

Minimum time clocks remains ON after CKE asynchronously

drops LOW

tDelay

tIS+tCK+tIH

ns

15

Rev. 1.2 / Dec 2006

22

1HY5PS1G431(L)F

1HY5PS1G831(L)F

General notes, which may apply for all AC parameters

1. Slew Rate Measurement Levels

a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for

single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between

DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not

necessarily tested on each device.

b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to

VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to

CK - CK = +500 mV

(250mV to -500 mV for falling egdes).

c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or

between DQS and DQS for differential strobe.

2. DDR2 SDRAM AC timing reference load

The following figure represents the timing reference load used in defining the relevant timing parameters of

the part. It is not intended to be either a precise representation of the typical system environment nor a depic-

tion of the actual load presented by a production tester. System designers will use IBIS or other simulation

tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their pro-

duction test conditions (generally a coaxial transmission line terminated at the tester electronics).

VDDQ

DQ

DQS

Output

DUT

V_TT= V_DDQ/2

RDQS

Timing

reference

point

25Ω

AC Timing Reference Load

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-

ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement

(e.g. DQS) signal.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown below.

VDDQ

DUT

DQ

Output

DQS, DQS

V_TT= V_DDQ/2

RDQS, RDQS

25Ω

Test point

Slew Rate Test Load

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the

setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system

design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single

Rev. 1.2 / Dec 2006

23

1HY5PS1G431(L)F

1HY5PS1G831(L)F

VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and

its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.

Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must

be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.

t

DQSL

DQSH

DQS

DQS/

DQS

t

WPST

WPRE

V

(dc)

V

(ac)

IH

DQ

DM

D

t

D

t

V

(ac)

V

(dc)

IL

t

DH

DS

V

(dc)

V

(ac)

IH

DMin

(ac)

DMin

V

IL

V

(dc)

IL

Figure -- Data input (write) timing

t

CL

CH

CK

CK/CK

DQS

DQS/DQS

DQ

t

RPRE

RPST

Q

t

DQSQmax

t

DQSQmax

t

QH

Figure -- Data output (read) timing

5. AC timings are for linear signal transitions. See System Derating for other signal transitions.

6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They

may be guaranteed by device design or tester correlation.

7. All voltages referenced to VSS.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-

ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full

voltage range specified.

Rev. 1.2 / Dec 2006

24

1HY5PS1G431(L)F

1HY5PS1G831(L)F

Specific Notes for dedicated AC parameters

1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be

used for fast active power down exit timing. tXARDS is expected to be used for slow active power down

exit timing where a lower power value is defined by each vendor data sheet.

2. AL = Additive Latency

3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and

tRAS(min) have been satisfied.

4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency

5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for

other slew rate values.

6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0

V/ns. See System Derating for other slew rate values.

7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS

signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single

ended mode. See System Derating for other slew rate values.

8. tDS and tDH derating

tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table)

DQS, DQS Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

0.8 V/ns

△tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD

S

H

S

H

S

H

S

-

H

-

S

-

H

-

S

-

H

-

S

-

H

-

S

-

H

S

-

H

2.0 125 45 125 45 +125 +45

-

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

83

0

-

21

0

-

83

0

21 +83 +21 95

33

12

-2

-

0

12

1

24

13

-1

24

10

-7

-

DQ

Slew

rate

-11 -14 -11 -14

25

11

-7

22

5

-

-25 -31 -13 -19

23

5

17

-6

-

-43 -54 -31 -42 -42 -19

-8

17

-7

6

-

V/ns

-

-67 -83

-110 -125

-175 -188

-

-43 -59 -31 -47 -19 -35

-23

5

-11

-

-74 -89 -62 -77 -50 -65 -38 -53

-127 -140 -115 -128 -103 -116

-

1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating

value listed in Table x.

Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing

of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and

the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac

region’, use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere

between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for

derating value(see Fig b.)

Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first

crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)

min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to

VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see

Fig d.)

Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time

of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.

Rev. 1.2 / Dec 2006

25

1HY5PS1G431(L)F

1HY5PS1G831(L)F

These values are typically not subject to production test. They are verified by design and characterization.

Fig. a Illustration of nominal slew rate for tIS,tDS

CK,DQS

CK, DQS

t_IS,

t_DS

t_IH,

t_DH

t_IS,

t_DS

t_IH,

t_DH

V_DDQ

V_IH(ac)min

V_IH(dc)min

nominal

slew rate

V_REF(dc)

nominal

slew rate

V_IL(dc)max

V_REFto ac

region

V_IL(ac)max

Vss

Delta TF

Delta TR

Setup Slew Rate

Falling Signal

VREF(dc)-V_IL(ac)max

Delta TF

Setup Slew Rate

Rising Signal

V_IH(ac)min-VREF(dc)

Delta TR

=

Rev. 1.2 / Dec 2006

26

1HY5PS1G431(L)F

1HY5PS1G831(L)F

Fig. -b Illustration of tangent line for tIS,tDS

CK, DQS

t_IS,

t_DS

t_IH,

t_DH

t_IS,

t_DS

t_IH,

t_DH

V_DDQ

nominal

line

V_IH(ac)min

V_IH(dc)min

tangent

line

V_REF(dc)

Tangent

line

V_IL(dc)max

V_REFto ac

region

V_IL(ac)max

Nomial

line

Vss

Delta TR

Setup Slew Rate

Rising Signal

Tangent line[V_IH(ac)min-VREF(dc)]

Delta TR

=

Delta TF

Tangent line[VREF(dc)-V_IL(ac)max]

Delta TF

Setup Slew Rate

Falling Signal

=

Rev. 1.2 / Dec 2006

27

1HY5PS1G431(L)F

1HY5PS1G831(L)F

Fig. -c Illustration of nominal line for tIH, tDH

CK, DQS

t_IS,

t_DS

t_IH,

t_DH

t_IS,

t_DS

t_IH,

t_DH

V_DDQ

V_IH(ac)min

V_IH(dc)min

dc to V_REF

region

nominal

slew rate

V_REF(dc)

nominal

slew rate

V_IL(dc)max

V_IL(ac)max

Vss

Delta TR

Hold Slew Rate

Delta TF

V_IH(dc)min - V_REF(dc)

Delta TF

Hold Slew Rate

Rising Signal

VREF(dc)-V_IL(dc)max

Delta TR

=

Falling Signal

Rev. 1.2 / Dec 2006

28

1HY5PS1G431(L)F

1HY5PS1G831(L)F

Fig. -d Illustration of tangent line for tIH , tDH

CK, DQS

t_IS,

t_DS

t_IS,

t_DS

t_IH,

t_DH

t_IH,

t_DH

V_DDQ

V_IH(ac)min

nominal

line

V_IH(dc)min

tangent

line

V_REF(dc)

dc to V_REF

region

Tangent

line

nominal

line

V_IL(dc)max

V_IL(ac)max

Vss

Delta TR

Delta TF

Hold Slew Rate Tangent line[VREF(dc)-V_IL(ac)max]

=

Rising Signal

Delta TR

Tangent line[V_IH(ac)min-VREF(dc)]

Delta TF

Hold Slew Rate

Falling Signal

=

Rev. 1.2 / Dec 2006

29

1HY5PS1G431(L)F

1HY5PS1G831(L)F

9. tIS and tIH (input setup and hold) derating

tIS, tIH Derating Values

CK, CK Differential Slew Rate

1.5 V/ns

2.0 V/ns

tIS

1.0 V/ns

tIS tIH

△

tIH

tIS

tIH

△

Units

Notes

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.25

0.2

0.15

0.1

+187

+179

+167

+150

+125

+83

+94

TBD

ps

1

+89

+83

+75

+45

+21

0

+0

-11

-14

Command /

Address

Slew

-25

-31

-43

-54

rate(V/ns)

-67

-83

-100

-150

-223

-250

-500

-750

-1250

-125

-188

-292

-375

-500

-708

-1125

1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the

datasheet value to the derating value listed in above Table.

Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

V

(dc) and the first crossing of V (ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as

REF

IH

the slew rate between the last crossing of V_REF(dc) and the first crossing of V (ac)max. If the actual signal

IL

is always earlier than the nominal slew rate for line between shaded ‘V

(dc) to ac region’, use nominal

REF

slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere

between shaded ‘V

level to dc level is used for derating value(see Fig b.)

(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac

REF

Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

VIL(dc)max and the first crossing of V

(dc). Hold(tIH) nominal slew rate for a falling signal is defined as

REF

the slew rate between the last crossing of V

(dc). If the actual signal signal is always later than the nom-

REF

inal slew rate line between shaded ‘dc to V

(dc) region’, use nominal slew rate for derating value(see

Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to

(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to V (dc) level is

V

REF

used for derating value(see Fig d.)

Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached

V

(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transi-

IH/IL

tion and reach V

(ac).

IH/IL

For slew rates in between the values listed in table, the derating values may obtained by linear interpola-

tion.

Rev. 1.2 / Dec 2006

30

1HY5PS1G431(L)F

1HY5PS1G831(L)F

These values are typically not subject to production test. They are verified by design and characterization.

10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value

for this parameter, but system performance (bus turnaround) will degrade accordingly.

11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as pro-

vided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH).

For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock

source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.

12. t QH = t HP – t QHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH,

tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the

next transition, both of which are, separately, due to data pin skew and output pattern effects, and

p-

channel to n-channel variation of the output drivers.

13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of

the output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any

given cycle.

14. t DAL = (nWR) + ( tRP/tCK):

For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the

application clock period. nWR refers to the t WR parameter stored in the MRS.

Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns)

clocks =4 +(4)clocks=8clocks.

15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In

case of clock frequency change during precharge power-down, a specific procedure is required as

described in section 2.9.

16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn

on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

17. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are

referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or

begins driving (tLZ). Below figure shows a method to calculate the point when device is no longer driving

(tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage mea-

surement points are not critical as long as the calculation is consistenet.

19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when

the device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to

calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Fig-

Rev. 1.2 / Dec 2006

31

1HY5PS1G431(L)F

1HY5PS1G831(L)F

ure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driv-

ing (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are

not critical as long as the calculation is consistent.

VOH + xmV

VTT + 2xmV

VTT + xmV

VOH + 2xmV

tHZ

tRPST end point

tRPRE begin point

VOL + 1xmV

VOL + 2xmV

VTT -xmV

VTT - 2xmV

tHZ , tRPST end point = 2*T1-T2

tLZ , tRPRE begin point = 2*T1-T2

20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input

signal crossing at the V (ac) level to the differential data strobe crosspoint for a rising signal, and from the

IH

input signal crossing at the V (ac) level to the differential data strobe crosspoint for a falling signal applied

IL

to the device under test.

21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input

signal crossing at the V (dc) level to the differential data strobe crosspoint for a rising signal and V (dc) to

IH

IL

the differential data strobe crosspoint for a falling signal applied to the device under test.

Differential Input waveform timing

DQS

tDS tDH

VDDQ

VIH(ac)min

VIH(dc)min

V_REF(dc)

VIL(dc)max

VIL(ac)max

V_SS

22. Input waveform timing is referenced from the input signal crossing at the V (ac) level for a rising signal

IH

and V (ac) for a falling signal applied to the device under test.

IL

23. Input waveform timing is referenced from the input signal crossing at the V (dc) level for a rising signal

IL

and V (dc) for a falling signal applied to the device under test.

IH

Rev. 1.2 / Dec 2006

32

1HY5PS1G431(L)F

1HY5PS1G831(L)F

5. Package Dimensions

Package Dimension(x4,x8)

68Ball Fine Pitch Ball Grid Array Outline

11.9 +/- 0.10

A1 Ball Mark

1.20 Max.

0.34 +/- 0.10

< Top View>

A1 Ball Mark

1

2

3

7 8 9

0.80

84 - Φ.50

0.80 X 8 = 6.40

Note: All dimensions are in Millimeters.

< Bottom View>

Rev. 1.2 / Dec 2006

33


型号：	HY5PS1G831F-C4
厂家：	HYNIX SEMICONDUCTOR
描述：	1Gb DDR2 SDRAM 1GB DDR2 SDRAM 存储内存集成电路动态存储器双倍数据速率时钟
文件：	总33页 (文件大小：524K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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