HY5PS561621ALFP-C4 [HYNIX]
256Mb DDR2 SDRAM; 256MB DDR2 SDRAM型号: | HY5PS561621ALFP-C4 |
厂家: | HYNIX SEMICONDUCTOR |
描述: | 256Mb DDR2 SDRAM |
文件: | 总34页 (文件大小:573K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HY5PS561621A(L)FP
256Mb DDR2 SDRAM
HY5PS561621A(L)FP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
Revision History
Rev.
History
Draft Date
0.1
0.2
June. 2005
Initial data sheet release.
Removed all contents on x4/8 Org.
Updated IDD Spec.
Oct. 2005
0.3
0.4
July 2006
Sep. 2006
Removed improper note in ODT DC spec.
Timing Parameters Table Modified
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Feaures
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default chracteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
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1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the
clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
Ordering Information
Operating Frequency
Speed Bin
tCK(ns)
CL
3
tRCD
tRP
3
Unit
Part No.
Organization
16Mx16
Package
E3
Clk
5
3.75
3
3
4
5
5
HY5PS561621A(L)FP-X*
Lead free**
C4
Y5
S5
Clk
Clk
Clk
4
4
Note:
1. -X* is the speed bin, refer to the Operation Frequency table for
complete Part No.
2. Hynix Lead-free products are compliant to RoHS.
5
5
2.5
5
5
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1HY5PS561621A(L)FP
1.2 Pin Configuration & Address Table
16Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
7
8
3
9
1
2
VSSQ
UDQS
VSS
VDDQ
VDD
NC
A
B
C
D
E
F
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSQ
DQ8
UDM
VDDQ
DQ11
VSS
DQ15
VDDQ
DQ13
VDDQ
DQ7
DQ14
VDDQ
DQ12
VDD
VSSQ
DQ9
VSSQ
NC
VSSQ
LDQS
VSSQ
DQ0
LDM
DQ6
VSSQ
DQ1
VSSQ
VDDQ
DQ3
VDDQ
DQ5
VDDQ
DQ4
G
H
VSSQ
VSSDL
RAS
CK
CK
VSS
WE
VDD
ODT
VDDL
VREF
CKE
J
K
CAS
A2
CS
A0
A4
A8
NC
BA1
A1
L
M
N
P
NC
VSS
VDD
BA0
A10
A3
VDD
VSS
A6
A5
A11
NC
A9
A7
NC
R
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS
16Mx16
# of Bank
4
Bank Address
BA0, BA1
A10/AP
A0 - A12
A0-A8
Auto Precharge Flag
Row Address
Column Address
Page size
1 KB
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1HY5PS561621A(L)FP
1.3 PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and
SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank).
CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asyn-
chronous for SELF REFRESH exit. After VREF has become stable during the power on and initial-
CKE
Input
ization sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high
throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled
during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
Chip Select : All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
CS
Input
Input
On Die Termination Control : ODT(registered HIGH) enables on die termination resistance inter-
nal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS, RDQS,
and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/
UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode
Register(EMRS(1)) is programmed to disable ODT.
ODT
RAS, CAS, WE
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is
sampled High coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing. For x8 device, the function of DM or RDQS/ RDQS is enabled by EMRS command.
DM
(LDM, UDM)
Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE
command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank address also deter-
mines if the mode register or extended mode register is to be accessed during a MRS or EMRS
cycle.
BA0 - BA2
Input
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge command to determine
whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0-BA2. The address inputs also provide the
op code during MODE REGISTER SET commands.
A0 -A15
DQ
Input/
Data input / output : Bi-directional data bus
Output
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PIN
TYPE
DESCRIPTION
Data Strobe : Output with read data, input with write data. Edge aligned with read data, cen-
tered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds
to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the
EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in
single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS
to provide differential pair signaling to the system during both reads and wirtes. An EMRS(1)
control bit enables or disables all complementary data strobe signals.
DQS, (DQS)
(UDQS),(UDQS)
(LDQS),(LDQS)
(RDQS),(RDQS)
Input/
Output
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of
EMRS(1)
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of
EMRS(1)
x16 LDQS and UDQS
NC
VDDQ
VSSQ
VDDL
VSSDL
VDD
No Connect : No internal electrical connection is present.
DQ Power Supply: 1.8V +/- 0.1V
DQ Ground
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DLL Power Supply : 1.8V +/- 0.1V
DLL Ground
Power Supply : 1.8V +/- 0.1V
Ground
VSS
VREF
Reference voltage for inputs for SSTL interface.
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2. Maximum DC Ratings
2.1 Absolute Maximum DC Ratings
Symbol
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
Notes
VDD
- 1.0 V ~ 2.3 V
V
1
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
VIN, VOUT
TSTG
V
1
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions.
Please refer to JESD51-2 standard.
2.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
tOPER
0 to 95
°C
1,2
Operating Temperature
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
2. At tOPER 85~95℃, Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this temperature range
it must be reguired an EMRS command to change iself refresh rate.
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3. AC & DC Operating Conditons
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions (SSTL_1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
Typ.
Max.
VDD
VDDL
VDDQ
VREF
VTT
1.7
1.8
1.9
V
V
1
Supply Voltage
1.7
1.8
1.8
1.9
1,2
1,2
3,4
5
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
5. VTT of transmitting device must track VREF of receiving device.
3.1.2 ODT DC electrical characteristics
PARAMETER/CONDITION
SYMBOL
MIN
NOM
MAX UNITS NOTES
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm
Deviation of VM with respect to VDDQ/2
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
delta VM
60
120
40
75
150
50
90
180
60
ohm
ohm
ohm
%
1
1
1
1
-6
+6
Note
1. Test condition for Rtt measurements
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and
I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
VIH (ac) - VIL (ac)
Rtt(eff) =
I(VIH (ac)) - I(VIL (ac))
Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.
2 x Vm
- 1
x 100%
delta VM =
VDDQ
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3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(dc)
VREF + 0.125
VDDQ + 0.3
V
dc input logic high
dc input logic low
VIL(dc)
- 0.3
VREF - 0.125
V
3.2.2 Input AC Logic Level
DDR2 400,533
DDR2 667,800
Symbol
Parameter
Units
Notes
Min.
Max.
Min.
Max.
VIH (ac)
VREF + 0.250
-
VREF + 0.200
-
-
V
V
ac input logic high
ac input logic low
V
IL (ac)
-
VREF - 0.250
VREF - 0.200
3.2.3 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
VSWING(MAX)
SLEW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
0.5 * VDDQ
1.0
V
V
1
1
1.0
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising
edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VSWING(MAX)
V
IL(dc) max
IL(ac) max
V
VSS
delta TF
delta TR
VREF - VIL(ac) max
delta TF
VIH(ac) min - VREF
delta TR
Falling Slew =
Rising Slew =
< Figure : AC Input Test Signal Waveform>
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3.2.4 Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VID (ac)
0.5
VDDQ + 0.6
V
1
ac differential input voltage
ac differential cross point voltage
V
IX (ac)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS
and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK,
DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value
is equal to VIH(DC) - V IL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as
CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value
is equal to V IH(AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track
variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
3.2.5 Differential AC output parameters
Symbol
OX (ac)
Note:
Parameter
Min.
Max.
Units
Notes
V
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track
variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
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3.3 Output Buffer Characteristics
3.3.1 Output AC Test Conditions
Symbol
Parameter
SSTL_18 Class II
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
1. The VDDQ of the device under test is referenced.
3.3.2 Output DC Current Drive
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18
- 13.4
13.4
Units
mA
Notes
1, 3, 4
2, 3, 4
mA
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ
-
280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive
current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18
receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm
load line to define a convenient driver current for measurement.
3.3.3 OCD defalut characteristics
Description
Parameter
Min
Nom
Max
Unit
ohms
ohms
ohms
V/ns
Notes
Output impedance
-
-
-
1.5
4
1
6
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
0
0
1,2,3
Sout
1.5
-
5
1,4,5,6,7,8
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Note
1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/Ioh must be
less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink
dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC
to AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/variations and
represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the OCD impedance is 18 ohms
+/- 0.75 ohms under nominal conditions.
VTT
Output Slew rate load:
25 ohms
Reference
point
Output
(Vout)
7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and
tQHS specification.
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3.4 IDD Specifications & Test Conditions
IDD Specifications(x16) (TCASE : 0 to 95oC)
DDR2 800
@CL5
DDR2 667
@CL5
DDR2 533
@CL4
DDR2 400
Symbol
Units
Note
@CL3
85
105
8
80
100
8
75
90
7
70
mA
IDD0
IDD1
80
6
mA
mA
IDD2P
40
45
35
35
60
200
190
120
4
35
40
35
35
55
180
150
120
4
30
35
30
30
50
160
130
115
4
25
30
30
30
45
140
120
110
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4W
IDD4R
IDD5B
1
1
IDD6(Normal)
IDD6(Low)
IDD7
2
2
2
2
230
220
210
200
Notes :
1. IDD6 current alues are guaranted up to Tcase of 85oC max.
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1HY5PS561621A(L)FP
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
IDD0
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS min(IDD)
; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
mA
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
t
t
IDD1
CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and
IDD2P
IDD2Q
IDD2N
mA
mA
mA
address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
IDD4R
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
mA
mA
mA
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL =
t
t
t
t
t
t
CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS
is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
t
t
t
t
AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD);
CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
IDD7
mA
Note:
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
6. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for
address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ
signals not including masks or strobes.
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
For purposes of IDD testing, the following parameters are to be utilized
Speed
Bin
(CL-tRCD-tRP)
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
5-5-5
6-6-6
6
4-4-4
5-5-5
5
3-3-3
4-4-4
4
3-3-3
3
CL(IDD)
5
4
3
tCK
t
12.5
15
12
15
11.25
15
15
RCD(IDD)
ns
ns
t
57.25
7.5
60
57
60
56.25
7.5
60
55
RC(IDD)
RRD(IDD)-x4/x8
t
ns
ns
7.5
7.5
7.5
7.5
7.5
t
RRD(IDD)-x16
10
10
10
3
10
3
10
10
10
5
t
2.5
2.5
3.75
3.75
CK(IDD)
RASmin(IDD)
ns
ns
t
45
70000
12.5
75
45
70000
15
45
70000
12
45
70000
15
45
70000
11.25
75
45
70000
15
40
70000
15
t
ns
ns
ns
ns
ns
RASmax(IDD)
t
RP(IDD)
t
t
75
75
75
75
75
RFC(IDD)-256Mb
RFC(IDD)-512Mb
105
105
105
105
105
105
105
t
127.5
127.5
127.5
127.5
127.5
127.5
127.5
RFC(IDD)-1Gb
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
t
t
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
3.5. Input/Output Capacitance
DDR2- 400
DDR2- 533
DDR2 667
DDR2 800
Parameter
Symbol
Units
Min
1.0
x
Max
2.0
Min
1.0
x
Max
2.0
Min
1.0
x
Max
2.0
Input capacitance, CK and CK
CCK
CDCK
CI
pF
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
0.25
2.0
0.25
2.0
0.25
1.75
0.25
3.5
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
1.0
x
1.0
x
CDI
0.25
4.0
0.25
3.5
CIO
2.5
x
2.5
x
2.5
x
CDIO
0.5
0.5
0.5
4. Electrical Characteristics & AC Timing Specification
( 0 ℃ ≤ TCASE ≤ 95℃; VDDQ = 1.8 V +/- 0.1V; VDD = 1.8V +/- 0.1V)
Refresh Parameters
Parameter
Symbol
Spec
75
Units
Refresh to Active/Refresh command time
tRFC
ns
ns
ns
0 ℃≤ TCASE ≤ 85℃
7.8
Average periodic refresh interval
tREFI
85℃ < TCASE ≤ 95℃
3.9
DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin
Speed
DDR2-800
5-5-5
min
DDR2-667
DDR2-533
DDR2-400
Units
Bin(CL-tRCD-tRP)
5-5-5
min
5
4-4-4
min
4
3-3-3
min
5
Parameter
CAS Latency
tRCD
5
tCK
ns
ns
ns
12.5
15
15
15
tRP
12.5
15
15
15
tRAS
45
45
45
40
tRC
57.25
60
60
55
ns
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1HY5PS561621A(L)FP
Timing Parameters by Speed Grade
(Refer to notes for information related to this table at the following pages of this table)
DDR2-400
DDR2-533
Symbol
Unit
Note
Parameter
min
max
min
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-600
+600
-500
+500
ps
ps
tDQSCK
tCH
-500
+500
-450
+450
0.45
0.55
0.45
0.55
tCK
tCK
ps
CK low-level width
tCL
0.45
0.55
0.45
0.55
CK half period
tHP
min(tCL,tCH)
-
min(tCL,tCH)
-
11,12
15
Clock cycle time, CL=x
tCK
5000
8000
3750
8000
ps
DQ and DM input setup time(differential strobe)
DQ and DM input hold time(differential strobe)
DQ and DM input setup time(single ended strobe)
DQ and DM input hold time(single ended strobe)
tDS(base)
tDH(base)
tDS
150
-
100
-
ps
6,7,8,20
6,7,8,21
6,7,8,20
6,7,8,21
275
-
225
-
ps
25
-
-25
-
ps
tDH
25
-
-25
-
ps
Control & Address input pulse width for each input tIPW
0.6
-
-
0.6
-
-
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDIPW
tHZ
0.35
0.35
-
tAC max
tAC max
tAC max
350
-
tAC max
tAC max
tAC max
300
18
18
18
13
12
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC min
ps
2*tAC min
2*tAC min
ps
-
-
ps
-
450
-
400
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
First DQS latching transition to associated clock
edge
tDQSS
-0.25
+ 0.25
-0.25
+ 0.25
tCK
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
-
0.35
0.35
0.2
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
-
-
tDSH
0.2
-
-
0.2
-
-
tMRD
tWPST
tWPRE
tIS(base)
tIH(base)
tRPRE
tRPST
tRRD
2
2
0.4
0.6
-
0.4
0.6
-
10
Write preamble
0.35
350
475
0.9
0.35
250
375
0.9
Address and control input setup time
Address and control input hold time
Read preamble
-
-
5,7,9,23
5,7,9,23
-
-
ps
1.1
0.6
-
1.1
0.6
-
tCK
tCK
ns
Read postamble
0.4
0.4
Active to active command period
Four Activate Window
7.5
7.5
4
tFAW
37.5
2
-
37.5
2
-
ns
CAS to CAS command delay
Write recovery time
tCCD
tCK
ns
tWR
15
-
-
-
15
-
-
-
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
tDAL
WR+tRP
10
WR+tRP
7.5
tCK
ns
14
24
3
tWTR
tRTP
7.5
7.5
ns
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1HY5PS561621A(L)FP
-Continue-
DDR2-400
DDR2-533
Symbol
Unit
Note
Parameter
min
max
min
tRFC + 10
200
max
Exit self refresh to a non-read command
Exit self refresh to a read command
tXSNR
tXSRD
tRFC + 10
200
ns
-
-
-
-
tCK
Exit precharge power down to any non-read
command
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
1
Exit active power down to read command
(Slow exit, Lower power)
6 - AL
6 - AL
1, 2
CKE minimum pulse width
(high and low pulse width)
t
3
2
3
2
tCK
tCK
ns
27
CKE
t
ODT turn-on delay
ODT turn-on
2
2
AOND
tAC(max)+
1
tAC(max)+
1
t
tAC(min)
tAC(min)
16
AON
2tCK+
tAC(max)+
1
2tCK+
tAC(max)+
1
t
ODT turn-on(Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AONPD
t
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
AOFD
tAC(max)+
0.6
tAC(max)+
0.6
t
tAC(min)
tAC(min)
17
AOF
2.5tCK+
tAC(max)+
1
2.5tCK+
tAC(max)+
1
t
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
ns
15
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
DDR2-667
min
DDR2-800
Symbol
Unit
Note
Parameter
max
+450
+400
0.55
min
-400
-350
0.45
0.45
max
+400
+350
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
0.55
0.55
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
-
-
ps
11,12
Clock cycle time, CL=x
tCK
3000
100
8000
2500
50
ps
ps
15
DQ and DM input setup time
tDS(base)
tDH(base)
tIPW
-
-
6,7,8,20
6,7,8,21
DQ and DM input hold time
175
-
125
-
ps
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
0.6
-
0.6
-
tCK
tCK
ps
tDIPW
tHZ
0.35
-
-
0.35
-
-
tAC max
tAC max
18
18
18
13
12
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
2*tAC min
-
tAC max
tAC min
2*tAC min
-
tAC max
ps
tAC max
tAC max
ps
240
200
ps
-
340
-
300
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
- 0.25
0.35
0.35
0.2
-
tHP - tQHS
- 0.25
0.35
0.35
0.2
-
ps
First DQS latching transition to associated clock edge tDQSS
+ 0.25
+ 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
-
-
-
-
-
-
tDSH
0.2
-
0.2
-
tMRD
2
-
0.6
-
2
-
0.6
-
tWPST
tWPRE
tIS(base)
tIH(base)
tRPRE
tRPST
tRAS
0.4
0.4
10
Write preamble
0.35
200
0.35
175
Address and control input setup time
Address and control input hold time
Read preamble
-
-
5,7,9,22
275
-
250
-
ps
5,7,9,23
0.9
1.1
0.6
70000
0.9
1.1
0.6
70000
tCK
tCK
ns
19
19
3
Read postamble
0.4
0.4
Activate to precharge command
45
45
Active to active command period for 1KB page size
products
tRRD
7.5
-
-
7.5
-
-
ns
4
Four Activate Window
tFAW
tCCD
tWR
37.5
37.5
ns
tCK
ns
CAS to CAS command delay
2
15
2
15
Write recovery time
-
-
-
-
-
-
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
tWTR
tRTP
WR+tRP
7.5
WR+tRP
7.5
tCK
ns
14
3
7.5
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
-
-
-
-
tCK
tCK
Exit precharge power down to any non-read command tXP
2
2
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
-Continue-
DDR2-667
DDR2-800
Symbol
Unit
Note
Parameter
min
max
min
max
Exit active power down to read command
tXARD
2
2
tCK
tCK
1
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
7 - AL
8 - AL
1, 2
CKE minimum pulse width
(high and low pulse width)
t
3
2
3
2
tCK
tCK
ns
CKE
t
ODT turn-on delay
2
2
AOND
tAC(max)
+0.7
tAC(max)
+0.7
t
ODT turn-on
tAC(min)
tAC(min)
6,16
17
AON
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
t
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
ns
tCK
ns
AONPD
t
2.5
2.5
2.5
AOFD
tAC(max)+
0.6
tAC(max)
+0.6
t
ODT turn-off
tAC(min)
tAC(min)
AOF
tAC(min)
+2
2.5tCK+
tAC(max)+1
tAC(min)
+2
2.5tCK+
tAC(max)+1
t
ODT turn-off (Power-Down mode)
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tIS+tCK
+tIH
tDelay
tIS+tCK+tIH
ns
15
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.
For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV.
Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from
VIH(dc) and VIL(ac) for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV(250mV
to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for
differential strobe.
2. DDR2 SDRAM AC timing reference load
The following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not
intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environ-
ment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester
electronics).
VDDQ
DQ
DQS
DQS
Output
DUT
VTT = VDDQ/2
RDQS
RDQS
Timing
reference
point
25Ω
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage
level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown below.
VDDQ
DUT
DQ
Output
DQS, DQS
VTT = VDDQ/2
RDQS, RDQS
25Ω
Test point
Slew Rate Test Load
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2
SDRAM pin timings are measured is mode dependent. In single
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This
distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled
via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper
operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
V
(dc)
V
(ac)
IH
IH
DQ
DM
D
D
D
t
D
t
V
(ac)
V
(dc)
IL
IL
t
t
DS
DH
DH
DS
V
(dc)
V
(ac)
IH
IH
DMin
DMin
DMin
(ac)
DMin
V
IL
V
(dc)
IL
Figure -- Data input (write) timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active
power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is
defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been
satisfied.
4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values.
6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. See System
Derating for other slew rate values.
7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a
differen tial slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System
Derating for other slew rate values.
tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table)
DQS, DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
125 45 125 45 +125 +45
-
-
-
-
-
-
-
-
-
-
-
-
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
83
0
-
21
0
-
83
0
21 +83 +21 95
33
12
-2
-
-
-
-
-
-
-
-
-
-
-
0
0
0
12
1
24
13
-1
24
10
-7
-
-
-
-
-
-
-
DQ
Slew
rate
V/ns
-11 -14 -11 -14
25
11
-7
22
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-25 -31 -13 -19
23
5
17
-6
-
-
-
-
-
-
-
-
-
-
-
-
-
-31 -42 -42 -19
-8
17
-7
6
-
-
-
-
-
-
-
-
-
-
-43 -59 -31 -47 -19 -35
-23
5
-11
-
-
-
-
-
-
-74 -89 -62 -77 -50 -65 -38 -53
-127 -140 -115 -128 -103 -116
-
-
-
-
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating
value listed in above Table.
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and
the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac
region’, use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for
derating value(see Fig b.)
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first
crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)
min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to
VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see
Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first
crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)
min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to
VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see
Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the
time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Rev. 0.4 / Sep. 2006
25
1
1HY5PS561621A(L)FP
Fig. a Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VREF to ac
region
VIL(ac)max
Vss
Delta TF
Delta TR
Setup Slew Rate
Falling Signal
VREF(dc)-VIL(ac)max
Delta TF
Setup Slew Rate
Rising Signal
VIH(ac)min-VREF(dc)
Delta TR
=
=
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
Fig. -b Illustration of tangent line for tIS,tDS
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
nominal
line
VIH(ac)min
VIH(dc)min
tangent
line
VREF(dc)
VIL(dc)max
VIL(ac)max
Tangent
line
VREF to ac
region
Nomial
line
Vss
Delta TR
Setup Slew Rate
Rising Signal
Tangent line[VIH(ac)min-VREF(dc)]
Delta TR
=
Delta TF
Tangent line[VREF(dc)-VIL(ac)max]
Delta TF
Setup Slew Rate
Falling Signal
=
Rev. 0.4 / Sep. 2006
27
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1HY5PS561621A(L)FP
Fig. -c Illustration of nominal line for tIH, tDH
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
dc to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Hold Slew Rate
Delta TF
VIH(dc)min - VREF(dc)
Delta TF
Hold Slew Rate
Rising Signal
VREF(dc)-VIL(dc)max
Delta TR
=
=
Falling Signal
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
Fig. -d Illustration of tangent line for tIH , tDH
CK, DQS
CK, DQS
tIS,
tDS
tIS,
tDS
tIH,
tDH
tIH,
tDH
VDDQ
VIH(ac)min
nominal
line
VIH(dc)min
tangent
line
VREF(dc)
dc to VREF
region
Tangent
line
nominal
line
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max]
=
Rising Signal
Delta TR
Tangent line[VIH(ac)min-VREF(dc)]
Delta TF
Hold Slew Rate
Falling Signal
=
Rev. 0.4 / Sep. 2006
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1
1HY5PS561621A(L)FP
9. tIS and tIH (input setup and hold) derating
tIS, tIH Derating Values for DDR2 400, DDR2 533
CK, CK Differential Slew Rate
1.5 V/ns
2.0 V/ns
△tIS
1.0 V/ns
△tIH
+94
+89
+83
+75
+45
+21
0
△tIS
+217
+209
+197
+180
+155
+113
+30
△tIH
+124
+119
+113
+105
+75
△tIS
+247
+239
+227
+210
+185
+143
+60
△tIH
+124
+149
+143
+135
+105
+81
Units Notes
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+187
+179
+167
+150
+125
+83
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+0
+30
60
-11
-14
+19
+16
+49
+46
Command /
Address Slew
rate(V/ns)
-25
-31
+5
-1
+35
+29
-43
-54
-37
-53
-7
+6
-67
-83
-37
-53
-7
-23
-100
-150
-223
-250
-500
-750
-1250
-125
-188
-292
-375
-500
-708
-1125
-80
-95
-50
-65
-145
-255
-320
-495
-770
-1420
-158
-262
-345
-470
-678
-1095
-115
-225
-290
-465
-740
-1065
-128
-232
-315
-440
-648
TBD
tIS, tIH Derating Values for DDR2 667, DDR2 800
CK, CK Differential Slew Rate
2.0 V/ns
△tIS
1.5 V/ns
△tIS
1.0 V/ns
△tIH
+94
+89
+83
+75
+45
+21
0
△tIH
+124
+119
+113
+105
+75
△tIS
+210
+203
+193
+180
+160
+127
+60
△tIH
+154
+149
+143
+135
+105
+81
Units Notes
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+150
+143
+133
+120
+100
+67
0
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+30
60
-5
-14
+16
+55
+46
Command /
Address Slew
rate(V/ns)
-13
-31
-1
+47
+29
-22
-54
-24
+38
+6
-34
-83
-4
-53
-26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
Rev. 0.4 / Sep. 2006
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1HY5PS561621A(L)FP
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to the derating
value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and
the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line between shaded ‘VREF(dc) to
ac region’, use nominal slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for der-
ating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first cross-
ing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc). If the
actual signal signal is always later than the nominal slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for
derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc)
region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time of
the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH are = 50%
of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( t
JIT(crosstalk)) into the clock traces.
12. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both
of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as
well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle.
14. DAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application
clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.
tDAL = 4 + (15ns/3.75ns) clocks = 4+(4) clocks = 8 clocks.
15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock
frequency change during precharge power-down, a specific procedure is required as described in section 2.9.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
17. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are referenced to a
specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving (tLZ). Below figure
Rev. 0.4 / Sep. 2006
31
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1HY5PS561621A(L)FP
shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal
at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistenet.
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no
longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calculate these points when the device is
no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to calculate these points when the device
is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage
measurement points are not critical as long as the calculation is consistent.
VOH + xmV
VTT + 2xmV
VTT + xmV
VOH + 2xmV
tHZ
tHZ
tRPST end point
tRPRE begin point
VOL + 1xmV
VOL + 2xmV
VTT -xmV
VTT - 2xmV
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input signal crossing at the
VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level
to the differential data strobe crosspoint for a falling signal applied to the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the
VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint
for a falling signal applied to the device under test.
Differential Input waveform timing
DQS
DQS
tDS tDH
tDS tDH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
VSS
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling
signal applied to the device under test.
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling
signal applied to the device under test.
Rev. 0.4 / Sep. 2006
32
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1HY5PS561621A(L)FP
DQS
DQS
tIS
tIH
tIS
tIH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
VSS
24. tWTR is at least two clocks (2*tCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the
VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input sig-
nal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal
applied to the device under test. The DQS signal must be monotonic between VIL(dc)max and VIH(dc) min.
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the
VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input sig-
nal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal
applied to the device under test. The DQS signal must be monotonic between VIL(dc) max and VIH(dc) min.
27. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input
level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its
valid level during the time period of tIS + 2*tCK + tIH.
Rev. 0.4 / Sep. 2006
33
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1HY5PS561621A(L)FP
5. Package Dimensions
Package Dimension(x16)
84 Ball Fine Pitch Ball Grid Array Outline
8.00 +/- 0.10
A1 Ball Mark
1.20 Max.
0.34 +/- 0.05
A1 Ball Mark
1
2
3
7
8
9
84 - φ0.45 ± 0.05
0.80
0.80 x 8 = 6.40
<Bottom View>
note: all dimension units are Millimeters.
Rev. 0.4 / Sep. 2006
34
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