HY5V22F-55I_技术文档

HY57V283220T-I/ HY5V22F-I

4 Banks x 1M x 32Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V283220T-I / HY5V22F-I is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the mem-

ory applications which require wide data I/O and high bandwidth. HY57V283220T-I / HY5V22F-I is organized as

4banks of 1,048,576x32.

HY57V283220T-I / HY5V22F-I is offering fully synchronous operation referenced to a positive edge of the clock. All

inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to

achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

JEDEC standard 3.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM0,1,2 and 3

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY57V283220(L)T-5I

HY5V22(L)F-5I

4Banks x 1Mbits

x32

86TSOP-II

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

LVTTL

90Ball FBGA

HY57V283220(L)T-55I

HY5V22(L)F-55I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

LVTTL

HY57V283220(L)T-6I

HY5V22(L)F-6I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-7I

HY5V22(L)F-7I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-8I

HY5V22(L)F-8I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-PI

HY5V22(L)F-PI

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-SI

HY5V22(L)F-SI

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.6/Nov. 02

HY57V283220T-I / HY5V22F-I

PIN CONFIGURATION ( HY57V283220T-I Series)

V D D

D Q 0

V D D Q

D Q 1

D Q 2

V S S Q

D Q 3

D Q 4

8 6

8 5

8 4

8 3

8 2

8 1

8 0

7 9

7 8

7 7

7 6

7 5

7 4

7 3

7 2

7 1

7 0

6 9

6 8

6 7

6 6

6 5

6 4

6 3

6 2

6 1

6 0

5 9

5 8

5 7

5 6

5 5

5 4

5 3

5 2

5 1

5 0

4 9

4 8

4 7

4 6

4 5

4 4

1

V S S

2

D Q 1 5

V S S Q

D Q 1 4

D Q 1 3

V D D Q

D Q 1 2

D Q 1 1

V S S Q

D Q 1 0

D Q 9

V D D Q

D Q 8

N C

3

4

5

6

7

8

D D Q

D Q 5

D Q 6

V

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

3 4

3 5

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

V S S Q

D Q 7

N C

V D D

V S S

D Q M 0

/W E

D Q M 1

N C

/C A S

/R A S

/C S

N C

C L K

C K E

A 9

8 6 p in T S O P II

4 0 0 m il x 8 7 5 m il

0 .5 m m p in p itc h

A 1 1

B A 0

B A 1

A 1 0 /A P

A 0

A 8

A 7

A 6

A 5

A 1

A 4

A 2

A 3

D Q M 2

V D D

D Q M 3

V S S

N C

D Q 1 6

D Q 3 1

V D D Q

D Q 3 0

D Q 2 9

V S S Q

D Q 2 8

D Q 2 7

V D D Q

D Q 2 6

D Q 2 5

V S S Q

D Q 2 4

V S S

S S Q

V

D Q 1 7

D Q 1 8

D D Q

V

D Q 1 9

D Q 2 0

V S S Q

D Q 2 1

D Q 2 2

V D D Q

D Q 2 3

V D D

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK.

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE

Clock Enable

Chip Select

CS

Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

Bank Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

A0 ~ A11

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

DQM0~3

DQ0 ~ DQ31

VDD/VSS

VDDQ/VSSQ

NC

Data Input/Output Mask

Data Input/Output

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power Supply/Ground

Power supply for internal circuits and input buffers

Power supply for output buffers

Data Output Power/Ground

No Connection

No connection

Rev. 0.6/Nov. 02

2

HY57V283220T-I / HY5V22F-I

Ball CONFIGURATION ( HY5V22F-ISeries)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

DQ 26

DQ 28

VSSQ

VDDQ

VSS

DQ 24

VDDQ

DQ 27

DQ 29

DQ 31

DQ M3

A5

VSS

VSSQ

DQ 25

DQ 30

NC

VDD

VDDQ

DQ 22

DQ 17

NC

DQ 23

VSSQ

DQ 20

DQ 18

DQ 16

DQ M2

A0

DQ 21

DQ 19

VDDQ

VSSQ

VDD

A3

A2

G

H

J

A4

A6

A10

A1

Top View

A7

A8

NC

BA1

A11

CLK

CKE

NC

A9

BA0

/CAS

/CS

/RAS

DQ M 0

K

L

DQ M1

NC

/W E

VDDQ

VSSQ

DQ 11

DQ 13

DQ 8

DQ 10

DQ 12

VDDQ

DQ 15

VSS

DQ 9

VDD

DQ 6

DQ 7

DQ 5

VSSQ

VDDQ

DQ 4

M

N

P

R

DQ 14

VSSQ

VSS

DQ 1

DQ 3

VDDQ

VDD

VSSQ

DQ 0

DQ 2

Ball DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK.

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE

Clock Enable

Chip Select

CS

Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

Bank Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

A0 ~ A11

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

DQM0~3

DQ0 ~ DQ31

VDD/VSS

VDDQ/VSSQ

NC

Data Input/Output Mask

Data Input/Output

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power Supply/Ground

Data Output Power/Ground

No Connection

Power supply for internal circuits and input buffers

Power supply for output buffers

No connection

Rev. 0.6/Nov. 02

3

HY57V283220T-I / HY5V22F-I

FUNCTIONAL BLOCK DIAGRAM

1Mbit x 4banks x 32 I/O Synchronous DRAM

Self Refresh Logic

& Timer

Refresh

Counter

x32 Bank 3

1M

CLK

Row

1M x32 Bank 2

1M x32 Bank 1

1M x32 Bank 0

Row Active

Pre

CKE

CS

Decoder

DQ0

DQ1

RAS

CAS

Memory

Cell

Array

WE

Column

Active

Column

DQM0

DQM1

DQM2

DQM3

Pre

Decoder

DQ30

DQ31

Y decoder

Column Add

Counter

Bank Select

A0

A1

Address

Register

Burst

Counter

A11

BA0

BA1

CAS Latency

Pipe Line Control

Mode Register

Data Out Control

Rev. 0.6/Nov. 02

4

HY57V283220T-I / HY5V22F-I

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Ambient Temperature

TA

-40 ~ 85

-55 ~ 125

-1.0 ~ 4.6

50

°C

Storage Temperature

TSTG

°C

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

V

VDD, VDDQ

IOS

V

mA

PD

1

W

Soldering Temperature ⋅ Time

TSOLDER

260 ⋅ 10

°C ⋅ Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION (TA=-40 to 85°C)

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

Input high voltage

Input low voltage

VDD, VDDQ

VIH

3.135

2.0

3.3

3.0

0

3.6

VDDQ + 0.3

0.8

V

1

1,2

1,3

VIL

VSSQ - 0.3

Note :

1.All voltages are referenced to VSS = 0V

2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes

3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes

AC OPERATING CONDITION (TA=-40 to 85°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)

Parameter

Symbol

Value

Unit

Note

AC input high / low level voltage

VIH / VIL

Vtrip

2.4/0.4

1.4

1

V

Input timing measurement reference level voltage

Input rise / fall time

tR / tF

Voutref

CL

ns

V

Output timing measurement reference level

Output load capacitance for access time measurement

1.4

30

pF

1

Note :

1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)

For details, refer to AC/DC output load circuit

Rev. 0.6/Nov. 02

5

HY57V283220T-I / HY5V22F-I

CAPACITANCE ( HY57V283220T-I Series) (TA=25°C, f=1MHz, VDD=3.3V)

Parameter

Input capacitance

Symbol

Min

Max

Unit

CLK

CI1

CI2

2.5

4.0

pF

A0 ~ A11, BA0, BA1, CKE, CS, RAS,

CAS, WE, DQM0~3

Data input / output capacitance

DQ0 ~ DQ31

CI/O

4.0

6.5

pF

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=500 Ω

RT=50 Ω

Output

Z0 = 50Ω

Output

30pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I ^{(DC operating conditions unless otherwise noted)}

Parameter

Symbol

Min.

Max

Unit

Note

Input leakage current

Output leakage current

Output high voltage

Output low voltage

ILI

-1

2.4

-

1

uA

V

1

2

ILO

VOH

VOL

-

IOH = -2mA

IOL = +2mA

0.4

V

Note :

1.VIN = 0 to 3.6V, All other pins are not under test = 0V

2.DOUT is disabled, VOUT=0 to 3.6V

Rev. 0.6/Nov. 02

6

HY57V283220T-I / HY5V22F-I

DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)

Speed

Parameter

Symbol

Test Condition

Unit

mA

Note

-5

-55

-6

-7

-8

-P

S

Burst length=1, One bank active

Operating Current

IDD1

120

110

100

90

1

tRC ≥ tRC(min), IOL=0mA

IDD2P

CKE ≤ VIL(max), tCK = 10ns

CKE ≤ VIL(max), tCK = ∞

2

1

Precharge Standby

Current

in power down mode

IDD2PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD2N

14

9

Precharge Standby

Current

mA

in non power down mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD2NS

IDD3P

7

6

CKE ≤ VIL(max), tCK = 10ns

CKE ≤ VIL(max), tCK = ∞

Active Standby Current

in power down mode

IDD3PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD3N

17

13

Active Standby Current

in non power down mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD3NS

CL=3

230

-

220

-

200

-

180

-

150

-

130

140

130

140

ttCK ≥ tCK(min), IOL=0mA

Burst Mode Operating

Current

IDD4

IDD5

IDD6

mA

1

All banks active

CL=2

Auto Refresh Current

Self Refresh Current

170

160

150

140

2

140

2

3

4

tRC ≥ tRC(min), All banks active

CKE ≤ 0.2V

0.8

Note :

1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3.HY57V283220T(HY5V22F)-5I/55I/6I/7I/8I/PI/SI

4.HY57V283220LT(HY5V22LF)-5I/55I/6I/7I/8I/PI/SI

Rev. 0.6/Nov. 02

7

HY57V283220T-I / HY5V22F-I

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

-5

-55

-6

-7

-8

-P

-S

Parameter

Symbol

Unit Note

Min Max Min Max Min Max Min Max Min Max Min Max Min Max

CAS Latency = 3 tCK3

CAS Latency = 2 tCK2

5

10

2

5.5

10

2.25

-

6

10

2.5

-

7

8

-10

3

-

10

3

-

10

12

3

-

ns

System clock

cycle time

1000

10

Clock high pulse width

Clock low pulse width

tCHW

tCLW

-

3

-

ns

1

2

-

3

-

CAS Latency = 3 tAC3

CAS Latency = 2 tAC2

tOH

-

4.5

5

6

-

5.5

-

5.5

6

-

6

-

6

-

Access time from

clock

2

-

6

-

6

-

6

-

Data-out hold time

1.5

1

-

2

-

2

-

2

1

2

1

2

1

2

1

-

2

1

2

1

2

1

2

1

-

2

1

2

1

2

1

2

1

-

3

1

Data-Input setup time

Data-Input hold time

Address setup time

Address hold time

tDS

1.5

1

-

1.5

1

1.75

-

tDH

tAS

-

1

-

1.5

1

-

1.5

1

-

1.5

1

-

1.75

-

tAH

-

1

-

CKE setup time

tCKS

tCKH

tCS

1.5

1

-

1.5

1

-

1.5

1

-

1.75

-

CKE hold time

-

1

-

Command setup time

Command hold time

CLK to data output in low Z-time

1.5

1

-

1.5

1

-

1.5

1

-

1.75

-

tCH

tOLZ

-

1

-

1

-

1

-

1

-

CAS Latency = 3 tOHZ3

CAS Latency = 2 tOHZ2

-

4.5

6

-

5

6

-

5.5

6

5.5

6

CLK to data output

in high Z-time

-

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v

3.Data-out hold time to be measured under 30pF load condition, without Vt termination

Rev. 0.6/Nov. 02

8

HY57V283220T-I / HY5V22F-I

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

-5

-55

-6

-7

-8

-P

-S

Not

e

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Operation

Auto Refresh

tRC

55

15

-

55

-

60

18

-

63

20

-

64

20

-

70

20

-

70

20

-

ns

RAS cycle time

tRRC

tRCD

RAS to CAS delay

RAS active time

16.5

100

K

100

K

100

K

100

K

100

K

100

K

100

K

tRAS

38.7

42

48

50

ns

RAS precharge time

tRP

15

2

1

0

1

4

2

0

2

3

2

1

-

16.5

2

-

18

2

1

0

1

4

2

0

2

3

2

1

-

20

2

1

0

1

4

2

0

2

3

2

1

-

20

2

1

0

1

4

2

0

2

3

2

1

-

20

1

-

20

1

-

ns

RAS to RAS bank active delay

CAS to CAS delay

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

CLK

ms

-

1

-

Write command to data-in delay

Data-in to precharge command

Data-in to active command

DQM to data-out Hi-Z

-

0

-

0

-

0

-

1

-

1

-

1

-

4

-

4

-

4

-

2

-

2

-

2

-

DQM to data-in mask

-

0

-

0

-

0

-

MRS to new command

-

2

-

2

-

2

-

CAS Latency = 3 tPROZ3

CAS Latency = 2 tPROZ2

-

3

-

3

-

3

-

Precharge to

data output Hi-Z

-

2

-

2

-

2

-

Power down exit time

Self refresh exit time

Refresh Time

tPDE

tSRE

tREF

-

1

-

1

-

1

-

1

-

1

-

1

-

1

64

-

64

-

64

-

64

Note :

1. A new command can be given tRRC after self refresh exit

Rev. 0.6/Nov. 02

9

HY57V283220T-I / HY5V22F-I

DEVICE OPERATING OPTION TABLE

HY5xxxxxxxxx-5I

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

200MHz(5ns)

183MHz(5.5ns)

166MHz(6ns)

3CLKs

8CLKs

7CLKs

11CLKs

10CLKs

3CLKs

4.5ns

5ns

5.5ns

1.5ns

2ns

HY5xxxxxxxxx-55I

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

183MHz(5.5ns)

166MHz(6ns)

143MHz(7ns)

3CLKs

7CLKs

6CLKs

10CLKs

9CLKs

3CLKs

5ns

5.5ns

2ns

HY5xxxxxxxxx-6I

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

166MHz(6ns)

143MHz(7ns)

125MHz(8ns)

3CLKs

7CLKs

6CLKs

10CLKs

9CLKs

3CLKs

5.5ns

6ns

2ns

2.5ns

HY5xxxxxxxxx-7I

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

143MHz(7ns)

125MHz(8ns)

100MHz(10ns)

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

9CLKs

7CLKs

3CLKs

2CLKs

5.5ns

6ns

2ns

HY5xxxxxxxxx-8I

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

125MHz(8ns)

100MHz(10ns)

83MHz(12ns)

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

4CLKs

9CLKs

7CLKs

6CLKs

3CLKs

2CLKs

6ns

2ns

2.5ns

HY5xxxxxxxxx-PI

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

2ns

2.5ns

Rev. 0.6/Nov. 02

10

HY57V283220T-I / HY5V22F-I

HY5xxxxxxxxx-SI

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

3CLKs

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

2ns

2.5ns

Rev. 0.6/Nov. 02

11

HY57V283220T-I / HY5V22F-I

COMMAND TRUTH TABLE

A10/

ADDR

Command

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

Note

AP

Mode Register Set

H

X

L

H

L

X

H

L

X

H

L

X

H

X

OP code

No Operation

X

Bank Active

L

RA

V

Read

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

H

L

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

H

X

V

X

L

H

L

H

X

L

X

V

X

DQM

X

Auto Refresh

H

X

L

H

L

Burst-Read-Single-

WRITE

A9 Pin High

(Other Pins OP code)

3

H

L

X

Entry

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

Self Refresh¹

Exit

X

L

H

L

H

L

X

H

L

Entry

Precharge

power down

X

H

L

Exit

H

L

Entry

Clock

Suspend

Exit

H

L

X

H

X

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation

3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.

Rev. 0.6/Nov. 02

12

HY57V283220T-I / HY5V22F-I

PACKAGE INFORMATION (HY57V283220T-I Series)

400mil 86pin Thin Small Outline Package

Unit : mm(inch)

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0.150(0.0059)

0.050(0.0020)

1.194(0.0470)

0.991(0.0390)

5deg

0deg

0.210(0.0083)

0.120(0.0047)

0.597(0.0235)

0.406(0.0160)

0.21(0.008)

0.18(0.007)

0.50(0.0197)

Rev. 0.6/Nov. 02

13

HY57V283220T-I / HY5V22F-I

PACKAGE INFORMATION (HY5V22F-I Series)

90Ball FBGA with 0.8mm of pin pitch

8.00±.10

Rev. 0.6/Nov. 02

14


型号：	HY5V22F-55I
厂家：	HYNIX SEMICONDUCTOR
描述：	Synchronous DRAM, 4MX32, 5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90 动态存储器
文件：	总14页 (文件大小：292K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY5V22F-55I [HYNIX]

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