HY5V22GF [HYNIX]
4 Banks x 1M x 32Bit Synchronous DRAM; 4银行X 1M X 32位同步DRAM
| 型号： | HY5V22GF |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 4 Banks x 1M x 32Bit Synchronous DRAM |
| 文件： | 总11页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY5V22GF
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY5V22G is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY5V22G is organized as 4banks of 1,048,576x32.
HY5V22G is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
•
JEDEC standard 3.3V power supply
•
•
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
90Ball FBGA with 0.8mm of pin pitch
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
All inputs and outputs referenced to positive edge of
system clock
•
•
Data mask function by DQM0,1,2 and 3
Internal four banks operation
•
•
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY5V22GF-H
HY5V22GF-P
133MHz
100MHz
4Banks x 1Mbits
x32
Normal
LVTTL
90Ball FBGA
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3/Nov. 01
HY5V22GF
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
VSS
VSSQ
DQ25
DQ30
NC
VDD
VDDQ
DQ22
DQ17
NC
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A3
A2
G
H
J
A4
A6
A10
A1
Top View
(11mmx13mm)
A7
A8
NC
NC
BA1
A11
CLK
CKE
NC
A9
BA0
CS#
RAS#
DQM0
K
L
DQM1
NC
CAS#
WE#
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
DQ9
VDD
DQ6
DQ7
DQ5
VSSQ
VDDQ
VDDQ
DQ4
M
N
P
R
DQ14
VSSQ
VSS
DQ1
DQ3
VDDQ
VDD
VSSQ
DQ0
DQ2
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
CLK
Clock
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CKE
Clock Enable
Chip Select
CS
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
Bank Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
A0 ~ A11
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
Data Input/Output Mask
Data Input/Output
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power Supply/Ground
Data Output Power/Ground
No Connection
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.3/Nov. 01
3
HY5V22GF
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
x32 Bank 3
1M
CLK
Row
1M x32 Bank 2
Row Active
Pre
CKE
CS
Decoder
1M x32 Bank 1
1M x32 Bank 0
DQ0
DQ1
RAS
CAS
Memory
Cell
Array
WE
Column
Active
Column
DQM0
DQM1
DQM2
DQM3
Pre
Decoder
DQ30
DQ31
Y decoder
Column Add
Counter
Bank Select
A0
A1
Address
Register
Burst
Counter
A10
BA0
BA1
CAS Latency
Pipe Line Control
Mode Register
Data Out Control
Rev. 0.3/Nov. 01
4
HY5V22GF
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
°C
Storage Temperature
TSTG
°C
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
V
VDD, VDDQ
IOS
V
mA
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Input high voltage
Input low voltage
VDD, VDDQ
VIH
3.0
2.0
3.3
3.0
0
3.6
VDDQ + 0.3
0.8
V
V
V
1,2
1,3
1,4
VIL
VSSQ - 0.3
Note :
1.All voltages are referenced to VSS = 0V
2.VDD/VDDQ(min) is 3.15V for HY5V22GF-H/P
3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes
4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes
AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)
Parameter
Symbol
Value
Unit
Note
AC input high / low level voltage
VIH / VIL
Vtrip
2.4/0.4
1.4
1
V
V
Input timing measurement reference level voltage
Input rise / fall time
tR / tF
Voutref
CL
ns
V
Output timing measurement reference level
Output load capacitance for access time measurement
1.4
30
pF
2
Note :
1.3.15V ≤VDD ≤3.6V is applied for HY5V22GF-H/P
2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.3/Nov. 01
5
HY5V22GF
CAPACITANCE (TA=25°C, f=1MHz, VDD=3.3V)
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
CI1
CI2
2.5
2.5
3.5
3.8
pF
pF
A0 ~ A10, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
Data input / output capacitance
DQ0 ~ DQ31
CI/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500 Ω
RT=50 Ω
Output
Z0 = 50Ω
Output
30pF
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Parameter
Symbol
Min.
Max
Unit
Note
Input leakage current
Output leakage current
Output high voltage
Output low voltage
ILI
-1
-1
2.4
-
1
1
uA
uA
V
1
2
ILO
VOH
VOL
-
IOH = -2mA
IOL = +2mA
0.4
V
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.3/Nov. 01
6
HY5V22GF
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Speed
Parameter
Symbol
Test Condition
Unit
mA
mA
Note
-H
-P
Burst Length=1, One bank active
tRAS ≥ tRAS(min), tRP ≥ tRP(min),
IOL=0mA
Operating Current
IDD1
150
140
1
IDD2P
4
4
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
Precharge Standby Current
in power down mode
IDD2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2N
30
20
Precharge Standby Current
in non power down mode
mA
mA
mA
mA
CKE ≥ VIH(min), tCK = ∞
IDD2NS
Input signals are stable.
IDD3P
6
6
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
Active Standby Current
in power down mode
IDD3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3N
IDD3NS
IDD4
80
50
Active Standby Current
in non power down mode
CKE ≥ VIH(min), tCK = ∞
Input signals are stable
CL=3
CL=2
tCK ≥ tCK(min),
Burst Mode Operating
Current
tRAS ≥ tRAS(min), IOL=0mA
All banks active
250
350
230
330
1
2
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
tRRC ≥ tRRC(min), 2 banks active
CKE ≤ 0.2V
mA
mA
4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS I
Rev. 0.3/Nov. 01
7
HY5V22GF
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-H
-P
Parameter
Symbol
Unit
Note
Min
7.5
10
Max
Min
10
10
3
Max
CAS Latency = 3
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock
cycle time
1000
1000
CAS Latency = 2
Clock high pulse width
Clock low pulse width
2.5
2.5
-
-
-
-
1
1
3
CAS Latency = 3
CAS Latency = 2
5.4
6
-
6
6
-
Access time from clock
2
-
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
3
2
1
2
1
2
1
2
1
1
3
1
1
1
1
1
1
1
1
tDS
-
-
tDH
-
-
tAS
-
-
tAH
-
-
tCKS
tCKH
tCS
-
-
CKE hold time
-
-
Command setup time
Command hold time
-
-
tCH
-
-
CLK to data output in low Z-time
tOLZ
tOHZ3
tOHZ2
-
-
CAS Latency = 3
CAS Latency = 2
CLK to data output in
high Z-time
5.4
6
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.3/Nov. 01
8
HY5V22GF
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
-H
-P
Parameter
Symbol
Unit
Note
Min
65
65
20
45
20
15
1
Max
Min
70
70
20
50
20
20
1
Max
Operation
Auto Refresh
tRC
-
-
ns
RAS cycle time
tRRC
tRCD
tRAS
tRP
-
-
ns
RAS to CAS delay
RAS active time
-
-
ns
120K
120K
ns
RAS precharge time
-
-
-
-
ns
RAS to RAS bank active delay
CAS to CAS delay
tRRD
tCCD
tWTL
tDPL
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ms
-
-
Write command to data-in delay
Data-in to precharge command
Data-in to active command
DQM to data-out Hi-Z
0
-
0
-
1
-
1
-
tDAL
4
-
3
-
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tPDE
tSRE
tREF
2
-
2
-
DQM to data-in mask
0
-
0
-
MRS to new command
1
-
1
-
CAS Latency = 3
CAS Latency = 2
3
-
3
-
Precharge to data
output Hi-Z
2
-
2
-
Power down exit time
Self refresh exit time
Refresh Time
1
-
1
-
1
-
1
-
1
-
64
-
64
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.3/Nov. 01
9
HY5V22GF
DEVICE OPERATING OPTION TABLE
HY5V22GF-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY5V22GF-P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
Rev. 0.3/Nov. 01
10
HY5V22GF
COMMAND TRUTH TABLE
A10/
AP
ADDR
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
Note
Mode Register Set
H
H
H
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
X
No Operation
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
H
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
DQM
Auto Refresh
Entry
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
L
Self Refresh1
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
X
X
X
H
L
Entry
Precharge
power down
H
L
Exit
H
H
L
Entry
Clock
Suspend
Exit
H
L
L
X
X
H
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.3/Nov. 01
11
HY5V22GF
PACKAGE INFORMATION
Rev. 0.3/Nov. 01
12
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