HY62256ALT1_技术文档

Data Sheet-sram/62256ald1

http://www.hea.com/hean2/sram/62256ald1.htm

HY62256A-(I) Series

32Kx8bit CMOS SRAM

Description

Features

The

Fully static operation and

Tri-state outputs

·

HY62256A/HY62256A-I

is a high-speed, low

power and 32,786 x 8-bits

CMOS Static Random

Access Memory

TTL compatible inputs

and outputs

Low power consumption

-2.0V(min.) data

retention

fabricated using

Hyundai's high

Standard pin

configuration

-28 pin 600 mil PDIP

-28 pin 330 mil SOP

-28 pin 8x13.4 mm

TSOP-1

·

performance CMOS

process technology. The

HY62256A/HY62256A-I

has a data retention mode

that guarantees data to

remain valid at the

(standard and reversed)

minimum power supply

voltage of 2.0 volt. Using

the CMOS technology,

supply voltages from 2.0

to 5.5 volt has little effect

on supply current in the

data retention mode. The

HY62256A/HY62256A-I

is suitable for use in low

voltage operation and

battery back-up

application.

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Data Sheet-sram/62256ald1

http://www.hea.com/hean2/sram/62256ald1.htm

Standby

Current(uA)

Voltage Speed

Operation

Current(mA)

Temperature

(°C)

Product No.

(V)

(ns)

L

LL

HY62256A 5.0

HY62256A-I 5.0

Note

55/70/85 50

1mA 100 25 0-70(Normal)

1mA 100 - -40-85(E.T.)

1. E T. Extended Temperature, Normal: Normal Temperature

2. Current value is max.

3101 North First Street, San Jose, CA 95134

Phone: 408-232-8000 URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com

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HYUNDAI ELECTRONICS AMERICA

HY62256A-(I) Series

PIN INFORMATION

32Kx8bit CMOS SRAM

PIN CONNECTION

BLOCK DIAGRAM

PIN DESCRIPTION

Pin Name

Pin Function

/CS

Chip Select

/WE

Write Enable

Output Enable

Address Inputs

Data Input/Output

Power(+5.0V)

Ground

/OE

A0-A14

I/O1-I/O8

Vcc

Vss

3101 North First Street, San Jose, CA 95134

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SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com

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HYUNDAI ELECTRONICS AMERICA

HY62256A-(I) Series

RATINGS INFORMATION

32Kx8bit CMOS SRAM

ABSOLUTE MAXIMUM RATING (1)

Symbol

Parameter

Rating

Unit

Remark

VCC VIN

VOUT

Power Supply Input/Output

Voltage

-0.5 to 7.0 V

0 to 70

°C

HY62256A

HY62256A-I

TA

Operating Temperature

-40 to 85 °C

-65 to 150 °C

TSTG

PD

Storage Temperature

Power Dissipation

Data OutPut Current

1.0

50

W

IOUT

mA

Lead Soldering Temperature

& Time

TSOLDER

260 /10

°C / sec

Note

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is stress rating only and the

functional operation of the device under these or any other conditions above

those indicated in the operation of this specification is not implied. Exposure to

the absolute maximum rating conditions for extended period may affect

reliability.

RECOMMENDED DC OPERATING CONDITIONS

TA=0°C to 70°C / TA= -40°C to 85°C (E.T.)

Symbol

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Min

4.5

Typ

5.0

Max

Unit

VCC

5.5

V

VIH

2.2

-

VCC+0.5

0.8

V

VIL

-0.5(1)

Note

1. VIL = -3.0V for pulse width less than 30ns

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TRUTH TABLE

/CS /WE

/OE

MODE

I/O OPERATION

H

X

Standby

High-Z

L

H

L

H

L

Output Disabled

Read

High-Z

Data Out

Data In

L

X

Write

Note:

1. H=VIH, L=VIL, X=Don't Care

DC CHARACTERISTICS

Vcc = 5V ?% TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise

specified

Symbol

Parameter

Test Condition

Min Typ Max Unit

ILI

Input Leakage Current

Vss <= VIN <= Vcc -1

-

1

uA

Vss <= VOUT <= Vcc

/CS=VIH or

-1

ILO

Output Leakage Current

/OE=VIH or /WE =

VIL

/CS= VIL,

VIN=VIH or VIL, II/O= -

0mA

Operating Power Supply

Current

Icc

30 50

40 70

mA

/CS = VIL

Min. Duty Cycle =

100%, II/O =0mA

Average Operating

Current

Icc1

-

TTL Standby Current

(TTL Inputs)

/CS = VIH VIN = VIH

or VIL

ISB

-

0.4

2

1

mA

-

CMOS

Standby

/CS >= Vcc-

0.2V

HY62256A

L

2

1

-

100 uA

ISB1

Current

(CMOS

VIN <= 0.2V or LL -

VIN >=

25

1

uA

-

mA

Input)

VCC-0.2V

HY62256A-I

L

-

2

-

100 uA

VOL

VOH

Output Low Voltage

Output High Voltage

IOL= 2.1 mA

IOH = 1mA

-

0.4

-

V

2.4

-

Note: Typical values are at Vcc = 5.0V TA = 25°C

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AC CHARACTERISTICS

Vcc = 5V(±)10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.) unless otherwise

specified.

-55

-70

-85

# Symbol

Parameter

Unit

Min. Max. Min. Max. Min. Max.

READ CYCLE

1 tRC

2 tAA

3 tACS

Read Cycle Time

55

-

70

-

85

-

ns

Address Access Time

55

70

85

Chip Select Access Time

-

Output Enable to Output

Valid

4 tOE

-

30

-

35

-

45

-

ns

Chip Select to Output in

Low Z

5 tCLZ

6 tOLZ

7 tCHZ

8 tOHZ

9 tOH

5

0

5

0

5

0

5

Output Enable to Output in

Low Z

-

Chip Deselection to Output

in High Z

20

-

30

-

30

-

Out Disable to Output in

High Z

Output Hold from Address

Change

WRITE CYCLE

10 tWC

Write Cycle Time

55

50

-

70

65

-

85

75

-

ns

Chip Selection to End of

Write

11 tCW

Address Valid to End of

Write

12 tAW

50

-

65

-

75

-

ns

13 tAS

14 tWP

15 tWR

Address Set-up Time

Write Pulse Width

0

-

0

-

0

-

ns

40

0

-

50

0

-

55

0

-

Write Recovery Time

-

16 tWHZ Write to Output in High Z

0

20

-

0

30

-

0

30

-

17 tDW

18 tDH

Data to Write Time Overlap 25

Data Hold from Write Time 0

35

0

40

0

-

Output Active from End of

Write

19 tOW

5

-

5

-

5

-

ns

AC TEST CONDITIONS

TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise specified.

PARAMETER VALUE

Input Pulse Level

Input Rise and Fall Time

0.8V to 2.4V

5ns

Input and Output Timing Reference Levels 1.5V

70/85/100ns

55ns

CL = 100pF + 1TTL Load

CL = 50pF + 1TTL Load

Output Load

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AC TEST LOADS

Note: Including jig and scope capacitance

CAPACITANCE

TAA= 25 °C, f = 1.0MHz

Symbol

Parameter

Condition

Max

Unit

pF

CIN

Input Capacitance

VIN = 0V

VI/O= 0V

6

8

CI/O

Input/Output Capacitance

Note: These parameters are sampled and not 100% tested

3101 North First Street, San Jose, CA 95134

Phone: 408-232-8000 URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com

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HYUNDAI ELECTRONICS AMERICA

HY62256A-I

TIMING INFORMATION

32K x 8bit CMOS SRAM

TIMING DIAGRAM

READ CYCLE 1

Note (READ CYCLE):

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open

circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min.

both for a given device and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

Note (READ CYCLE):

1. /WE is high for the read cycle.

2. Device is continuously selected /CS= VIL.

3. /OE =VIL.

WRITE CYCLE 1 (/OE Clocked)

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WRITE CYCLE 2 (/OE Low Fixed)

Notes (WRlTE CYCLE):

1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at

the latest transition among /CS going low and /WE going low: A write ends at

the earliest transition among /CS going high and /WE going high. tWP is

measured from the beginning of write to the end of write.

2. tcw is measured from the later of /CS going low to the end of write .

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in

case a write ends as /CS, or /WE going high.

5. If /OE and /WE are in the read mode during this period, and the I/O pins are in

the output low-Z state, input of opposite phase of the output must not be applied

because bus contention can occur.

6. If /CS goes low simultaneously with /WE going low, or after /WE going low,

the outputs remain in high impedance state.

7. DOUT is the same phase of latest written data in this write cycle.

8. DOUT is the read data of the new address.

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DATA RETENTION CHARACTERISTIC

TA= 0°C to 70°C (normal) /-40°C to 85°C (E.T.)

Symbol

Parameter

Test Condition Min Typ Max Unit

/CS >= Vcc-0.2V

Vss <= VIN <=

Vcc

VDR

Vcc for Data Re! ention

2

-

V

Vcc = 3.0V

/CS >= Vcc

-0.2V

Vss <= VIN

<= Vcc

L

-

1

50 uA

15(2) uA

50 uA

Data

Retention

Current

HY62256A

LL -

ICCDR

HY62256A-1

L

-

Chip Disable to Data Retention

Time

See Data

Retention Timing

Diagram

tCDR

0

-

ns

tR

Operating Recovery Time

tRC(3) -

Notes

1. Typical values are under the condition of TA = 25°C

2. 3uA max. at TA= 0°C to 40°C

3. tRC is read cycle time.

Data Retention Timing Diagram

RELIABILITY SPEC.

TEST MODE

TEST SPEC.

>= 2000V

>= 250V

HBM

MM

ESD

<= -100mA

>= 100mA

LATCH-UP

3101 North First Street, San Jose, CA 95134

Phone: 408-232-8000 URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com

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HYUNDAI ELECTRONICS AMERICA

HY62256A-(I) Series

PACKAGE INFORMATION

32Kx8bit CMOS SRAM

28pin 600mil Dual In-Line Package(P)

28pin 330mil Small Outline Package(J)

28pin 8X13.4mm Thin Small Outline Package Standard(T1)

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28pin 8X13.4mm Thin Small Outline Package SReversed(R1)

3101 North First Street, San Jose, CA 95134

Phone: 408-232-8000 URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com

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HYUNDAI ELECTRONICS AMERICA

HY62256A-(I) Series

ORDERING INFORMATION

32Kx8bit CMOS SRAM

Part No.

HY62256AP

Speed

55/70/85

Power

L-part

Temp.

Package

PDIP

SOP

HY62256ALP

HY62256ALLP

HY62256AJ

LL-part

HY62256ALJ

L-part

HY62256ALLJ

HY62256AT1

HY62256ALT1

HY62256ALLT1

HY62256AR1

HY62256ALR1

HY62256ALLR1

HY62256AP-I

HY62256ALP-I

HY62256AJ-I

HY62256ALJ-I

HY62256AT1-I

HY62256ALT1-I

HY62256AR2-I

HY62256ALR2-I

LL-part

TSOP-I Standard

TSOP-I Reversed

PDIP

L-part

LL-part

L-part

LL-part

E.T.

L-part

E.T.

E .T.

E.T.

PDIP

SOP

TSOP-I

TSOP-I Reversed

3101 North First Street, San Jose, CA 95134

Phone: 408-232-8000 URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com

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型号：	HY62256ALT1
厂家：	HYNIX SEMICONDUCTOR
描述：	32Kx8bit CMOS SRAM 32Kx8bit CMOS SRAM 静态存储器
文件：	总14页 (文件大小：822K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY62256ALT1 [HYNIX]

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HY62256ALT1-10

HY62256ALT1-10I

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HY62256ALT1-55

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HY62256ALT1-70

HY62256ALT1-70I

HY62256ALT1-85

HY62256ALT1-85I

HY62256ALT1-I

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HY62256AP