HY62EF8100LLST-12 [HYNIX]
Standard SRAM, 128KX8, 120ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32;
| 型号： | HY62EF8100LLST-12 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 128KX8, 120ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32 静态存储器 光电二极管 |
| 文件： | 总12页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY62UF8100/ HY62QF8100/ HY62EF8100/
HY62SF8100 Series 128Kx8bit full CMOS SRAM
DESCRIPTION
FEATURES
The HY62UF8100 / HY62QF8100 / HY62EF8100
/ HY62SF8100 is a high speed, super low power
and 1M bit full CMOS SRAM organized as
131,072 words by 8bit. The HY62UF8100 /
HY62QF8100 / HY62EF8100 / HY62SF8100 uses
high performance full CMOS process technology
and designed for high speed low power circuit
technology. It is particularly well suited for used in
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 1.5V.
·
·
·
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(LL/SL-part)
- 1.5V(min) data retention
Standard pin configuration
·
-
32pin sTSOP-I
Product
No.
Voltage
(V)
Speed
(ns)
Operation
Current(mA)
Standby Current(uA)
Temperature
(°C)
LL
5
SL
1
HY62UF8100
HY62UF8100-I
HY62QF8100
HY62QF8100-I
HY62EF8100
HY62EF8100-I
HY62SF8100
HY62SF8100-I
3.0
3.0
2.5
2.5
2.0
2.0
1.8
1.8
70/85/100
70/85/100
85/100/120
85/100/120
100/120/150
100/120/150
120/150/200
120/150/200
10
10
5
5
5
5
5
5
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
ROW DECODER
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O1
1
2
A0
A8
3
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
4
5
6
7
8
9
10
11
12
13
14
15
16
MEMORY ARRAY
1024x1024
A6
A1
A5
A2
A4
A3
A16
I/O8
Small TSOP-I(Standard)
/CS1
CS2
/OE
/WE
PIN DESCRIPTION
Pin Name
/CS1
Pin Function
Pin Name
Pin Function
Address Input
Chip Select 1
Chip Select 2
Write Enable
Output Enable
A0 ~ A16
CS2
/WE
/OE
I/O1 ~ I/O8
Vcc
Data Input/Output
Power(3.0V, 2.5V, 2.0V or 1.8V)
Ground
Vss
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.05 /Feb.99
Hyundai Semiconductor
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
ORDERING INFORMATION
Part No.
Speed
70/85/100
70/85/100
70/85/100
70/85/100
85/100/120
85/100/120
85/100/120
85/100/120
100/120/150
100/120/150
100/120/150
100/120/150
120/150/200
120/150/200
120/150/200
120/150/200
Power
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
Temp.
Package
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
sTSOP
HY62UF8100LLST
HY62UF8100SLST
HY62UF8100LLST-I
HY62UF8100SLST-I
HY62QF8100LLST
HY62QF8100SLST
HY62QF8100LLST-I
HY62QF8100SLST-I
HY62EF8100LLST
HY62EF8100SLST
HY62EF8100LLST-I
HY62EF8100SLST-I
HY62SF8100LLST
HY62SF8100SLST
HY62SF8100LLST-I
HY62SF8100SLST-I
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature
ABSOLUTE MAXIMUM RATING (1)
Symbol
VIN, VOUT
Vcc
Parameter
Input/Output Voltage
Power Supply
Rating
-0.2 to 3.6
-0.2 to 4.0
0 to 70
Unit
V
V
Remark
TA
Operating Temperature
HY62UF8100
HY62QF8100
HY62EF8100
HY62SF8100
HY62UF8100-I
HY62QF8100-I
HY62EF8100-I
HY62SF8100-I
°C
-40 to 85
°C
TSTG
PD
Storage Temperature
Power Dissipation
-55 to 150
1.0
°C
W
TSOLDER
Lead Soldering Temperature & Time
260 · 5
°C·sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Rev.05 /Feb.99
2
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Parameter
Supply Voltage
Product
Min.
2.7
2.2
1.8
1.6
0
Typ.
3.0
2.5
2.0
1.8
0
Max.
3.3
2.8
2.2
2.0
0
Unit
V
V
HY62UF8100-(I)
HY62QF8100-(I)
HY62EF8100-(I)
HY62SF8100-(I)
HY62UF8100-(I)
HY62QF8100-(I)
HY62EF8100-(I)
HY62SF8100-(I)
V
Vss
VIH
Ground
V
Input High Voltage HY62UF8100-(I)
HY62QF8100-(I)
2.2
2.0
1.6
1.4
-0.2(1)
-
-
-
Vcc+0.2
Vcc+0.2
Vcc+0.2
Vcc+0.2
0.4
V
V
V
V
V
HY62EF8100-(I)
HY62SF8100-(I)
VIL
Input Low Voltage HY62UF8100-(I)
HY62QF8100-(I)
-
HY62EF8100-(I)
HY62SF8100-(I)
Note : 1. VIL = -1.5V for pulse width less than 30ns
TRUTH TABLE
/CS1 CS2
/WE /OE
MODE
Standby
I/O OPERATION
High-Z
Supply Current
Isb, Isb1
H
X
L
L
L
X
L
H
H
H
X
X
H
H
L
X
X
H
L
Output Disabled High-Z
Read
Write
Icc
Icc1
Icc1
Data Out
Data In
X
Note :
1. H=VIH, L=VIL, X=don't care
Rev.05 /Feb.99
3
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.0V±10%/2.5V±10%/2.0V±10%/1.8V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.)
Sym
ILI
ILO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Vss < VIN < Vcc
Vss < VOUT < Vcc, /CS1 = VIH or
CS2 = VIL or /OE = VIH or /WE = VIL
Min.
-1
-1
Typ.
-
-
Max.
1
1
Unit
uA
uA
Icc
Operating Power Supply
Current
/CS1 = VIL,
CS2 = VIH,
VIN = VIH or VIL,
II/O = 0mA
Vcc = 3.0V
-
-
5
3
10
5
mA
mA
Vcc = 2.5V/2V/
1.8V
ICC1
Average
HY62UF8100-(I) /CS1 = VIL CS2 = VIH,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55
40
25
20
0.5
0.3
0.3
0.3
1
mA
mA
mA
mA
mA
mA
mA
mA
uA
Operating HY62QF8100-(I) Min Duty Cycle = 100%, II/O = 0mA
HY62EF8100-(I)
Current
TTL
Standby
Current
(TTL Input)
HY62SF8100-(I)
HY62UF8100-(I) /CS1 = VIH or CS2 = VIL
HY62QF8100-(I)
HY62EF8100-(I)
HY62SF8100-(I)
ISB
-
0.05
-
ISB1
VOL
Standby Current
(CMOS Input)
/CS1 > Vcc – 0.2V
CS2 < 0.2V or
CS2 > Vcc – 0.2V
Vcc = 3.0V
SL
LL
5
uA
Output Low Voltage
IOL = 2.1mA
IOL = 0.5mA
-
-
0.4
V
Vcc = 2.5V
Vcc = 2.0V
Vcc = 1.8V
HY62UF8100-(I) Vcc = 3.0V
HY62QF8100-(I) Vcc = 2.5V
HY62EF8100-(I) Vcc = 2.0V
HY62SF8100-(I) Vcc = 1.8V
IOL = 0.33mA
IOL = 0.26mA
IOH = -1.0mA
IOH = -0.5mA
IOH = -0.44mA
IOH = -0.44mA
VOH
Output
High
Voltage
2.2
2.0
1.6
1.4
-
-
-
-
-
-
-
-
V
V
V
V
Note : Typical values are at Vcc = 3.0V/2.5V/2.0V/1.8V, TA = 25°C
Rev.05 /Feb.99
4
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
AC CHARACTERISTICS
Vcc = 3.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-70
Max. Min.
-85
Max. Min
-10
Max.
#
Symbol
Parameter
Unit
Min.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
70
-
-
-
10
5
0
0
10
-
85
-
-
-
10
5
0
0
10
-
100
-
-
-
20
5
0
0
15
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
40
-
85
85
45
-
-
-
-
30
30
-
30
30
-
30
30
-
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWR
16 tWHZ
17 tDW
18 tDH
19 tOW
Write Cycle Time
70
60
60
0
50
0
0
30
0
-
-
-
-
-
-
25
-
-
-
85
70
70
0
55
0
0
35
0
-
-
-
-
-
-
30
-
-
-
100
80
80
0
75
0
0
45
0
-
-
-
-
-
-
35
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
5
5
10
Vcc = 2.5V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-85
Max. Min.
-10
Max. Min
-12
#
Symbol
Parameter
Unit
Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
85
-
-
-
10
5
0
0
10
-
100
-
-
-
20
5
0
0
15
-
100
100
50
-
120
-
-
-
120
120
60
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
85
45
-
-
20
10
0
0
15
-
-
-
30
30
-
30
30
-
40
40
-
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWR
16 tWHZ
17 tDW
18 tDH
19 tOW
Write Cycle Time
85
70
70
0
55
0
0
35
0
-
-
-
-
-
-
30
-
-
-
100
80
80
0
75
0
0
45
0
-
-
-
-
-
-
35
-
-
-
120
100
100
0
85
0
0
50
0
-
-
-
-
-
-
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
5
10
10
Rev.05 /Feb.99
5
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
Vcc = 2.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-10
Max. Min.
-12
Max. Min
-15
Max.
#
Symbol
Parameter
Unit
Min.
READ CYCLE
1
2
3
4
5
6
7
8
9
TRC
TAA
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
100
-
-
-
100
100
50
-
120
-
-
-
120
120
60
-
150
-
-
-
150
150
75
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
TACS
TOE
TCLZ
TOLZ
TCHZ
-
-
-
20
10
0
0
15
20
10
0
0
15
20
10
0
0
15
-
-
-
30
30
-
40
40
-
50
50
-
TOHZ Out Disable to Output in High Z
TOH
Output Hold from Address Change
WRITE CYCLE
10 TWC
11 TCW
12 TAW
13 TAS
14 TWP
15 TWR
Write Cycle Time
100
80
80
0
75
0
0
45
0
-
-
-
-
-
-
35
-
-
-
120
100
100
0
85
0
0
50
0
-
-
-
-
-
-
40
-
-
-
150
120
120
0
100
0
0
60
0
-
-
-
-
-
-
50
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
16 TWHZ Write to Output in High Z
17 TDW
18 TDH
19 TOW
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
10
10
10
Vcc = 1.8V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-12
Max. Min.
-15
Max. Min
-20
#
Symbol
Parameter
Unit
Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
TRC
TAA
TACS
TOE
TCLZ
TOLZ
TCHZ
tOHZ
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
120
-
-
-
120
120
60
-
150
-
-
-
150
150
75
-
200
-
-
-
200
200
100
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
20
10
0
0
15
20
10
0
0
15
30
15
0
0
30
-
-
-
40
40
-
50
50
-
60
60
-
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWR
16 tWHZ
17 tDW
18 tDH
19 tOW
Write Cycle Time
120
100
100
0
85
0
0
50
0
-
-
-
-
-
-
60
-
-
-
150
120
120
0
100
0
0
60
0
-
-
-
-
-
-
70
-
-
-
200
170
170
0
135
0
0
80
0
-
-
-
-
-
-
80
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
10
15
15
Rev.05 /Feb.99
6
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
AC TEST CONDITIONS
TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.), unless otherwise specified
PARAMETER Value
0.4V to 2.2V
Input Pulse Level
HY62UF8100-(I)
HY62QF8100-(I)
HY62EF8100-(I)
HY62SF8100-(I)
0.4V to 2.2V
0.4V to 1.8V
0.4V to 1.6V
Input Rise and Fall Time
Input and Output
Timing Reference
5ns
1.5V
1.1V
0.9V
HY62UF8100-(I)
HY62QF8100-(I)
HY62EF8100-(I)
HY62SF8100-(I)
Level
0.8V
Output Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM(2)
3070 Ohm
3150 Ohm
DOUT
CL(1)
Note
1. Including jig and scope capacitance
2. VTM = 2.8V for Vcc = 3.0V : HY62UF8100-(I)
VTM = 2.3V for Vcc = 2.5V : HY62QF8100-(I)
VTM = 1.8V for Vcc = 2.0V : HY62EF8100-(I)
VTM = 1.6V for Vcc = 1.8V : HY62SF8100-(I)
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance(Add, /CS, /WE, /OE)
Output Capacitance(I/O)
Condition
VIN = 0V
VI/O = 0V
Max.
8
10
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.05 /Feb.99
7
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
OE
tAA
tOE
tOLZ
tOH
CS1
CS2
tACS
tCLZ
tOHZ
tCHZ
High-Z
Data
Out
Data Valid
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS1 = VIL, CS2 = VIH.
3. /OE =VIL.
Rev.05 /Feb.99
8
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
WRITE CYCLE 1(/WE Controlled)
tWC
ADDR
CS1
tAW
tWR
tCW
CS2
tWP
tAS
WE
tDW
tDH
Data Valid
Data In
tOHZ
tOW
High-Z
Data
Out
Data Undefined
WRITE CYCLE 2 (/CS1 Controlled)
tWC
ADDR
tWR
tAS
tCW
CS1
tAW
CS2
WE
tWP
tDH
tDW
Data Valid
Data In
High-Z
tCLZ
tWHZ
Data
Out
High-Z
High-Z
Rev.05 /Feb.99
9
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
WRITE CYCLE 3 (CS2 Controlled)
tWC
ADDR
tAS
tWR
tCW
CS1
tAW
CS2
WE
tWP
tDW
Data Valid
tDH
Data In
High-Z
tCLZ
tWHZ
High-Z
Data
High-Z
Out
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition
among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among
/CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of
write.
.
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as
/CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low.
5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state.
7. Dout is the read data of the new address.
8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite
phase leading to the outputs should not be applied.
Rev.05 /Feb.99
10
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
DATA RETENTION ELECTRIC CHARACTERISTIC
TA=0°C to 70°C (Normal)/-40°C to 85°C (E.T.)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VDR
Vcc for Data Retention
/CS1 > Vcc-0.2V,
1.5
-
3.3
V
CS2 < 0.2V or
> Vcc - 0.2V,
Vss < VIN < Vcc
ICCDR
Data Retention Current
Vcc=2.0V, /CS1 > Vcc - 0.2V,
CS2 < 0.2V or > Vcc - 0.2V,
Vss < VIN < Vcc
LL
SL
-
-
-
-
5
1
uA
uA
tCDR
tR
Chip Deselect to Data
Retention Time
Operating Recovery Time
See Data Retention Timing Diagram
0
-
-
-
-
ns
ns
tRC(2)
Notes:
1. Typical values are under the condition of TA = 25°C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM 1
DATA RETENTION MODE
VCC
2.7/2.2V
1.8/1.6V
tCDR
tR
VIH
VDR
CS1>VCC-0.2V
CS1
VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE
VCC
2.7/2.2V
1.8/1.6V
tCDR
tR
CS2
VDR
0.4V
VSS
CS2<0.2V
Note :
1. 2.7V : HY62UF8100 and HY62UF8100-I
2.2V : HY62QF8100 and HY62QF8100-I
1.8V : HY62EF8100 and HY62EF8100-I
1.6V : HY62SF8100 and HY62SF8100-I
Rev.05 /Feb.99
11
HY62UF8100/HY62QF8100/HY62EF8100/HY62SF8100 Series
RELIABILITY SPEC.
TEST MODE
TEST SPEC.
ESD
HBM
MM
> 2000V
> 250V
LATCH - UP
< -100mA
> 100mA
PACKAGE INFORMATION
32pin 8x13.4mm Thin Small Outline Package Standard(ST)
#1
#32
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
#17
#16
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
0.020(0.50)
0.008(0.2)
0.004(0.1)
0.024(0.6)
0.016(0.4)
0.011(0.27)
0.007(0.17)
Rev.05 /Feb.99
12
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