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HY62EF8200SLM-10I [HYNIX]

Standard SRAM, 256KX8, 100ns, CMOS, PBGA48, MICRO, BGA-48;
HY62EF8200SLM-10I
型号： HY62EF8200SLM-10I
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

Standard SRAM, 256KX8, 100ns, CMOS, PBGA48, MICRO, BGA-48

静态存储器
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HY62UF8200/ HY62QF8200/ HY62EF8200/  
HY62SF8200 Series 256Kx8bit full CMOS SRAM  
DESCRIPTION  
FEATURES  
·
·
·
Fully static operation and Tri-state output  
TTL compatible inputs and outputs  
Battery backup(LL/SL-part)  
- 1.5V(min) data retention  
Standard pin configuration  
- 48ball uBGA  
The HY62UF8200 / HY62QF8200 / HY62EF8200  
/ HY62SF8200 is a high speed, super low power  
and 2M bit full CMOS SRAM organized as  
262,144 words by 8bits. The HY62UF8200 /  
HY62QF8200 / HY62EF8200 / HY62SF8200 uses  
high performance full CMOS process technology  
and is designed for high speed and low power  
circuit technology. It is particularly well-suited for  
the high density low power system application.  
This device has a data retention mode that  
guarantees data to remain valid at a minimum  
power supply voltage of 1.5V.  
·
Product  
No.  
Voltage  
(V)  
Speed  
(ns)  
Operation  
Current(mA)  
Standby Current(uA)  
Temperature  
(°C)  
LL  
10  
10  
10  
10  
10  
10  
10  
10  
SL  
2
2
2
2
2
2
2
2
HY62UF8200  
HY62UF8200-I  
HY62QF8200  
HY62QF8200-I  
HY62EF8200  
HY62EF8200-I  
HY62SF8200  
HY62SF8200-I  
3.0  
3.0  
2.5  
2.5  
2.0  
2.0  
1.8  
1.8  
70/85/100  
70/85/100  
85/100/120  
85/100/120  
100/120/150  
100/120/150  
120/150/200  
120/150/200  
10  
10  
5
5
5
5
5
5
0~70(Normal)  
-40~85(E.T.)  
0~70(Normal)  
-40~85(E.T.)  
0~70(Normal)  
-40~85(E.T.)  
0~70(Normal)  
-40~85(E.T.)  
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature  
2. Current value is max.  
PIN CONNECTION ( Top View )  
BLOCK DIAGRAM  
ROW DECODER  
I/O1  
A0  
A0 A1 CS2 A3 A6 A8  
IO5 A2 /WE A4 A7 IO1  
IO6  
Vss  
Vcc  
IO7  
NC A5  
IO2  
Vcc  
Vss  
IO3  
MEMORY ARRAY  
2048x1024  
A
1
7
I/O8  
NC A17  
/CS1  
CS2  
IO8 /OE /CS1 A16 A15 IO4  
A9 A10 A11 A12 A13 A14  
/WE  
/OE  
PIN DESCRIPTION  
Pin Name  
/CS1  
Pin Function  
Pin Name  
Pin Function  
Address Input  
Chip Select 1  
Chip Select 2  
Write Enable  
Output Enable  
A0 ~ A17  
CS2  
/WE  
/OE  
I/O1 ~ I/O8  
Vcc  
Data Input/Output  
Power(3.0V, 2.5V, 2.0V or 1.8V)  
Ground  
Vss  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev.04 /Feb. 99  
Hyundai Semiconductor  
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
ORDERING INFORMATION  
Part No.  
Speed  
70/85/100  
70/85/100  
70/85/100  
70/85/100  
85/100/120  
85/100/120  
85/100/120  
85/100/120  
100/120/150  
100/120/150  
100/120/150  
100/120/150  
120/150/200  
120/150/200  
120/150/200  
120/150/200  
Power  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
Temp.  
Package  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
HY62UF8200LLM  
HY62UF8200SLM  
HY62UF8200LLM-I  
HY62UF8200SLM-I  
HY62QF8200LLM  
HY62QF8200SLM  
HY62QF8200LLM-I  
HY62QF8200SLM-I  
HY62EF8200LLM  
HY62EF8200SLM  
HY62EF8200LLM-I  
HY62EF8200SLM-I  
HY62SF8200LLM  
HY62SF8200SLM  
HY62SF8200LLM-I  
HY62SF8200SLM-I  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature  
ABSOLUTE MAXIMUM RATING (1)  
Symbol  
VIN, VOUT  
Vcc  
Parameter  
Input/Output Voltage  
Power Supply  
Rating  
-0.2 to 3.6  
-0.2 to 4.0  
0 to 70  
Unit  
V
V
Remark  
TA  
Operating Temperature  
HY62UF8200  
HY62QF8200  
HY62EF8200  
HY62SF8200  
HY62UF8200-I  
HY62QF8200-I  
HY62EF8200-I  
HY62SF8200-I  
°C  
-40 to 85  
°C  
TSTG  
PD  
Storage Temperature  
Power Dissipation  
-55 to 150  
1.0  
°C  
W
TSOLDER  
Lead Soldering Temperature & Time  
260 · 5  
°C·sec  
Note  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent  
damage to the device. This is stress rating only and the functional operation of the device under these or  
any other conditions above those indicated in the operation of this specification is not implied.  
Exposure to the absolute maximum rating conditions for extended period may affect reliability.  
Rev.04 /Feb.99  
2
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
RECOMMENDED DC OPERATING CONDITION  
Symbol  
Vcc  
Parameter  
Supply Voltage  
Product  
Min.  
2.7  
2.2  
1.8  
1.6  
0
Typ.  
3.0  
2.5  
2.0  
1.8  
0
Max.  
3.3  
2.8  
2.2  
2.0  
0
Unit  
V
V
V
HY62UF8200-(I)  
HY62QF8200-(I)  
HY62EF8200-(I)  
HY62SF8200-(I)  
HY62UF8200-(I)  
HY62QF8200-(I)  
HY62EF8200-(I)  
HY62SF8200-(I)  
Vss  
VIH  
Ground  
V
Input High Voltage HY62UF8200-(I)  
HY62QF8200-(I)  
2.2  
2.0  
1.6  
1.4  
-0.2(1)  
-
-
-
Vcc+0.2  
Vcc+0.2  
Vcc+0.2  
Vcc+0.2  
0.4  
V
V
V
V
V
HY62EF8200-(I)  
HY62SF8200-(I)  
VIL  
Input Low Voltage HY62UF8200-(I)  
HY62QF8200-(I)  
-
HY62EF8200-(I)  
HY62SF8200-(I)  
Note : 1. VIL = -1.5V for pulse width less than 30ns  
TRUTH TABLE  
/CS1 CS2  
/WE /OE  
MODE  
Standby  
I/O OPERATION  
High-Z  
Supply Current  
Isb, Isb1  
H
X
L
L
L
X
L
H
H
H
X
X
H
H
L
X
X
H
L
Output Disabled High-Z  
Read  
Write  
Icc  
Icc  
Icc  
Data Out  
Data In  
X
Note :  
1. H=VIH, L=VIL, X=don't care  
Rev.04 /Feb.99  
3
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
DC ELECTRICAL CHARACTERISTICS  
Vcc = 3.0V±10%/2.5V±10%/2.0V±10%/1.8V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.)  
Sym  
ILI  
ILO  
Parameter  
Input Leakage Current  
Output Leakage Current  
Test Condition  
Vss < VIN < Vcc  
Vss < VOUT < Vcc, /CS1 = VIH or  
CS2 = VIL or /OE = VIH or /WE = VIL  
Min.  
-1  
-1  
Typ.  
-
-
Max.  
1
1
Unit  
uA  
uA  
Icc  
Operating Power Supply  
Current  
/CS1 = VIL,  
CS2 = VIH,  
VIN = VIH or VIL,  
II/O = 0mA  
Vcc = 3.0V  
-
-
5
3
10  
5
mA  
mA  
Vcc = 2.5V/2V/  
1.8V  
ICC1  
Average  
HY62UF8200-(I) /CS1 = VIL CS2 = VIH,  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55  
40  
25  
20  
0.5  
0.3  
0.3  
0.3  
2
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
uA  
Operating HY62QF8200-(I) Min Duty Cycle = 100%, II/O = 0mA  
Current  
HY62EF8200-(I)  
HY62SF8200-(I)  
HY62UF8200-(I) /CS1 = VIH or CS2 = VIL  
HY62QF8200-(I)  
HY62EF8200-(I)  
ISB  
TTL  
Standby  
Current  
(TTL Input)  
HY62SF8200-(I)  
-
0.05  
-
ISB1  
VOL  
Standby Current  
(CMOS Input)  
/CS1 > Vcc - 0.2V,  
CS2 > Vcc - 0.2V or  
CS2 < 0.2V  
SL  
LL  
10  
uA  
Output Low Voltage  
Vcc = 3.0V  
Vcc = 2.5V  
IOL = 2.1mA  
IOL = 0.5mA  
-
-
0.4  
V
Vcc = 2.0V  
Vcc = 1.8V  
HY62UF8200-(I) Vcc = 3.0V  
HY62QF8200-(I) Vcc = 2.5V  
HY62EF8200-(I) Vcc = 2.0V  
HY62SF8200-(I) Vcc = 1.8V  
IOL = 0.33mA  
IOL = 0.26mA  
IOH = -1.0mA  
IOH = -0.5mA  
IOH = -0.44mA  
IOH = -0.44mA  
VOH  
Output  
High  
Voltage  
2.2  
2.0  
1.6  
1.4  
-
-
-
-
-
-
-
-
V
V
V
V
Note : Typical values are at Vcc = 3.0V/2.5V/2.0V/1.8V, TA = 25°C  
Rev.04 /Feb.99  
4
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
AC CHARACTERISTICS  
Vcc = 3.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-70  
Max. Min.  
-85  
Max. Min  
-10  
Max.  
#
Symbol  
Parameter  
Unit  
Min.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
Output Hold from Address Change  
70  
-
-
-
10  
5
0
0
10  
-
85  
-
-
-
10  
5
0
0
10  
-
100  
-
-
-
20  
5
0
0
15  
-
100  
100  
50  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
70  
70  
40  
-
85  
85  
45  
-
-
-
-
30  
30  
-
30  
30  
-
30  
30  
-
WRITE CYCLE  
10 tWC  
11 tCW  
12 tAW  
13 tAS  
14 tWP  
15 tWR  
16 tWHZ  
17 tDW  
18 tDH  
19 tOW  
Write Cycle Time  
70  
60  
60  
0
50  
0
0
30  
0
-
-
-
-
-
-
25  
-
-
-
85  
70  
70  
0
55  
0
0
35  
0
-
-
-
-
-
-
30  
-
-
-
100  
80  
80  
0
75  
0
0
45  
0
-
-
-
-
-
-
35  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
5
5
10  
Vcc = 2.5V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-85  
Max. Min.  
-10  
Max. Min  
-12  
#
Symbol  
Parameter  
Unit  
Min.  
Max.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
Output Hold from Address Change  
85  
-
-
-
10  
5
0
0
10  
-
100  
-
-
-
20  
5
0
0
15  
-
100  
100  
50  
-
120  
-
-
-
120  
120  
60  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
85  
85  
45  
-
-
20  
10  
0
0
15  
-
-
-
30  
30  
-
30  
30  
-
40  
40  
-
WRITE CYCLE  
10 tWC  
11 tCW  
12 tAW  
13 tAS  
14 tWP  
15 tWR  
16 tWHZ  
17 tDW  
18 tDH  
19 tOW  
Write Cycle Time  
85  
70  
70  
0
55  
0
0
35  
0
-
-
-
-
-
-
30  
-
-
-
100  
80  
80  
0
75  
0
0
45  
0
-
-
-
-
-
-
35  
-
-
-
120  
100  
100  
0
85  
0
0
50  
0
-
-
-
-
-
-
40  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
5
10  
10  
Rev.04 /Feb.99  
5
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
Vcc = 2.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-100  
Max. Min.  
-120  
Max. Min  
-150  
Max.  
#
Symbol  
Parameter  
Unit  
Min.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
Output Hold from Address Change  
100  
-
-
-
20  
5
0
0
15  
-
100  
100  
50  
-
120  
-
-
-
120  
120  
60  
-
150  
-
-
-
150  
150  
75  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
20  
10  
0
0
15  
20  
10  
0
0
15  
-
-
-
30  
30  
-
40  
40  
-
50  
50  
-
WRITE CYCLE  
10 tWC  
11 tCW  
12 tAW  
13 tAS  
14 tWP  
15 tWR  
16 tWHZ  
17 tDW  
18 tDH  
19 tOW  
Write Cycle Time  
100  
80  
80  
0
75  
0
0
45  
0
-
-
-
-
-
-
35  
-
-
-
120  
100  
100  
0
85  
0
0
50  
0
-
-
-
-
-
-
40  
-
-
-
150  
120  
120  
0
100  
0
0
60  
0
-
-
-
-
-
-
50  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
10  
10  
10  
Vcc = 1.8V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-12  
Max. Min.  
-15  
Max. Min  
-20  
#
Symbol  
Parameter  
Unit  
Min.  
Max.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
Output Hold from Address Change  
120  
-
-
-
120  
120  
60  
-
150  
-
-
-
150  
150  
75  
-
200  
-
-
-
200  
200  
100  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
-
20  
10  
0
0
15  
20  
10  
0
0
15  
30  
15  
0
0
30  
-
-
-
40  
40  
-
50  
50  
-
60  
60  
-
WRITE CYCLE  
10 tWC  
11 tCW  
12 tAW  
13 tAS  
14 tWP  
15 tWR  
16 tWHZ  
17 tDW  
18 tDH  
19 tOW  
Write Cycle Time  
120  
100  
100  
0
85  
0
0
50  
0
-
-
-
-
-
-
60  
-
-
-
150  
120  
120  
0
100  
0
0
60  
0
-
-
-
-
-
-
70  
-
-
-
200  
170  
170  
0
135  
0
0
80  
0
-
-
-
-
-
-
80  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
10  
15  
15  
Rev.04 /Feb.99  
6
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
AC TEST CONDITIONS  
TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.), unless otherwise specified  
PARAMETER Value  
0.4V to 2.2V  
Input Pulse Level  
HY62UF8200-(I)  
HY62QF8200-(I)  
HY62EF8200-(I)  
HY62SF8200-(I)  
0.4V to 2.2V  
0.4V to 1.8V  
0.4V to 1.6V  
Input Rise and Fall Time  
Input and Output  
Timing Reference  
5ns  
1.5V  
1.1V  
0.9V  
HY62UF8200-(I)  
HY62QF8200-(I)  
HY62EF8200-(I)  
HY62SF8200-(I)  
Level  
0.8V  
Output Load  
CL = 30pF + 1TTL Load  
AC TEST LOADS  
VTM(2)  
3070 Ohm  
3150 Ohm  
DOUT  
CL(1)  
Note  
1. Including jig and scope capacitance  
2. VTM = 2.8V for Vcc = 3.0V : HY62UF8200-(I)  
VTM = 2.3V for Vcc = 2.5V : HY62QF8200-(I)  
VTM = 1.8V for Vcc = 2.0V : HY62EF8200-(I)  
VTM = 1.6V for Vcc = 1.8V : HY62SF8200-(I)  
CAPACITANCE  
(Temp = 25°C, f= 1.0MHz)  
Symbol  
CIN  
COUT  
Parameter  
Input Capacitance(Add, /CS, /WE, /OE)  
Output Capacitance(I/O)  
Condition  
VIN = 0V  
VI/O = 0V  
Max.  
8
10  
Unit  
pF  
pF  
Note : These parameters are sampled and not 100% tested  
Rev.04 /Feb.99  
7
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
TIMING DIAGRAM  
READ CYCLE 1  
tRC  
ADDR  
OE  
tAA  
tOE  
tOLZ  
tOH  
CS1  
CS2  
tACS  
tCLZ  
tOHZ  
tCHZ  
High-Z  
Data  
Out  
Data Valid  
Note(READ CYCLE):  
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are  
not referenced to output voltage levels  
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given  
device and from device to device.  
3. /WE is high for the read cycle.  
READ CYCLE 2  
tRC  
ADDR  
tAA  
tOH  
tOH  
Data  
Out  
Previous Data  
Data Valid  
Note(READ CYCLE):  
1. /WE is high for the read cycle.  
2. Device is continuously selected /CS1 = VIL, CS2 = VIH.  
3. /OE =VIL.  
Rev.04 /Feb.99  
8
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
WRITE CYCLE 1(/WE Controlled)  
tWC  
ADDR  
CS1  
tAW  
tWR  
tCW  
CS2  
tWP  
tAS  
WE  
tDW  
tDH  
Data Valid  
Data In  
tOHZ  
tOW  
High-Z  
Data  
Out  
Data Undefined  
WRITE CYCLE 2 (/CS1 Controlled)  
tWC  
ADDR  
tWR  
tAS  
tCW  
CS1  
tAW  
CS2  
WE  
tWP  
tDH  
tDW  
Data Valid  
Data In  
High-Z  
tCLZ  
tWHZ  
Data  
Out  
High-Z  
High-Z  
Rev.04 /Feb.99  
9
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
WRITE CYCLE 3 (CS2 Controlled)  
tWC  
ADDR  
tAS  
tWR  
tCW  
CS1  
tAW  
CS2  
WE  
tWP  
tDW  
Data Valid  
tDH  
Data In  
High-Z  
tCLZ  
tWHZ  
High-Z  
Data  
High-Z  
Out  
Notes(WRITE CYCLE):  
1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition  
among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among  
/CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of  
write.  
.
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write .  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as  
/CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low.  
5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,  
input of opposite phase of the output must not be applied because bus contention can occur.  
6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state.  
7. Dout is the read data of the new address.  
8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite  
phase leading to the outputs should not be applied.  
Rev.04 /Feb.99  
10  
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
DATA RETENTION ELECTRIC CHARACTERISTIC  
TA=0°C to 70°C (Normal)/-40°C to 85°C (E.T.)  
Symbol  
VDR  
Parameter  
Vcc for Data Retention  
Test Condition  
/CS1 > Vcc-0.2V,  
Min  
1.5  
Typ  
-
Max  
3.3  
Unit  
V
CS2 < 0.2V or > Vcc-0.2V,  
Vss < VIN¡ VÂcc  
ICCDR  
Data Retention Current  
Vcc=2.0V, /CS1 > Vcc - 0.2V,  
CS2 < 0.2V or > Vcc-0.2V,  
Vss < VIN < Vcc  
LL  
SL  
-
-
-
-
10  
2
uA  
uA  
tCDR  
tR  
Chip Deselect to Data  
Retention Time  
Operating Recovery Time  
See Data Retention Timing Diagram  
0
-
-
-
-
ns  
ns  
tRC(2)  
Notes:  
1. Typical values are under the condition of TA = 25°C.  
2. tRC is read cycle time.  
DATA RETENTION TIMING DIAGRAM 1  
DATA RETENTION MODE  
VCC  
2.7/2.2V  
1.8/1.6V  
tCDR  
tR  
VIH  
VDR  
CS1>VCC-0.2V  
CS1  
VSS  
DATA RETENTION TIMING DIAGRAM 2  
DATA RETENTION MODE  
VCC  
2.7/2.2V  
1.8/1.6V  
tCDR  
tR  
CS2  
VDR  
0.4V  
VSS  
CS2<0.2V  
Note :  
1. 2.7V : HY62UF8200 and HY62UF8200-I  
2.2V : HY62QF8200 and HY62QF8200-I  
1.8V : HY62EF8200 and HY62EF8200-I  
1.6V : HY62SF8200 and HY62SF8200-I  
RELIABILITY SPEC.  
Rev.04 /Feb.99  
11  
HY62UF8200/HY62QF8200/HY62EF8200/HY62SF8200 Series  
TEST MODE  
HBM  
TEST SPEC.  
> 2000V  
ESD  
MM  
> 250V  
LATCH - UP  
< -100mA  
> 100mA  
PACKAGE INFORMATION  
48ball Micro Ball Grid Array Package(M)  
B
A
A1 CORNER  
INDEX AREA  
6
5
4
3
2
1
A
A
B
C
D
C
C1  
E
3.0 X 5.0 MIN  
FLAT AREA  
F
G
H
C1/2  
B1/2  
B1  
BUMP VIEW  
TOP VIEW  
6
E1  
E2  
C
E
SEATING PLANE  
4
A
r
3 D(DIAMETER)  
SIDE VIEW  
Note  
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.  
2. ALL DIMENSIONS ARE MILLIMETERS.  
Symbol  
Min.  
-
-
6.65  
-
9.2  
0.3  
0.85  
0.6  
0.2  
-
Typ.  
0.75  
3.75  
6.7  
5.25  
9.25  
0.35  
0.9  
Max.  
-
-
6.8  
-
9.35  
0.4  
0.95  
0.7  
0.3  
0.08  
A
B
B1  
C
C1  
D
E
E1  
E2  
r
3. DIMENSION “ D” IS MEASURED AT THE MAXIMUM SOLDER  
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.  
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE  
CROWN OF THE SOLDER BALLS.  
5. SOLDER BALL ARRAY MAY BE DEPOPULATED BY OMISSION  
BALLS FROM A FULL MATRIX. NO SHIFTING OF MATRIX  
PATTERN IS ALLOWED.  
0.65  
0.25  
-
6. THIS IS A CONTROLLING DIMENSION.  
Rev.04 /Feb.99  
12  

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