HY62KF08401C-SS [HYNIX]
512Kx8bit full CMOS SRAM; 512Kx8bit全CMOS SRAM
| 型号： | HY62KF08401C-SS |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 512Kx8bit full CMOS SRAM |
| 文件： | 总10页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY62KF08401C Series
512Kx8bit full CMOS SRAM
Document Title
512K x 8bit 2.7 ~ 3.6V Super low Power FCMOS Slow SRAM
Revision History
Revision No History
Draft Date
Remark
Final
00
01
Initial Draft
Mar.21.2001
Jun.07.2001
Changed Isb1 values
Final
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev.01 / Jun.01
Hynix Semiconductor
HY62KF08401C Series
DESCRIPTION
FEATURES
The HY62KF08401C is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
512K words by 8bits. The HY62KF08401C uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
·
·
·
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup
-. 1.2V(min) data retention
Standard pin configuration
·
-. 32 - sTSOP - 8X13.4(Standard)
Standby
Temperature
Current(uA)
Voltage
Operation
Current/Icc(mA)
Product No.
Speed (ns)
55/70
(V)
(°C)
LL
15
SL
6
HY62KF08401C-I 2.7~3.6
5
-40~85
Note 1. I : Industrial
2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
ROW
DECODER
A11
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A0
A10
/CS
I/O1
A13
/WE
A18
A15
VCC
A17
A16
A14
A12
A7
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
MEMORY ARRAY
512K x 8
I/O8
A0
A1
A2
A3
A18
A6
A5
A4
/CS
/OE
/WE
32-sTSOP Forward
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
/CS
Chip Select
I/O1 ~ I/O8
Vcc
Data Input/Output
Power (2.7~3.6V)
Ground
/WE
Write Enable
Output Enable
Address Input
/OE
Vss
A0 ~ A18
Rev.01 / Jun.01
2
HY62KF08401C Series
ORDERING INFORMATION
Part No.
HY62KF08401C-DS(I)
HY62KF08401C-SS(I)
Speed
55/70
55/70
Power
LL-part
SL-part
Temp.
Package
sTSOP
sTSOP
I
I
Note 1. I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
TA
TSTG
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Rating
-0.3 to 3.6
-0.3 to 4.6
-40 to 85
-55 to 150
1.0
Unit
V
V
°C
°C
Remark
HY62KF08401C-I
PD
W
TSOLDER
Ball Soldering Temperature & Time
260 · 10
°C·sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS
H
/WE /OE
MODE
Deselected
Output Disabled
Read
I/O OPERATION
High-Z
Supply Current
Standby
X
H
L
X
H
L
High-Z
Dout
Din
Active
L
Active
X
Write
Note:
1. H=VIH, L=VIL, X=don't care (VIL or VIH)
Rev.01 / Jun.01
2
HY62KF08401C Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
Typ
3.0 or 3.3
Max.
3.6
0
Vcc+0.3
0.6
Unit
V
V
V
V
0
-
-
2.2
-0.31.
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C
Sym
ILI
Parameter
Test Condition
Vss < VIN < Vcc
Min Typ1. Max Unit
Input Leakage Current
-1
-
1
uA
Vss < VOUT < Vcc, /CS = VIH or
/OE = VIH or /WE = VIL
/CS = VIL,
ILO
Icc
Output Leakage Current
-1
-
1
uA
Operating Power Supply Current
5
mA
mA
mA
VIN = VIH or VIL, II/O = 0mA
/CS = VIL,
2.7~3.6V
2.7~3.3V
45
40
VIN = VIH or VIL,
Cycle Time = Min,
100% Duty, II/O = 0mA
/CS < 0.2V,
ICC1
Average Operating Current
VIN < 0.2V or VIN > Vcc-0.2V,
Cycle Time = 1us,
100% Duty, II/O = 0mA
/CS = VIH or VIN = VIH or VIL
/CS > Vcc - 0.2V or
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
5
mA
ISB
Standby Current (TTL Input)
Standby Current (CMOS Input)
0.5
15
mA
uA
LL
0.2
0.2
ISB1
SL
6
uA
VOL
VOH
Output Low
Output High
IOL = 2.1mA
IOH = -1.0mA
-
-
-
0.4
-
V
V
2.4
Note
1. Typical values are at Vcc = 3.0V TA = 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance (Add, /CS, /WE, /OE)
Output Capacitance (I/O)
Condition
VIN = 0V
VI/O = 0V
Max.
8
10
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.01 / Jun.01
3
HY62KF08401C Series
AC CHARACTERISTICS
TA = -40°C to 85°C, unless otherwise specified
55ns
70ns
#
Symbol
Parameter
Unit
Min. Max. Min. Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
55
-
-
-
10
5
0
0
10
-
70
-
-
-
10
5
0
0
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
30
-
70
70
35
-
-
-
30
30
-
30
30
-
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWR
16 tWHZ
17 tDW
18 tDH
19 tOW
Write Cycle Time
55
50
50
0
45
0
0
25
0
-
-
-
-
-
-
20
-
-
-
70
60
60
0
50
0
0
30
0
-
-
-
-
-
-
20
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
5
5
AC TEST CONDITIONS
TA = -40°C to 85°C, unless otherwise specified
Parameter
Value
Input Pulse Level
Input Rise and Fall Time
0.4V to 2.2V
5ns
Input and Output Timing Reference Level
Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW
Others
1.5V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=2.8V
1029 Ohm
DOUT
CL(1)
1728 Ohm
Note
1. Including jig and scope capacitance
Rev.01 / Jun.01
4
HY62KF08401C Series
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
tRC
ADDR
/CS
tAA
tACS
tOH
tCHZ(3)
tOE
/OE
tOLZ(3)
tOHZ(3)
tCLZ(3)
Data
High-Z
Out
Data Valid
READ CYCLE 2 (Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Previous Data
Out
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
tACS
tCLZ(3)
tCHZ(3)
Data
Out
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
Rev.01 / Jun.01
5
HY62KF08401C Series
WRITE CYCLE 1(1,4,8) (/WE Controlled)
tWC
tCW
ADDR
tWR(2)
/CS
tAW
tWP
/WE
tAS
tDW
Data Valid
tDH
High-Z
Data In
tWHZ(3,8)
(5)
(6)
tOW
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC
ADDR
tAS
tWR(2)
tCW
/CS
tAW
tWP
/WE
tDW
Data Valid
tDH
High-Z
Data In
High-Z
Data
Out
Rev.01 / Jun.01
6
HY62KF08401C Series
Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occurs simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
/CS > Vcc - 0.2V,
Min
Typ1. Max
Unit
VDR
Vcc for Data Retention
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
Vcc=1.5V,
/CS > Vcc - 0.2V or
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
1.2
-
3.6
V
LL
-
-
0.1
0.1
10
3
uA
uA
Iccdr
Data Retention Current
SL
Chip Deselect to Data
Retention Time
Operating Recovery Time
tCDR
tR
0
-
-
-
-
ns
ns
See Data Retention Timing Diagram
tRC
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical value are sampled and not 100% tested
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
VIH
VDR
/CS >VCC-0.2V
/CS
VSS
Rev.01 / Jun.01
7
HY62KF08401C Series
PACKAGE INFORMATION
32pin 8x13.4mm Smaller Thin Small Outline Package Standard(S)
#1
#32
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
#17
#16
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
0.020(0.50)
0.008(0.2)
0.004(0.1)
0.024(0.6)
0.016(0.4)
0.011(0.27)
0.007(0.17)
Rev.01 / Jun.01
8
HY62KF08401C Series
MARKING INFORMATION
Package
Marking Example
H
1
y
Y
C
y
6
-
2
c
K
S
p
F
s
0
s
8
t
4
0
sTSOP
w
w
K
O
R
Index
• HY62KF08401C
• c
: Part Name
: Power Consumption
- D
- S
: Low Low Power
: Super Low Power
• S
: Package Type
- S
: sTSOP
• ss
: Speed
- 55
: 55ns
: 70ns
- 70
• t
: Temperature
- I
: Industrial ( -40 ~ 85 °C )
• yy
: Year ( ex : 00 = year 2000, 01 = year 2001 )
: work week ( ex : 12 = ww12 )
: Process Code
• ww
• p
• KOR
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.01 / Jun.01
9
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