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HY62SF16200SLM-15I [HYNIX]

Standard SRAM, 128KX16, 150ns, CMOS, PBGA48, MICRO, BGA-48;
HY62SF16200SLM-15I
型号： HY62SF16200SLM-15I
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

Standard SRAM, 128KX16, 150ns, CMOS, PBGA48, MICRO, BGA-48

静态存储器 内存集成电路
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Y62UF16200/ HY62QF16200/ HY62EF16200/  
HY62SF16200 Series 128Kx16bit full CMOS SRAM  
DESCRIPTION  
FEATURES  
·
·
·
Fully static operation and Tri-state output  
TTL compatible inputs and outputs  
Battery backup(LL/SL-part)  
- 1.5V(min) data retention  
Standard pin configuration  
- 48ball uBGA  
The  
HY62UF16200  
/
HY62QF16200  
/
HY62EF16200 / HY62SF16200 is a high speed,  
super low power and 2M bit full CMOS SRAM  
organized as 131,072 words by 16bits. The  
HY62UF16200 / HY62QF16200 / HY62EF16200 /  
HY62SF16200 uses high performance full CMOS  
process technology and is designed for high  
speed and low power circuit technology. It is  
particularly well-suited for the high density low  
power system application. This device has a data  
retention mode that guarantees data to remain  
valid at a minimum power supply voltage of 1.5V.  
·
Product  
No.  
Voltage  
(V)  
Speed  
(ns)  
Operation  
Current(mA)  
Standby Current(uA)  
Temperature  
(°C)  
LL  
10  
10  
10  
10  
10  
10  
10  
10  
SL  
2
2
2
2
2
2
2
2
HY62UF16200  
HY62UF16200-I  
HY62QF16200  
HY62QF16200-I  
HY62EF16200  
HY62EF16200-I  
HY62SF16200  
HY62SF16200-I  
3.0  
3.0  
2.5  
2.5  
2.0  
2.0  
1.8  
1.8  
70/85/100  
70/85/100  
85/100/120  
85/100/120  
100/120/150  
100/120/150  
120/150/200  
120/150/200  
15  
15  
10  
10  
10  
10  
10  
10  
0~70(Normal)  
-40~85(E.T.)  
0~70(Normal)  
-40~85(E.T.)  
0~70(Normal)  
-40~85(E.T.)  
0~70(Normal)  
-40~85(E.T.)  
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature  
2. Current value is max.  
PIN CONNECTION (Top View )  
BLOCK DIAGRAM  
ROW  
DECODER  
A0  
/LB /OE A0 A1 A2 NC  
IO9 /UB A3 A4 /CS IO1  
IO10 IO11 A5 A6 IO2 IO3  
Vss IO12 NC A7 IO4 Vcc  
Vcc IO13 NC A16 IO5 Vss  
IO15 IO14 A14 A15 IO6 IO7  
IO16 NC A12 A13 /WE IO8  
NC A8 A9 A10 A11 NC  
I/O1  
I/O8  
I/O9  
MEMORY ARRAY  
1024x128x16  
I/O16  
A16  
/CS  
/OE  
/LB  
/UB  
/WE  
PIN DESCRIPTION  
Pin Name  
/CS  
/WE  
/OE  
/LB  
Pin Funtion  
Chip Select  
Write Enable  
Output Enable  
Low Byte Control(I/O1~I/O8)  
Pin Name  
I/O1~I/O16  
A0~A16  
Vcc  
Pin Funtion  
Data Input/Output  
Address Input  
Power(3.0V/2.5V/2.0V/1.8V)  
Ground  
Vss  
/UB  
Upper Byte Control(I/O9~I/O16) NC  
No Connection  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev.02 /Feb.99  
Hyundai Semiconductor  
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
ORDERING INFORMATION  
Part No.  
Speed  
70/85/100  
70/85/100  
70/85/100  
70/85/100  
85/100/120  
85/100/120  
85/100/120  
85/100/120  
100/120/150  
100/120/150  
100/120/150  
100/120/150  
120/150/200  
120/150/200  
120/150/200  
120/150/200  
Power  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
LL-part  
SL-part  
Temp.  
Package  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
uBGA  
HY62UF16200LLM  
HY62UF16200SLM  
HY62UF16200LLM-I  
HY62UF16200SLM-I  
HY62QF16200LLM  
HY62QF16200SLM  
HY62QF16200LLM-I  
HY62QF16200SLM-I  
HY62EF16200LLM  
HY62EF16200SLM  
HY62EF16200LLM-I  
HY62EF16200SLM-I  
HY62SF16200LLM  
HY62SF16200SLM  
HY62SF16200LLM-I  
HY62SF16200SLM-I  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
E.T.  
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature  
ABSOLUTE MAXIMUM RATING (1)  
Symbol  
VIN, VOUT  
Vcc  
Parameter  
Input/Output Voltage  
Power Supply  
Rating  
-0.2 to 3.6  
-0.2 to 4.0  
0 to 70  
Unit  
V
V
Remark  
TA  
Operating Temperature  
HY62UF16200  
HY62QF16200  
HY62EF16200  
HY62SF16200  
HY62UF16200-I  
HY62QF16200-I  
HY62EF16200-I  
HY62SF16200-I  
°C  
-40 to 85  
°C  
TSTG  
PD  
Storage Temperature  
Power Dissipation  
-55 to 150  
1.0  
°C  
W
TSOLDER  
Lead Soldering Temperature & Time  
260 · 5  
°C·sec  
Note  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent  
damage to the device. This is stress rating only and the functional operation of the device under these or  
any other conditions above those indicated in the operation of this specification is not implied.  
Exposure to the absolute maximum rating conditions for extended period may affect reliability.  
Rev.04 /Feb.99  
2
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
RECOMMENDED DC OPERATING CONDITION  
Symbol  
Vcc  
Parameter  
Supply Voltage  
Product  
Min.  
2.7  
2.2  
1.8  
1.6  
0
Typ.  
3.0  
2.5  
2.0  
1.8  
0
Max.  
3.3  
2.8  
2.2  
2.0  
0
Unit  
V
V
HY62UF16200-(I)  
HY62QF16200-(I)  
HY62EF16200-(I)  
HY62SF16200-(I)  
HY62UF16200-(I)  
HY62QF16200-(I)  
HY62EF16200-(I)  
HY62SF16200-(I)  
V
Vss  
VIH  
Ground  
V
Input High Voltage HY62UF16200-(I)  
HY62QF16200-(I)  
2.2  
2.0  
-
-
-
Vcc+0.2  
Vcc+0.2  
Vcc+0.2  
Vcc+0.2  
0.4  
V
V
V
V
V
HY62EF16200-(I)  
1.6  
HY62SF16200-(I)  
1.4  
VIL  
Input Low Voltage HY62UF16200-(I)  
HY62QF16200-(I)  
-0.2(1)  
-
HY62EF16200-(I)  
HY62SF16200-(I)  
Note : 1. VIL = -1.5V for pulse width less than 30ns  
TRUTH TABLE  
I/O Pin  
Supply Current  
Mode  
/LB  
/CS /WE  
/OE  
/UB  
I/O1~I/O8  
Hi-Z  
I/O9~I/O16  
Hi-Z  
H
L
L
L
X
H
X
H
X
H
X
L
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
Not Selected  
Output Disabled  
ISB, ISB1  
Icc  
Hi-Z  
Hi-Z  
DOUT  
Hi-Z  
DOUT  
DIN  
Hi-Z  
Hi-Z  
Hi-Z  
DOUT  
DOUT  
Hi-Z  
DIN  
DIN  
Read  
Write  
Icc  
Icc  
L
L
X
Hi-Z  
DIN  
L
Note:  
1. H=VIH, L=VIL, X=don't care  
2. UB, LB(Upper, Lower Byte enable)  
These active LOW inputs allow individual bytes to be written or read.  
When LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.  
When UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.  
Rev.04 /Feb.99  
3
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
DC ELECTRICAL CHARACTERISTICS  
Vcc = 3.0V±10%/2.5V±10%/2.0V±10%/1.8V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.)  
Sym  
ILI  
ILO  
Parameter  
Input Leakage Current  
Output Leakage Current  
Test Condition  
Vss < VIN < Vcc  
Vss < VOUT < Vcc, /CS = VIH or  
/OE = VIH or /WE = VIL  
Min.  
-1  
-1  
Typ.  
-
-
Max.  
1
1
Unit  
uA  
uA  
/UB = VIH or /LB = VIH  
Icc  
Operating Power Supply  
Current  
/CS = VIL,  
VIN = VIH or VIL  
II/O = 0mA  
Vcc = 3.0V  
Vcc = 2.5V/2V/  
1.8V  
-
-
8
5
15  
10  
mA  
mA  
ICC1  
Average  
HY62UF16200-(I) /CS = VIL, Min Duty Cycle = 100%  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80  
60  
40  
35  
0.5  
0.3  
0.3  
0.3  
2
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
uA  
Operating HY62QF16200-(I) II/O = 0mA  
Current  
HY62EF16200-(I)  
HY62SF16200-(I)  
HY62UF16200-(I) /CS = VIH  
HY62QF16200-(I)  
HY62EF16200-(I)  
ISB  
TTL  
Standby  
Current  
(TTL Input)  
HY62SF16200-(I)  
ISB1  
VOL  
Standby Current  
(CMOS Input)  
Output Low Voltage  
/CS > Vcc - 0.2V  
SL  
LL  
0.05  
-
-
10  
0.4  
uA  
V
Vcc = 3.0V  
Vcc = 2.5V  
Vcc = 2.0V  
Vcc = 1.8V  
IOL = 2.1mA  
IOL = 0.5mA  
IOL = 0.33mA  
IOL = 0.26mA  
IOH = -1.0mA  
IOH = -0.5mA  
IOH = -0.44mA  
IOH = -0.44mA  
VOH  
Output  
High  
Voltage  
HY62UF16200-(I) Vcc = 3.0V  
HY62QF16200-(I) Vcc = 2.5V  
HY62EF16200-(I) Vcc = 2.0V  
HY62SF16200-(I) Vcc = 1.8V  
2.2  
2.0  
1.6  
1.4  
-
-
-
-
-
-
-
-
V
V
V
V
Note : Typical values are at Vcc = 3.0V/2.5V/2.0V/1.8V, TA = 25°C  
Rev.04 /Feb.99  
4
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
AC CHARACTERISTICS  
Vcc = 3.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-70  
Max. Min.  
-85  
Max. Min  
-10  
Max.  
#
Symbol  
Parameter  
Unit  
Min.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tBA  
tCLZ  
tOLZ  
tBLZ  
tCHZ  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
/LB, /UB Access Time  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
/LB, /UB Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
/LB, /UB Disable to Output in High Z  
Output Hold from Address Change  
70  
-
-
-
-
10  
5
5
0
0
-
85  
-
-
-
-
10  
5
10  
0
0
0
-
100  
-
-
-
-
20  
5
10  
0
0
0
-
100  
100  
50  
50  
-
-
-
30  
30  
30  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
70  
70  
40  
40  
-
-
-
30  
30  
30  
-
85  
85  
45  
45  
-
-
-
30  
30  
30  
-
10 tOHZ  
11 tBHZ  
12 tOH  
0
10  
10  
15  
WRITE CYCLE  
13 tWC  
14 tCW  
15 tAW  
16 tBW  
17 tAS  
18 tWP  
19 tWR  
20 tWHZ  
21 tDW  
22 tDH  
23 tOW  
Write Cycle Time  
70  
60  
60  
60  
0
50  
0
0
-
-
-
-
-
-
-
25  
-
-
85  
70  
70  
70  
0
55  
0
0
-
-
-
-
-
-
-
30  
-
-
100  
80  
80  
80  
0
75  
0
0
-
-
-
-
-
-
-
35  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
/LB, /UB Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
30  
0
5
35  
0
5
45  
0
10  
-
-
-
Rev.04 /Feb.99  
5
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
Vcc = 2.5V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-85  
Max. Min.  
-10  
Max. Min  
-12  
Max.  
#
Symbol  
Parameter  
Unit  
Min.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tBA  
tCLZ  
tOLZ  
tBLZ  
tCHZ  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
/LB, /UB Access Time  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
/LB, /UB Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
/LB, /UB Disable to Output in High Z  
Output Hold from Address Change  
85  
-
-
-
-
10  
5
10  
0
0
0
-
100  
-
-
-
-
20  
5
10  
0
0
0
-
100  
100  
50  
50  
-
-
-
30  
30  
30  
-
120  
-
-
-
-
20  
10  
10  
0
0
0
-
120  
120  
60  
60  
-
-
-
40  
40  
40  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
85  
85  
45  
45  
-
-
-
30  
30  
30  
-
10 tOHZ  
11 tBHZ  
12 tOH  
10  
15  
15  
WRITE CYCLE  
13 tWC  
14 tCW  
15 tAW  
16 tBW  
17 tAS  
18 tWP  
19 tWR  
20 tWHZ  
21 tDW  
22 tDH  
23 tOW  
Write Cycle Time  
85  
70  
70  
70  
0
55  
0
0
-
-
-
-
-
-
-
30  
-
-
100  
80  
80  
80  
0
75  
0
0
-
-
-
-
-
-
-
35  
-
-
120  
100  
100  
100  
0
85  
0
0
-
-
-
-
-
-
-
40  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
/LB, /UB Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
35  
0
5
45  
0
10  
50  
0
10  
-
-
-
Rev.04 /Feb.99  
6
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
Vcc = 2.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-10  
Max. Min.  
-12  
Max. Min  
-15  
Max.  
#
Symbol  
Parameter  
Unit  
Min.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tBA  
tCLZ  
tOLZ  
tBLZ  
tCHZ  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
/LB, /UB Access Time  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
/LB, /UB Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
/LB, /UB Disable to Output in High Z  
Output Hold from Address Change  
100  
-
-
-
-
20  
5
10  
0
0
0
-
100  
100  
50  
50  
-
-
-
30  
30  
30  
-
120  
-
-
-
-
20  
10  
10  
0
0
0
-
120  
120  
60  
60  
-
-
-
40  
40  
40  
-
150  
-
-
-
-
20  
10  
10  
0
0
0
-
150  
150  
75  
75  
-
-
-
50  
50  
50  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10 tOHZ  
11 tBHZ  
12 tOH  
15  
15  
15  
WRITE CYCLE  
13 tWC  
14 tCW  
15 tAW  
16 tBW  
17 tAS  
18 tWP  
19 tWR  
20 tWHZ  
21 tDW  
22 tDH  
23 tOW  
Write Cycle Time  
100  
80  
80  
80  
0
75  
0
0
-
-
-
-
-
-
-
35  
-
-
120  
100  
100  
100  
0
85  
0
0
-
-
-
-
-
-
-
40  
-
-
150  
120  
120  
120  
0
100  
0
0
-
-
-
-
-
-
-
50  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
/LB, /UB Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
45  
0
10  
50  
0
10  
60  
0
10  
-
-
-
Rev.04 /Feb.99  
7
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
Vcc = 1.8V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified  
-12  
Max. Min.  
-15  
Max. Min  
-20  
Max.  
#
Symbol  
Parameter  
Unit  
Min.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tBA  
tCLZ  
tOLZ  
tBLZ  
tCHZ  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
/LB, /UB Access Time  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
/LB, /UB Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Out Disable to Output in High Z  
/LB, /UB Disable to Output in High Z  
Output Hold from Address Change  
120  
-
-
-
-
20  
10  
10  
0
0
0
-
120  
120  
60  
60  
-
-
-
40  
40  
40  
-
150  
-
-
-
-
20  
10  
10  
0
0
0
-
150  
150  
75  
75  
-
-
-
50  
50  
50  
-
200  
-
-
-
-
30  
15  
15  
0
0
0
-
200  
200  
100  
100  
-
-
-
60  
60  
60  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10 tOHZ  
11 tBHZ  
12 tOH  
15  
15  
30  
WRITE CYCLE  
13 tWC  
14 tCW  
15 tAW  
16 tBW  
17 tAS  
18 tWP  
19 tWR  
20 tWHZ  
21 tDW  
22 tDH  
23 tOW  
Write Cycle Time  
120  
100  
100  
100  
0
85  
0
0
-
-
-
-
-
-
-
60  
-
-
150  
120  
120  
120  
0
100  
0
0
-
-
-
-
-
-
-
70  
-
-
200  
170  
170  
170  
0
135  
0
0
-
-
-
-
-
-
-
80  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
/LB, /UB Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
50  
0
10  
60  
0
15  
80  
0
15  
-
-
-
AC TEST CONDITIONS  
TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.), unless otherwise specified  
PARAMETER Value  
0.4V to 2.2V  
Input Pulse Level  
HY62UF16200-(I)  
HY62QF16200-(I)  
HY62EF16200-(I)  
HY62SF16200-(I)  
0.4V to 2.2V  
0.4V to 1.8V  
0.4V to 1.6V  
Input Rise and Fall Time  
Input and Output  
Timing Reference  
5ns  
1.5V  
1.1V  
0.9V  
HY62UF16200-(I)  
HY62QF16200-(I)  
HY62EF16200-(I)  
HY62SF16200-(I)  
Level  
0.8V  
Output Load  
CL = 30pF + 1TTL Load  
Rev.04 /Feb.99  
8
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
AC TEST LOADS  
VTM(2)  
3070 Ohm  
DOUT  
CL(1)  
3150 Ohm  
Note  
1. Including jig and scope capacitance  
2. VTM = 2.8V for Vcc = 3.0V : HY62UF16200-(I)  
VTM = 2.3V for Vcc = 2.5V : HY62QF16200-(I)  
VTM = 1.8V for Vcc = 2.0V : HY62EF16200-(I)  
VTM = 1.6V for Vcc = 1.8V : HY62SF16200-(I)  
CAPACITANCE  
(Temp = 25°C, f= 1.0MHz)  
Symbol  
CIN  
COUT  
Parameter  
Input Capacitance(Add, /CS, /WE, /OE)  
Output Capacitance(I/O)  
Condition  
VIN = 0V  
VI/O = 0V  
Max.  
8
10  
Unit  
pF  
pF  
Note : These parameters are sampled and not 100% tested  
TIMING DIAGRAM  
READ CYCLE 1(Note 1)  
tRC  
ADDR  
tAA  
OE  
tOE  
tOH  
tOLZ(5)  
CS  
tOHZ(5)  
tCHZ(5)  
tACS  
tBA  
UB,LB  
tBLZ(5)  
tCLZ  
tBHZ(5)  
Data Valid  
High-Z  
Data  
Out  
Rev.04 /Feb.99  
9
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
READ CYCLE 2(Note 1,2,4)  
tRC  
ADDR  
tAA  
tOH  
tOH  
Data  
Previous Data  
Out  
Data Valid  
READ CYCLE 3(Note 1,3,4)  
CS  
tACS  
tCLZ(5)  
tCHZ(5)  
Data  
Out  
Data Valid  
Notes:  
1. /WE is high for the Read Cycle.  
2. Device is continuously selected. /CS = VIL  
3. Address valid is prior to or coincident with /CS transition low  
4. /OE = VIL  
5. Transition is measured + 200mV from steady state voltage.  
This parameter is sampled and not 100% tested.  
WRITE CYCLE 1  
tWC  
ADDR  
tWR(2)  
tCW  
CS  
tAS  
tBW  
UB,LB  
tAW  
tWP(1)  
tAS  
WE  
tDW  
tDH  
Data Valid  
Data In  
tOHZ(3,9)  
Data  
Out  
Rev.04 /Feb.99  
10  
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
WRITE CYCLE 2 (Note 5)  
tWC  
ADDR  
tAW  
tCW  
tWR  
CS  
tAS  
tWP  
WE  
tDW  
tDH  
Data Valid  
tWHZ  
Data In  
tWHZ  
(7)  
(6)  
Data  
Out  
Notes:  
1. A write occurs during the overlap(tWP) of a low /CS and low /WE  
.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.  
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the  
output must not be applied.  
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE  
transition, outputs remain in a high impedance state.  
5. /OE is continuously low(/OE=VIL)  
6. Q(data out) is the same phase with the write data of this write cycle.  
7. Q(data out) is the read data of the next address.  
8. If /CS is low during this period, I/O pins are in the output state.  
Then the data input signals of opposite phase to the outputs must not be applied to them.  
9. Transition is measured +200mV from steady state.  
This parameter is sampled and not 100% tested.  
Rev.04 /Feb.99  
11  
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
DATA RETENTION ELECTRIC CHARACTERISTIC  
TA=0°C to 70°C (Normal)/-40°C to 85°C (E.T.)  
Symbol  
VDR  
ICCDR  
Parameter  
Vcc for Data Retention  
Data Retention Current  
Test Condition  
/CS > Vcc - 0.2V  
Vcc=2.0V, /CS > Vcc - 0.2V,  
Vss < VIN < Vcc  
Min  
1.5  
-
-
0
Typ  
Max  
3.3  
10  
2
Unit  
V
uA  
uA  
ns  
-
-
-
-
LL  
SL  
tCDR  
tR  
Chip Deselect to Data  
Retention Time  
Operating Recovery Time  
See Data Retention Timing Diagram  
-
tRC(2)  
-
-
ns  
Notes:  
1. Typical values are under the condition of TA = 25°C.  
2. tRC is read cycle time.  
DATA RETENTION TIMING DIAGRAM  
DATA RETENTION MODE  
VCC  
2.7/2.2V  
1.8/1.6V  
tCDR  
tR  
VIH  
VDR  
CS>VCC-0.2V  
CS  
VSS  
Note :  
1. 2.7V : HY62UF16200 and HY62UF16200-I  
2.2V : HY62QF16200 and HY62QF16200-I  
1.8V : HY62EF16200 and HY62EF16200-I  
1.6V : HY62SF16200 and HY62SF16200-I  
RELIABILITY SPEC.  
TEST MODE  
HBM  
TEST SPEC.  
> 2000V  
ESD  
MM  
> 250V  
LATCH - UP  
< -100mA  
> 100mA  
Rev.04 /Feb.99  
12  
HY62UF16200/HY62QF16200/HY62EF16200/HY62SF16200 Series  
PACKAGE INFORMATION  
48ball Micro Ball Grid Array Package(M)  
B
A
A1 CORNER  
INDEX AREA  
6
5
4
3
2
1
A
A
B
C
D
C
C1  
E
3.0 X 5.0 MIN  
FLAT AREA  
F
G
H
C1/2  
B1/2  
B1  
BUMP VIEW  
TOP VIEW  
6
E1  
E2  
C
E
SEATING PLANE  
4
A
r
3 D(DIAMETER)  
SIDE VIEW  
Note  
Symbol  
Min.  
-
-
6.65  
-
9.2  
0.3  
0.85  
0.6  
0.2  
-
Typ.  
0.75  
3.75  
6.7  
5.25  
9.25  
0.35  
0.9  
Max.  
-
-
6.8  
-
9.35  
0.4  
0.95  
0.7  
0.3  
0.08  
A
B
B1  
C
C1  
D
E
E1  
E2  
r
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.  
2. ALL DIMENSIONS ARE MILLIMETERS.  
3. DIMENSION “ D” IS MEASURED AT THE MAXIMUM SOLDER  
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.  
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE  
CROWN OF THE SOLDER BALLS.  
0.65  
0.25  
-
5. SOLDER BALL ARRAY MAY BE DEPOPULATED BY OMISSION  
BALLS FROM A FULL MATRIX. NO SHIFTING OF MATRIX  
PATTERN IS ALLOWED.  
6. THIS IS A CONTROLLING DIMENSION.  
Rev.04 /Feb.99  
13  

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