HY62SF16804B-SF10C [HYNIX]
Standard SRAM, 512KX16, 100ns, CMOS, PBGA48, FBGA-48;
| 型号： | HY62SF16804B-SF10C |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 512KX16, 100ns, CMOS, PBGA48, FBGA-48 静态存储器 |
| 文件： | 总10页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY62SF16804B Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM
Revision History
Revision No History
Draft Date
May.29.2001 Preliminary
Oct.22.2002 Final
Remark
00
01
Initial Release
DC Electrical Characteristics
- ICC changed 4mA -> 3mA
- ICC1 changed 25mA at 70ns -> 15mA at 70ns
- ICC1 changed 3mA at 1us -> 2mA at 1us
- ISB (TTL) changed 50uA -> 300uA
AC Test Loads
- (R1//R2) 4091Ohm // 3273Ohm -> 3070Ohm // 3150Ohm
AC Test Conditions
- Output Load changed 5pF -> 30pF
- Input Pulse Level 0.4V to 1.6V -> 0.2V to Vcc-0.2
Data Retention Electric Characteristic
- ICCDR LL-Part changed 20uA -> 10uA
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.01 /Oct.2002
Hynix Semiconductor
HY62SF16804B
DESCRIPTION
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL/SL-part)
- 1.2V(min) data retention
• Standard pin configuration
- 48-fBGA
The HY62SF16804B is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
512K words by 16bits. The HY62SF16804B uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
FEATURES
Product
No.
Voltage
(V)
Speed
(ns)
Operation
Standby Current(uA) Temperature
Current/Icc(mA)
LL
SL
(°C)
0~70
HY62SF16804B-C
HY62SF16804B-I
1.65~2.3 70/85/100
1.65~2.3 70/85/100
3
3
15
15
8
8
-40~85
Note 1. C : Commercial, I : Industrial
2. Current value is max.
PIN CONNECTION ( Top View )
BLOCK DIAGRAM
1
2
3
4
5
6
ROW
A0
I/O1
/LB /OE A0 A1 A2 NC
IO9 /UB A3 A4 /CS IO1
IO10 IO11 A5 A6 IO2 IO3
Vss IO12 A17 A7 IO4 Vcc
Vcc IO13 Vss A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
IO16 NC A12 A13 /WE IO8
A18 A8 A9 A10 A11 NC
B
C
D
E
F
I/O8
I/O9
I/O16
MEMORY ARRAY
256K x 16
A18
G
H
/CS
/OE
/LB
/UB
/WE
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
Data Inputs / Outputs
Address Inputs
/CS
/WE
/OE
/LB
Chip Select
I/O1~I/O16
A0~A18
Vcc
Write Enable
Output Enable
Power(1.65V~2.3V)
Ground
Lower Byte Control(I/O1~I/O8)
Vss
/UB
Upper Byte Control(I/O9~I/O16) NC
No Connection
Rev.01/Oct. 2002
2
HY62SF16804B
ORDERING INFORMATION
Part No.
Speed
Power
LL-part
SL-part
LL-part
SL-part
Package
fBGA
Temp.
HY62SF16804B-DFC
HY62SF16804B-SFC
HY62SF16804B-DFI
HY62SF16804B-SFI
70/85/100
70/85/100
70/85/100
70/85/100
C
C
I
fBGA
fBGA
fBGA
I
Note 1. C : Commercial, I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
Parameter
Rating
Unit
V
Remark
Input/Output Voltage
-0.3 to Vcc+0.3
-0.3 to 2.6V
0 to 70
Power Supply
V
HY62SF16804B-C
HY62SF16804B-I
°C
°C
°C
W
TA
Operating Temperature
-40 to 85
-55 to 150
1.0
TSTG
PD
Storage Temperature
Power Dissipation
°C •
TSOLDER
Ball Soldering Temperature & Time
260 • 10
sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
I/O
/CS
/WE
/OE
/LB /UB
Mode
Power
I/O1~I/O8 I/O9~I/O16
H
X
L
L
L
X
X
H
H
H
X
X
H
H
L
X
H
L
X
H
X
L
Deselected
Deselected
Output Disabled
Output Disabled
Read
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
Standby
Standby
Active
X
L
Active
H
L
Active
H
L
L
L
L
X
L
H
L
Write
Active
H
L
High-Z
DIN
L
DIN
Note:
1. H=VIH, L=VIL, X=don't care(VIH or VIL)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.01/Oct. 2002
2
HY62SF16804B
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Min.
1.65
0
Typ.
1.8
0
Max.
2.3
Unit
V
Vcc
Supply Voltage
Ground
Vss
VIH
VIL
0
V
Input High Voltage
Input Low Voltage
1.4
Vcc+0.3
0.4
V
-0.3(1)
-
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 1.65V~2.3V, TA = 0°C to 70°C / -40°C to 85°C
Sym
ILI
Parameter
Test Condition
Min.
-1
Typ. Max.
Unit
uA
Input Leakage Current
Vss < VIN < Vcc
-
1
Vss < VOUT < Vcc, /CS = VIH or
/OE = VIH or /WE = VIL,
/UB = /LB = VIH
ILO
Icc
Output Leakage Current
-1
-
-
1
uA
Operating Power Supply
Current
/CS = VIL, VIN = VIH or VIL, II/O = 0mA
3
mA
mA
Cycle Time=Min,100% duty,
-
-
15
II/O = 0mA, /CS = VIL,VIN = VIH or VIL
Average Operating
Current
Icc1
Cycle time = 1us, 100% duty,
-
2
mA
uA
II/O = 0mA, /CS < 0.2V, VIN<0.2V
/CS = VIH or /UB=/LB= VIH,
TTL Standby Current
(TTL Input)
ISB
-
-
-
-
300
8
VIN = VIH or VIL
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VIN < Vss+0.2V
IOL = 0.1mA
SL
LL
Standby Current
(CMOS Input)
ISB1
uA
1
15
VOL
VOH
Output Low Voltage
Output High Voltage
-
-
-
0.2
-
V
V
IOH = -0.1mA
1.4
Note : 1. Typical values are at Vcc = 1.8V, TA = 25°C
2. Typical values are sampled and not 100% tested
CAPACITANCE
(Temp = 25°C, f = 1.0MHz)
Symbol
Parameter
Conditio
n
Max.
Unit
CIN
COUT
Input Capacitance(Add, /CS, /WE, /UB, /LB, /OE)
Output Capacitance(I/O)
VIN = 0V
VI/O = 0V
8
pF
pF
10
Note : These parameters are sampled and not 100% tested
Rev.01/Oct. 2002
3
HY62SF16804B
-10
AC CHARATERISTICS
Vcc = 1.65V~2.3V, TA = 0°C to 70°C / -40°C to 85°C
-70
Max. Min.
-85
Max. Min
#
Symbol
Parameter
Unit
Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
Read Cycle Time
70
-
-
85
-
-
100
-
-
100
100
45
100
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
70
70
35
70
-
85
85
40
85
-
tACS
tOE
Chip Select Access Time
-
-
-
Output Enable to Output Valid
/LB, /UB Access Time
-
-
-
tBA
-
-
-
tCLZ
tOLZ
tBLZ
tCHZ
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB, /UB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
10
5
10
5
10
5
-
-
-
10
0
-
10
0
-
10
0
-
20
20
20
-
30
30
30
-
30
30
30
-
10 tOHZ
11 tBHZ
12 tOH
0
0
0
0
0
0
10
10
15
WRITE CYCLE
13 tWC
14 tCW
15 tAW
16 tBW
17 tAS
18 tWP
19 tWR
20 tWHZ
21 tDW
22 tDH
23 tOW
Write Cycle Time
70
60
60
60
0
-
-
85
70
70
70
0
-
-
100
80
80
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
-
-
-
-
-
-
-
-
-
Write Pulse Width
50
0
-
60
0
-
70
0
-
Write Recovery Time
-
-
-
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
20
-
0
25
-
0
25
-
30
0
35
0
45
0
-
-
-
5
-
5
-
10
-
AC TEST CONDITIONS
TA = 0°C to 70°C / -40°C to 85°C, unless otherwise specified
PARAMETER
Value
Input Pulse Level
0.2V to Vcc-0.2V
5ns
Input Rise and Fall Time
Input and Output Timing Reference Level
0.9V
tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
CL = 30pF + 1TTL Load
CL = 30pF + 1TTL Load
Output Load
Other
AC TEST LOADS
VTM
= 1.8V
3070 Ohm
DOUT
CL(1)
3150 Ohm
Note
1. Including jig and scope capacitance
Rev.01/Oct. 2002
4
HY62SF16804B
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
/CS
tAA
tACS
tOH
tCHZ(3)
tBA
/UB ,/ LB
/OE
tBHZ(3)
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
tOHZ(3)
Data
High-Z
Out
Data Valid
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Previous Data
Out
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tACS
tCLZ(3)
tCHZ(3)
Data
Out
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS and low /UB and /or /LB
2. /OE = VIL
3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referenced to output voltage levels.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.01/Oct. 2002
5
HY62SF16804B
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
tCW
ADDR
tWR(2)
/CS
tAW
tBW
/UB,/LB
tWP
/WE
tAS
tDW
Data Valid
tDH
Data In
High-Z
tWHZ(3,7)
(5)
(6)
tOW
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC
ADDR
tCW
tAS
tWR(2)
/CS
tAW
tBW
/UB,/LB
/WE
tWP
tDW
Data Valid
tDH
High-Z
Data In
High-Z
Data
Out
Rev.01/Oct. 2002
6
HY62SF16804B
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and low /UB and /or /LB
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0°C to 70°C / -40°C to 85°C
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VDR
Vcc for Data Retention
1.2
-
2.3
V
VIN < Vss+0.2V
Vcc=1.5V, /CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
-
-
LL
SL
1
-
12
8
uA
uA
ICCDR
Data Retention Current
VIN < Vss+0.2V
Chip Deselect to Data
Retention Time
tCDR
tR
0
-
-
-
-
ns
ns
See Data Retention Timing Diagram
Operating Recovery Time
tRC(2)
Notes:
1. Typical values are under the condition of TA = 25°C .
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
1.65V
tCDR
tR
VIH
VDR
/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V
/CS or
/UB & /LB
Vss
Rev.01/Oct. 2002
7
HY62SF16804B
PACKAGE INFORMATION
48ball Fine Pitch Ball Grid Array Package (F)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
A
B
C
D
C
C1
E
F
G
H
C1/2
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
4
A
r
3
D(DIAMETER)
Note
Symbol
Min.
-
Typ.
0.75
3.75
6.0
Max.
-
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
A
B
-
-
B1
C
5.9
-
6.1
-
5.25
8.5
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
C1
D
8.4
0.3
0.9
-
8.6
0.4
1.10
-
0.35
1.0
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
E
E1
E2
r
0.76
0.25
-
5. THIS IS A CONTROLLING DIMENSION.
0.20
-
0.30
0.08
Rev.01/Oct. 2002
8
HY62SF16804B
MARKING INSTRUCTION
Package
Marking Example
H
Y
S
F
6
8
y
0
4
B
c
x
s
x
s
x
t
w
K
w
O
p
fBGA
x
x
R
Index
• HYSF6804B
• c
: Part Name
: Power Consumption
- D
- S
: Low Low Power
: Super Low Power
ss
: Speed
- 70
•
: 70ns
: 85ns
: 100ns
- 85
- 10
•
t
: Temperature
- C
- I
: Commercial (
°C)
0 ~ 70
: Industrial ( -40 ~ 85 C)
°
y
: Year (ex : 0 = year 2000, 1= year 2001)
: Work Week ( ex : 12 = work week 12 )
: Process Code
•
• ww
p
•
xxxxx
: Lot No.
•
•
KOR
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.01/Oct. 2002
9
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