HY62UF16404E-SF55I [HYNIX]
Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, FBGA-48;
| 型号： | HY62UF16404E-SF55I |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY62UF16404E Series
256Kx16bit full CMOS SRAM
Document Title
256K x16 bit 2.7 ~ 3.3V Super Low Power FCMOS Slow SRAM
Revision History
Revision No History
Draft Date
Remark
00
01
02
Initial Draft
Dec.20.2001
Mar.05.2002
Feb.18.2003
Preliminary
Preliminary
Final
Package Height Changed 1.0mm -> 0.9mm
Add Package Size Option (6.0mmx8.0mm)
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 / Feb. 03
Semiconductor
Hynix
HY62UF16404E Series
DESCRIPTION
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup
The HY62UF16404E is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
256K words by 16bits. The HY62UF16404E uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
-. 1.2V(min) data retention
• Standard pin configuration
-. 48-ball FBGA
FEATURES
Standby
Temperature
Voltage
Operation
Product No.
Speed (ns)
55/70
Current(uA)
(V)
Current/Icc(mA)
(°C)
SL
6
LL
10
HY62UF16404E-I 2.7~3.3
Note 1. I : Industrial
3
-40~85
2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
1
2
3
4
5
6
ROW
A0
I/O1
I/O8
I/O9
I/O16
/LB /OE A0
A1
A2
NC
A
/CS
IO9
A3
A5
A4
A6
IO1
/UB
B
C
D
E
F
IO10
Vss
IO2 IO3
IO4 Vcc
IO11
IO12
IO13
IO14
A17 A7
MEMORY ARRAY
256K x 16
Vcc
NC A16 IO5 Vss
A14 A15 IO6 IO7
IO15
A17
/CS
IO16 NC A12 A13 /WE IO8
G
H
NC
A9
A10 A11 NC
A8
/OE
/LB
/UB
FBGA
/WE
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
I/O1~I/O16
A0~A17
Vcc
Pin Function
Data Inputs/Outputs
Address Inputs
Power (2.7~3.3V)
Ground
/CS
/WE
/OE
/LB
Chip Select
Write Enable
Output Enable
Lower Byte Control (I/O1~I/O8)
Vss
/UB
Upper Byte Control (I/O9~I/O16) NC
No Connection
Rev.02 / Feb. 03
2
HY62UF16404E Series
ORDERING INFORMATION
Part No.
Speed
Power
SL-part
LL-part
Temp.
Package
HY62UF16404E-SF(I)
HY62UF16404E-DF(I)
55/70
55/70
I
I
FBGA
FBGA
Note 1. I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
Parameter
Rating
Unit
V
Remark
Input/Output Voltage
-0.3 to VCC+0.3V
-0.3 to 3.6
-40 to 85
-55 to 150
1.0
Power Supply
V
TA
Operating Temperature
Storage Temperature
Power Dissipation
HY62UF16404E-I
°C
°C
W
TSTG
PD
TSOLDER
Ball Soldering Temperature & Time
260 • 10
°C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
I/O Pin
/CS
/WE
/OE
/LB /UB
Mode
Power
Standby
Active
I/O1~I/O8
I/O9~I/O16
H
X
X
X
X
X
X
H
L
X
H
X
L
Deselected
High-Z
High-Z
L
H
H
Output Disabled
High-Z
High-Z
X
L
H
L
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
DOUT
DOUT
High-Z
DIN
L
H
L
Read
Write
Active
Active
H
L
L
L
H
L
L
L
X
H
L
L
DIN
Note:
1. H=VIH, L=VIL, X=don't care (VIL or VIH)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
Rev.02 / Feb. 03
2
HY62UF16404E Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
Typ
Max.
3.3
Unit
V
Vcc
3.0
Vss
VIH
VIL
0
-
-
0
V
2.2
Vcc+0.3
0.6
V
V
1.
-0.3
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C
Sym
ILI
Parameter
Test Condition
Vss < VIN < Vcc
Min Typ1.
Max
1
Unit
uA
Input Leakage Current
-1
-
Vss < VOUT < Vcc, /CS = VIH or
/OE = VIH or /WE = VIL or
/UB = VIH , /LB = VIH
/CS = VIL,
ILO
Icc
Output Leakage Current
-1
-
1
uA
Operating Power Supply Current
3
mA
mA
mA
VIN = VIH or VIL, II/O = 0mA
/CS = VIL,
55ns
20
15
VIN = VIH or VIL,
Cycle Time = Min,
100% Duty, II/O = 0mA
/CS < 0.2V,
70ns
ICC1
Average Operating Current
VIN < 0.2V or VIN > Vcc-0.2V,
Cycle Time = 1us,
100% Duty, II/O = 0mA
/CS = VIH or /UB, /LB = VIH
VIN = VIH or VIL
/CS > Vcc - 0.2V or
/UB, /LB > Vcc - 0.2V
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
IOL = 2.1mA
IOH = -1.0mA
2
mA
ISB
Standby Current (TTL Input)
Standby Current (CMOS Input)
300
6
uA
uA
uA
SL
LL
0.2
0.2
ISB1
10
VOL
VOH
Output Low
Output High
-
-
-
0.4
-
V
V
2.4
Note
1. Typical values are at Vcc = 3.0V TA = 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
Input Capacitance(Add, /CS,/LB,/UB, /WE, /OE)
Output Capacitance(I/O)
Condition
VIN = 0V
VI/O = 0V
Max.
Unit
CIN
COUT
8
pF
pF
10
Note : These parameters are sampled and not 100% tested
Rev.02 / Feb. 03
3
HY62UF16404E Series
AC CHARACTERISTICS
TA = -40°C to 85°C, unless otherwise specified
55ns
70ns
#
Symbol
Parameter
Unit
Min.
Max. Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
55
55
30
55
-
70
70
35
70
-
tACS
tOE
Chip Select Access Time
-
-
Output Enable to Output Valid
/LB, /UB Access Time
-
-
-
tBA
-
tCLZ
tOLZ
tBLZ
tCHZ
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB, /UB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
10
5
10
5
-
-
20
20
20
-
-
-
25
25
25
-
10
0
10
0
10 tOHZ
11 tBHZ
12 tOH
0
0
0
0
10
10
WRITE CYCLE
13 tWC
14 tCW
15 tAW
16 tBW
17 tAS
18 tWP
19 tWR
20 tWHZ
21 tDW
22 tDH
23 tOW
Write Cycle Time
55
50
50
50
0
-
-
70
60
60
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
-
-
-
-
-
-
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
45
0
-
50
0
-
-
-
0
20
-
0
20
-
25
0
30
0
-
-
-
-
5
5
AC TEST CONDITIONS
TA = -40°C to 85°C, unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
5ns
Input Rise and Fall Time
Input and Output Timing Reference Level
1.5V
Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW
Others
CL = 30pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=2.8V
1029 Ohm
DOUT
CL(1)
1728 Ohm
Note 1. Including jig and scope capacitance:
Rev.02 / Feb. 03
4
HY62UF16404E Series
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
tRC
ADDR
/CS
tAA
tACS
tOH
tCHZ(3)
tBA
/UB ,/ LB
/OE
tBHZ(3)
tOE
tOLZ(3)
tBLZ(3)
tOHZ(3)
tCLZ(3)
Data
High-Z
Out
Data Valid
READ CYCLE 2 (Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Previous Data
Out
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tACS
tCLZ(3)
tCHZ(3)
Data
Out
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS and /UB and/or /LB .
2. /OE = VIL
3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.02 / Feb. 03
5
HY62UF16404E Series
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
tCW
ADDR
tWR(2)
/CS
tAW
tBW
/UB,/LB
tWP
/WE
tAS
tDW
Data Valid
tDH
Data In
High-Z
tWHZ(3,7)
(5)
(6)
tOW
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC
ADDR
tAS
tWR(2)
tCW
/CS
tAW
tBW
/UB,/LB
/WE
tWP
tDW
Data Valid
tDH
High-Z
Data In
High-Z
Data
Out
Rev.02 / Feb. 03
6
HY62UF16404E Series
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS and a low /UB and/or /LB .
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
Typ1. Max
Unit
/CS > Vcc - 0.2V or
/UB, /LB > Vcc - 0.2V,
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
Vcc=1.5V,
VDR
Vcc for Data Retention
1.2
-
3.3
V
SL
LL
-
0.1
0.1
3
6
uA
uA
/CS > Vcc - 0.2V or
/UB, /LB > Vcc - 0.2V
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
Iccdr
Data Retention Current
Chip Deselect to Data
Retention Time
Operating Recovery Time
tCDR
tR
0
-
-
-
-
ns
ns
See Data Retention Timing Diagram
tRC
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical value are sampled and not 100% tested
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
/CS >VCC-0.2V
VCC
2.7V
tCDR
tR
VIH
VDR
/CS
VSS
Rev.02 / Feb. 03
7
HY62UF16404E Series
PACKAGE INFORMATION (6.0mm X 7.0mm)
48ball Fine Pitch Ball Grid Array Package (F)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
B
C
D
C
C1
E
F
G
H
C1/2
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
4
3
D(DIAMETER)
Note
Symbol
Min.
Typ.
0.75
3.75
6.0
Max.
-
A
B
-
-
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
-
B1
C
5.9
-
6.1
-
5.25
7.0
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
C1
D
6.9
0.40
0.8
-
7.1
0.50
1.0
-
0.45
0.9
0.55
0.35
-
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
E
E1
E2
r
0.30
-
0.40
0.08
5. THIS IS A CONTROLLING DIMENSION.
Rev.02 / Feb. 03
8
HY62UF16404E Series
PACKAGE INFORMATION (6.0mm X 8.0mm)
48ball Fine Pitch Ball Grid Array Package(F)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
B1/2
6
5
4
3
2
1
A
B
C
D
C
C1
E
F
G
H
C1/2
C1/2
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
4
A
r
3
D(DIAMETER)
Symbol
Min.
-
Typ.
0.75
3.75
6.00
5.25
8.00
0.35
1.0
Max.
A
B
-
Note
-
-
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
B1
C
5.90
-
6.10
-
2. ALL DIMENSIONS ARE MILLIMETERS.
C1
D
7.90
0.3
0.9
0.75
0.17
-
8.10
0.4
1.10
0.85
-
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
E
E1
E2
r
0.80
-
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
-
0.12
5. THIS IS A CONTROLLING DIMENSION.
Rev.02 / Feb. 03
9
HY62UF16404E Series
MARKING INFORMATION
Package
Marking Example
H
Y
U
F
6
4
y
0
4
E
c
x
s
x
s
x
t
w
K
w
O
p
FBGA
x
x
R
Index
• HYUF6404E
• c
: Part Name
: Power Consumption
- D
- S
: Low Low Power
: Super Low Power
• ss
• t
: Speed
- 50
: 55ns
: 70ns
- 70
: Temperature
- I
: Industrial ( -40 ~ 85 °C )
• y
: Year (ex : 2 = year 2002, 3= year 2003)
: Work Week ( ex : 12 = work week 12 )
• ww
• p
: Process Code
- A (6.0mm X 7.0mm)
- B (6.0mm X 8.0mm)
• xxxxx
• KOR
: Lot No.
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.02 / Feb. 03
10
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