HY63V8100ALJ-12 [HYNIX]
Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, SOJ-32;
| 型号： | HY63V8100ALJ-12 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, SOJ-32 静态存储器 光电二极管 |
| 文件： | 总8页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY63V8100A Series
128Kx8bit CMOS FAST SRAM
PRELIMINARY
DESCRIPTION
FEATURES
The HY63V8100A is a 1,048,576-bit high-speed,
SRAM organized as 131,072 words by 8-bits. The
HY63V8100A uses eight common input and output
lines and has an output enable pin which operates
faster than. address access time at read cycle. The
device is fabricated using Hyundai's advanced
CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in
high-density high-speed system applications
·
·
·
·
Single 3.3V ± 0.3V Power Supply
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Low data Retention Voltage:
- 2.0V(min) – L-ver. Only
Center Power/Ground Pin Configuration
·
·
Standard pin configuration
- 32pin 400mil SOJ/TSOP-ll
Product
No.
Supply
Voltage(V)
Speed
(ns)
Operation
Current(mA)
Standby Current(mA)
L
HY63V8100A
HY63V8100A
HY63V8100A
3.3
3.3
3.3
8
10
12
200
190
180
5
5
5
0.5
0.5
0.5
PIN CONNECTION
BLOCK DIAGRAM
ROW
DECODER
A0
I/O1
A0
1
A16
A15
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A1
2
A2
A3
3
4
A14
A13
/OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
/CS
I/O1
5
6
I/O2
Vcc
Vss
7
MEMORY ARRAY
512x256x8
SOJ/
TSOP2
8
9
I/O3
I/O4
/WE
A4
10
11
12
13
14
15
16
I/O8
A5
A6
A7
A8
A16
/CS
/OE
SOJ/TSOP2
/WE
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
A0~A16
Vcc
Pin Function
Address Input
Power(+3.3V)
Ground
/CS
/WE
/OE
Chip Select
Write Enable
Output Enable
Vss
I/O1~I/O8 Data Inputs/Outputs
N.C
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 / Jan.99
Hyundai Semiconductor
HY63V8100A Series
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VIN, VOUT
Vcc
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Commercial
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
Rating
-0.5 to 4.6
-0.5 to 5.5
0 to 70
-40 to 85
-65 to 150
1.0
Unit
V
V
°C
°C
°C
W
TA
TSTG
PD
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA=0°C to 70°C)
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3(1)
Type
3.3
0
-
-
Max.
3.6
0
Unit
V
V
V
V
Vcc+0.3(2)
0.8
Note
1. VIL (min)= -2.0V a.c(pulse width less than 8ns) for I < 20mA
2. VIH(max) = Vcc + 2.0V a.c(pulse width less than 8ns) for I < 20mA
DC ELECTRICAL CHARACTERISTICS
(Vcc = 3.3V±0.3V, TA = 0°C to 70°C, unless otherwise specified.)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Test Conditions
VSS < VIN < VCC
VSS < VOUT < VCC,
/CS = VIH or /OE = VIH or /WE = VIL
Min Typ Max
Unit
uA
uA
-2
-2
-
-
2
2
ILO
/CS = VIL, VIN = VIH,
II/O = 0mA
Min. Duty Cycle = 100%
8ns
10ns
12ns
-
-
-
-
-
-
-
-
200
190
180
60
mA
mA
mA
mA
ICC
Operating Current
TTL Standby Current
(TTL Inputs)
/CS = VIH, VIN=VIH or VIL Min. Cycle
ISB
CMOS Standby Current
(CMOS Inputs)
Output Low Voltage
Output High Voltage
-
-
-
-
5
0.5
0.4
-
mA
mA
V
ISB1
/CS > VCC-0.2V, VIN >
VCC-0.2V or VIN < 0.2V
IOL = 8.0mA
L
VOL
VOH
-
-
IOH = -4.0mA
2.4
V
Note : Typical values are at Vcc = 3.3V, TA = 25°C
Rev.02 / Jan.99
2
HY63V8100A Series
AC CHARACTERISTICS
(Vcc = 3.3V ± 0.3V, TA = 0°C to 70°C, unless otherwise specified.)
8ns
10ns
12ns
Unit
#
Symbol
Parameter
Min Max Min Max Min Max
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselecting to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
8
-
-
-
8
8
4
-
10
-
-
-
10
10
5
-
-
5
5
-
12
-
-
-
12
12
6
-
-
6
6
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
3
0
0
0
3
3
0
0
0
3
3
0
0
0
3
-
5
5
-
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWP1
16 tWR
17 tWHZ
18 tDW
19 tDH
Write Cycle Time
8
6
6
0
6
8
0
0
4
0
3
-
-
-
-
-
-
-
4
-
-
-
10
7
7
0
7
10
0
0
5
0
-
-
-
-
-
-
-
5
-
-
-
12
8
8
0
8
12
0
0
6
0
-
-
-
-
-
-
-
6
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width(/OE High)
Write Pulse Width(/OE Low)
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20 tOW
3
3
NOTE : Above parameters are also guaranteed at industrial temperature range.
Rev.02 / Jan.99
3
HY63V8100A Series
AC TEST CONDITIONS
(Vcc = 3.3V ± 0.3V, TA = 0°C to 70°C, unless otherwise specified.)
Parameter
Input Pulse Level
Input Rise and Fall Time
Value
0V to 3V
3ns
Input and Output Timing Reference Level
Output Load
1.5V
See below
AC TEST CONDITIONS
Output Load (A)
Output Load (B)
(for tCHZ, tCLZ, tOHZ, tOLZ, tWHZ & tOW)
+
3.3V
=
Z 50
W
o
Dout
RL=50W
Dout
5pF *
353
W
VL = 1.5V
Note : *Including jig and scope capacitance
CAPACITANCE
Temp = 25°C, f= 1.0MHz
Symbol
CIN
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Condition
VIN = 0V
VI/O = 0V
Max.
7
8
Unit
pF
pF
Note : This parameter is sampled and not 100% tested
Rev.02 / Jan.99
4
HY63V8100A Series
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
OE
tAA
tOE
tOH
tOLZ
CS
tACS
tCLZ
tOHZ
tCHZ
High-Z
Data
Out
Data Valid
Note (Read Cycle)
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for read cycle.
READ CYCLE 2
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
Note (Read Cycle)
1. /WE is high for read cycle.
2. Device is continuously selected /CS=VIL.
3. /OE=VIL.
Rev.02 / Jan.99
5
HY63V8100A Series
WRITE CYCLE 1(/OE Clocked)
tWC
ADDR
OE
tAW
tCW
CS
tAS
tWR
tWP
WE
tDW
tDH
Data Valid
Data In
tOHZ
Data
Out
WRITE CYCLE 2(/OE Low Fixed)
tWC
ADDR
tAW
tCW
tWR
CS
tAS
tWP
WE
tDW
tDH
Data Valid
tOW
Data In
tWHZ
(8)
(7)
Data
Out
Notes(Write Cycle)
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low, and /WE going low : A write ends at the earliest transition among /CS going
high and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as
/CS or /WE going high.
5. If /OE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
inputs of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high
impedance state.
7. DOUT is the same phase of latest written data in the write cycle.
8. DOUT is the read data of the new address.
Rev.02 / Jan.99
6
HY63V8100A Series
Supply Current
FUNCTIONAL DESCRIPTION
I/O Pin
I/O1 - I/O8 I/O9 - I/O16
High-Z
/CS /WE /OE
/LB
/UB
MODE
Not Select
H
L
L
X
H
X
X*
H
X
X
X
H
L
X
X
H
H
L
L
H
L
High-Z
Isb,Isb1
Icc
Output Disable
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
High-Z
Dout
Dout
High-Z
Din
L
L
H
L
L
H
L
L
H
L
Read
Write
Icc
Icc
X
L
Din
* NOTE : X means Don,t Care
DATA RETENTION ELECTRIC CHARATERISTIC
(TA = 0°C to 70°C)
Symbol
VDR
Parameter
Vcc for Data Retention
Test Condition
/CS > Vcc - 0.2V
Min Typ Max
Unit
V
2.0
-
3.6
Vcc = 3.0V, /CS > Vcc - 0.2V
Vin > Vcc - 0.2V or < 2.0V
-
-
0.9
Data Retention
Current
IDR
mA
Vcc = 2.0V, /CS > Vcc - 0.2V
Vin > Vcc - 0.2V or < 2.0V
-
-
0.7
tCDR
tR
Data Retention Set-Up Time
Recovery Time
0
5
-
-
-
-
ns
ms
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
3.0/2.7V
tCDR
tR
2.2V
VDR
CS>Vcc-0.2V
CS
VSS
Rev.02 / Jan.99
7
HY63V8100A Series
PACKAGE INFORMATION
32pin 400mil Small Outline J-Form Package (J)
UNIT : INCH(mm)
0.030(0.762)
0.040(1.016)
0.026(0.66)
0.032(0.81)
0.395(10.033)
0.405(10.287)
0.436(11.0744)
0.444(11.2776)
0.368(9.3472)
0.380(9.65)
0.821(20.8534)
0.829(21.0566)
0.138(3.505)
0.148(3.759)
0.050(1.27)
BSC.
0.016(0.41)
0.020(0.508)
32pin 400mil Thin Small Outline Package (T2)
MAX.
10.2620(0.404)
10.0580(0.396)
UNIT : INCH(mm)
MIN.
11.9380(0.470)
11.7350(0.462)
21.0570(0.829)
20.8790(0.822)
GAGE PLANE
BASE PLANE
0-5
0.5970(0.0235)
0.4060(0.0160)
1.2700 BSC
(0.050)
0.4500(0.017)
0.3050(0.012)
SEATING PLANE
0.1500(0.0059)
0.0500(0.0020)
0.2100(0.0083)
0.1200(0.0047)
1.1940(0.047)
0.9910(0.039)
Rev.02 / Jan.99
8
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