HY63V8400AJ-10 [HYNIX]
Standard SRAM, 512KX8, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44;
| 型号： | HY63V8400AJ-10 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 512KX8, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44 静态存储器 光电二极管 |
| 文件： | 总8页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY63V8400A
512Kx8bit CMOS FAST SRAM
Preliminary
DESCRIPTION
FEATURES
The HY63V8400A is a 4,194,304-bit high-speed
Static Random Access Memory organized as
524,288 words by 8-bits. The HY63V8400A uses
eight common input and output lines and has an
out enable pin which operates faster than address
access time at read cycle. The device is
fabricated using Hyundai’ s advanced CMOS
process and designed for high speed circuit
technology. It is particularly well suited for use in
high-density high-speed system applications.
·
·
·
·
Single 3.3V+0.3V Power Supply
Fully static operation and Tri-state output
TTL compatible input and outputs
Low data Retention Voltage:
-2.0V(min) –L-ver. Only
Center Power/Ground Pin configuration
Standard pin configuration
·
·
- 36pin 400mil SOJ
- 44pin 400mil TSOP-ll
Product
No.
Voltage
(V)
Speed
(ns)
10
12
15
Operation
Current/Icc(mA)
Standby Current(uA)
L
200
190
180
10
10
10
1
1
1
HY63V8400A
3.3
PIN CONNECTION ( Top View )
BLOCK DIAGRAM
ROW
DECODER
A0
A1
A2
A3
A4
CS
NC
A0
N.C
N.C
N.C
A18
A17
A16
A15
/OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A14
A13
A12
A11
A10
N.C
N.C
N.C
N.C
N.C
A0
A1
A2
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
I/O1
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A18
A17
A16
2
3
3
4
4
5
A15
A3
A4
6
5
/OE
7
/
6
/CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
/WE
A5
A6
A7
A8
A9
8
I/O1
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A14
A13
A12
A11
A10
NC
7
MEMORY
9
I/O2
8
10
11
12
13
14
15
16
17
18
19
20
21
22
Vcc
9
512x1024x8
Vss
TSOP
10
11
12
13
14
15
16
17
18
SOJ
I/O3
I/O4
/WE
A5
A6
A7
I/O8
A18
A8
A9
/CS
/OE
/WE
N.C
N.C
SOJ
TSOPll
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
A0~A18
Vcc
Pin Function
Address Input
Power(+3.3V)
Ground
/CS
/WE
/OE
Chip Select
Write Enable
Output Enable
Vss
I/O1~I/O8 Data Input/Output
NC
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.1 / Jun. 2000
Hyundai Semiconductor
HY63V8400A
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
TA
TSTG
PD
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Operating Temperature
Storage Temperature
Power Dissipation
Rating
-0.5 to 4.6
-0.5 to 5.5
0 to 70
-65 to 150
1.0
Unit
V
V
°C
°C
W
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS
/WE
/OE
MODE
I/O Operation
H
L
L
L
X
H
H
L
X
H
L
Standby
Output Disable
Read
High-Z
High-Z
DOUT
X
Write
DIN
Note
1. H=VIH, L=VIL, X=Don’ t Care.
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.3V+0.3V, TA = 0°C to 70°C, unless otherwise specified.
Sym
ILI
ILO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Vss < VIN < Vcc
Vss < VOUT < Vcc,
Min.
-2
-2
Typ. Max.
Unit
uA
uA
-
-
2
2
/CS = VIH or /OE = VIH or /WE = VIL
Icc
Operating Power Supply
Current
/CS = VIL, VIN = VIH,
II/O = 0mA
Min. Duty Cycle = 100%
10ns
12ns
15ns
-
-
-
-
-
-
-
-
200
190
180
60
mA
mA
mA
mA
ISB
TTLStandbyCurrent
(TTL Input)
/CS = VIH, VIN = VIH or VIL,
Min. Cycle
ISB1
CMOS Standby Current
(CMOS Input)
Output Low Voltage
Output High Voltage
/CS > Vcc - 0.2V, VIN >
Vcc-0.2V or VIN < 0.2V, f =0Mhz
IOL = 8.0mA
IOH = -4.0mA
-
-
-
-
-
-
-
10
1
0.4
-
mA
mA
V
L
VOL
VOH
2.4
V
Note : Typical values are at Vcc = 3.3V, TA = 25°C
Rev.1 / Jun. 2000
2
HY63V8400A
RECOMMENDED DC OPERATING CONDITION (TA=0°C to 70°C)
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3(1)
Typ.
3.3
0
-
-
Max.
3.6
0
Unit
V
V
V
V
Vcc+0.3(2)
0.8
Note
1. VIL(min) = -2.0V a.c(pulse width < 8ns) for I < 20mA
2. VIH(max) = Vcc + 2.0V a.c(pulse width < 8ns) for I < 20mA
CAPACITANCE
(Temp = 25°C, f = 1.0MHz)
Symbol
CIN
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Condition
VIN = 0V
VI/O = 0V
Max.
7
8
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
AC CHARACTERISTICS
Vcc = 3.3V+0.3V, TA= 0°C to 70°C, unless otherwise specified
10ns
12ns
15ns
#
Symbol Parameter
Unit
Min.
Max. Min. Max. Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
10
-
-
-
10
10
5
-
-
5
5
-
12
-
-
-
12
12
6
-
-
6
6
-
15
-
-
-
15
15
7
-
-
7
7
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
3
0
0
0
3
3
0
0
0
3
3
0
0
0
3
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWP1
16 tWR
17 tWHZ
18 tDW
19 tDH
Write Cycle Time
10
7
7
0
7
10
0
0
5
0
-
-
12
8
8
0
8
12
0
0
6
0
-
-
15
10
10
0
10
15
0
0
7
0
3
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width(/OE High)
Write Pulse Width(/OE LOW)
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
-
-
-
-
-
-
-
5
-
-
-
-
6
-
-
-
-
7
-
-
-
20 tOW
3
3
Rev.1 / Jun. 2000
3
HY63V8400A
AC TEST CONDITIONS
Vcc = 3.3V+0.3V, TA = 0°C to 70°C, unless otherwise specified
PARAMETER
Input Pulse Level
Value
0V to 3V
3ns
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load
1.5V
See below
AC TEST LOADS
Output Load(A)
Output Load(B)
(for tCHZ, tCLZ, tOHZ, tOLZ, tWHZ & tOW)
+3.3V
Zo=50ohm
319ohm
Dout
Dout
RL=50ohm
5pF *
353ohm
VL = 1.5V
Note : *Including jig and scope capacitance
Rev.1 / Jun. 2000
4
HY63V8400A
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
OE
tAA
tOE
tOH
tOLZ
CS
tACS
tCLZ
tOHZ
tCHZ
High-Z
Data
Out
Data Valid
Note (Read Cycle)
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not reference to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for read cycle.
READ CYCLE 2
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
Notes (Read Cycle)
1. /WE is high for read cycle.
2. Device is continuously selected /CS=VIL
3. /OE=VIL
Rev.1 / Jun. 2000
5
HY63V8400A
WRITE CYCLE 1 (/OE Clocked)
tWC
ADDR
OE
tAW
tCW(2)
CS
tAS(3)
tWR(4)
tWP(1)
WE
tDW
tDH
Data Valid
Data In
tOHZ(5)
High-Z(6)
Data
Out
WRITE CYCLE 2 (/OE Low Fixed)
tWC
ADDR
tAW
tCW(2)
tWR(4)
CS
tAS(3)
tWP(1)
WE
tDW
tDH
Data Valid
tOW
Data In
tWHZ(5)
(8)
(7)
Data
Out
Rev.1 / Jun. 2000
6
HY63V8400A
Notes(Write Cycle)
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low, and /WE going low : A write ends at the earliest transition among /CS going
high and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as
/CS or /WE going high.
5. If /OE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
inputs of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high
impedance state.
7. DOUT is the same phase of latest written data in the write cycle.
8. DOUT is the read data of the new address.
DATA RETENTION ELECTRIC CHARACTERISTIC(L-Version)
TA= 0°C to 70°C
Symbol
VDR
Parameter
Vcc for Data Retention
Test Condition
/CS > Vcc - 0.2V
Min Typ Max
Unit
V
2.0
-
3.6
Vcc = 3.0V, /CS > Vcc - 0.2V
VIN > Vcc-0.2V or VIN < 0.2V
-
-
0.9
Data Retention
Current
IDR
mA
Vcc = 2.0V, /CS > Vcc - 0.2V
VIN > Vcc-0.2V or VIN < 0.2V
-
-
0.7
tCDR
tR
Data Retention Set-Up Time
Recovery Time
0
5
-
-
-
-
ns
ms
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
3.0V
tCDR
tR
2.0V
VDR
CS>VCC-0.2V
CS
VSS
Rev.1 / Jun. 2000
7
HY63V8400A
PACKAGE INFORMATION
36pin 400mil Small Outline J-Form Package(J)
UNIT : INCH(mm)
0.032(0.81)
0.380(9.652)
0.929(23.597)
0.921(23.393)
0.138(3.505)
44pin 400mil Thin Small Outline Package(T2)
#44
#23
Max.
Min.
UNIT : INCH(mm)
0.470(11.938)
0.462(11.735)
#1
#22
0.729(18.517)
0.721(18.313)
0.404(10.262)
0.396(10.058)
0.047(1.194)
0.039(0.991)
0.0083(0.21)
0.0047(0.120)
0.10MAX
0.004MAX
0.0235(0.597)
0.0160(0.406)
0~5
0.016(0.4)
0.012(0.3)
0.0059(0.150)
0.002(0.050)
0.0315(0.800)
BSC
Rev.1 / Jun. 2000
8
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