HY67V161610DTC [HYNIX]
2 Banks x 512K x 16 Bit Synchronous DRAM; 2 ，银行X 512K ×16位同步DRAM
| 型号： | HY67V161610DTC |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| 文件： | 总11页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY57V161610D
2 Banks x 512K x 16 Bit Synchronous DRAM
DE S CRIPT ION
T H E H y u n d a i H Y 5 7 V 1 6 1 6 1 0 D i s a 1 6 , 7 7 7 , 2 1 6 - b i t s C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e m a i n m e m o r y
and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as
2banks of 524, 288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1, 2 or 3), the number of consecutive read or
write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by
design is not restricted by a `2N` rule.)
a new burst read or write command on any cycle. (This pipeline
F EAT URES
Note1)
•
•
•
Single 3.0V to 3.6V power supply
•
•
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
4096 refresh cycles / 64ms
J E D E C s t a n d a r d 4 0 0 m i l 5 0 p i n T S O P - I I w i t h 0 . 8 m m
of pin pitch
P r o g r a m m a b l e B u r s t L e n g t h a n d B u r s t T y p e
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
P r o g r a m m a b l e C A S Latency ; 1, 2, 3 Clocks
•
All inputs and outputs referenced to positive edge of
system clock
•
•
•
D a t a m a s k f u n c t i o n b y U D Q M / L D Q M
Internal two banks operation
OR D E R IN G INF ORMAT IO N
Par t No.
C lock Fr equency
O r gani zat i on
I nt erf ace
Package
H Y 5 7 V 1 6 1 6 1 0 D T C - 5
H Y 5 7 V 1 6 1 6 1 0 D T C - 5 5
H Y 5 7 V 1 6 1 6 1 0 D T C - 6
H Y 5 7 V 1 6 1 6 1 0 D T C - 7
H Y 5 7 V 1 6 1 6 1 0 D T C - 8
H Y 5 7 V 1 6 1 6 1 0 D T C - 1 0
2 0 0 M H z
1 8 3 M H z
1 6 6 M H z
1 4 3 M H z
1 2 5 M H z
1 0 0 M H z
400mil
2 B a n k s x 5 1 2 K b i t s x 1 6
L V T T L
5 0 p i n T S O P I I
Note :
1. V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V
This document is
a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied
Rev. 3. 6/ Apr . 01
HY57V161610D
PIN CONF IGURAT ION
V D D
D Q 0
D Q 1
V S S Q
D Q 2
D Q 3
V D D Q
D Q 4
D Q 5
V S S Q
D Q 6
D Q 7
V D D Q
L D Q M
W E
1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
V S S
D Q 1 5
D Q 1 4
V S S Q
D Q 1 3
D Q 1 2
V D D Q
D Q 1 1
D Q 1 0
V S S Q
D Q 9
D Q 8
V D D Q
N C
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
5 0 p i n T S O P - I I
400mil x 825mil
0. 8mm pin pitch
U D Q M
C L K
C K E
N C
C A S
R A S
C S
A 1 1
A 9
A 1 0
A 8
A 0
A 7
A 1
A 6
A 2
A 5
A 3
A 4
V D D
V S S
P IN DE S CRIPTION
PI N
P I N N A ME
D E S C R I PTI O N
The system clock input. All other inputs are referenced to the SDRAM on the
r i s i n g e d g e o f C L K .
C L K
C K E
C l o c k
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh.
Clock Enable
C S
B A
C h i p S e l e c t
C o m m a n d i n p u t e n a b l e o r m a s k e x c e p t C L K , C K E a n d D Q M
Select either one of banks during both R A S a n d C A S activity.
B a n k A d d r e s s
R o w A d d r e s s : R A 0 ~ R A 1 0 , C o l u m n A d d r e s s : C A 0 ~ C A 7
Auto-precharge flag : A10
A 0 ~ A 1 0
A d d r e s s
R o w A d d r e s s S t r o b e ,
C o l u m n A d d r e s s S t r o b e ,
Write Enable
R A S , C A S and W E define the operation.
Refer function truth table for details
R A S , C A S , W E
L D Q M , U D Q M
Data Input/Output Mask
Data Input/Output
DQM control output buffer in read mode and mask input data in write mode
Multiplexed data input / output pin
D Q 0
~ D Q 1 5
V D D/V S S
V D D Q/V S S Q
N C
P o w e r S u p p l y / G r o u n d
D a t a O u t p u t P o w e r / G r o u n d
N o C o n n e c t i o n
Power supply for internal circuit and input buffer
P o w e r s u p p l y f o r D Q
N o c o n n e c t i o n
Rev. 3. 6/ Apr . 01
2
HY57V161610D
F UNCT IONAL BL OCK DIA GR A M
1 M x 1 6 S y n c h r o n o u s D R A M
Self Refresh Counter
R e f r e s h
R e f r e s h
C o u n t e r
I nt erval T imer
5 1 2 K x 1 6
B a n k 0
Address[0:10]
S e n s e A M P & I / O g a t e s
C o l u m n D e c o d e r
C L K
C K E
D Q 0
D Q 1
A d d r e s s
R e g i s t e r
P r e c h a r g e
R o w A c t i v e
D Q 2
D Q 3
B A ( A 1 1 )
D Q 4
D Q 5
C o l u m n A d d r.
C o l u m n A c t i v e
C S
D Q 6
L a t c h & C o u n t e r
D Q 7
R A S
Overflow
D Q 8
Burst Length
C o u n t e r
D Q 9
C A S
W E
D Q 1 0
D Q 1 1
D Q 1 2
D Q 1 3
D Q 1 4
D Q 1 5
U D Q M
L D Q M
C o l u m n D e c o d e r
S e n s e A M P & I / O g a t e s
5 1 2 K x 1 6
B a n k 1
Mode Register
T e s t M o d e
I/O Control
Rev. 3. 6/ Apr . 01
3
HY57V161610D
ABS OL UT E MAX IMU M R A T IN GS
P a r a m e t e r
S y m b o l
Rating
Unit
A m b i e n t T e m p e r a t u r e
TA
0 ~ 7 0
- 5 5 ~ 1 2 5
-1.0 ~ 4.6
-1.0 ~ 4.6
5 0
°C
Storage Temperature
TS T G
V IN , V O U T
V DD
°C
Voltage on Any Pin relative to V S S
Voltage on V D D relative to V S S
Short Circuit Output Current
Power Dissipation
V
V
IO S
m A
P D
1
W
Soldering Temperature·T i m e
TS O L D E R
2 6 0 ·1 0
°C ·S e c
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OP E RAT IN G C ON D ITION ( T A = 0 °C t o 7 0 °C )
P a r a m e t e r
P o w e r S u p p l y V o l t a g e
Input high voltage
Input low voltage
S y m b o l
V DD , V DDQ
V IH
Min
3.0
T y p .
3.3
3.0
0
M a x
3.6
Unit
V
Note
1, 2, 3
1, 4
2.0
V DD + 0.3
0.8
V
V IL
-0.5
V
1, 5
Note :
1.All voltages are referenced to V S S = 0V.
2.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S latency=2
3.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V
4.V IH (max) is acceptable 4. 6V AC pulse width with £ 10ns of duration.
5.V IL (min) is acceptable -1. 5V AC pulse width with £ 10ns of duration.
AC OP E RAT IN G C ON D ITION ( T A = 0 °C t o 7 0 °C , V DD =3.0V to 3.6V, V S S = 0 V )
P a r a m e t e r
S y m b o l
V IH / V IL
Vtrip
V a l u e
2.4/0.4
1.4
Unit
V
Note
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
V
tR / tF
Voutref
C L
1
n s
V
Output timing measurement reference level
Output load capacitance for access time measurement
1.4
3 0
pF
1
Note :
1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF).
For details, refer to AC/DC output load circuit.
2. V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s
3. V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V ‘
Rev. 3. 6/ Apr . 01
4
HY57V161610D
CAP ACIT ANCE ( T A = 2 5 °C , f = 1 M H z )
P a r a m e t e r
P i n
S y m b o l
CI1
Min
2.5
2.5
M a x
Unit
pF
C L K
4
5
Input capacitance
A 0
~
A 1 0 , B A
CI2
pF
C K E , C S , R A S , C A S, W E , U D Q M , L D Q M
Data input / output capacitance
D Q 0
~
D Q 1 5
C I/O
4
6.5
pF
OUT P UT L OAD CIRCUIT
Vtt= 1 . 4 V
R T= 2 5 0 W
Output
Output
3 0pF
3 0pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACT E RISTICS I ( T A = 0°C t o 7 0 °C )
P a r a m e t e r
P o w e r S u p p l y V o l t a g e
Input leakage current
Output leakage current
Output high voltage
Output low voltage
S y m b o l
M i n .
M a x
3.6
1
Unit
Note
1, 2
3
V DD
IL
3.0
-1
V
u A
u A
V
IO
-1
1
4
V O H
V O L
2.4
-
-
IO H = - 4 m A
IO L = + 4 m A
0.4
V
Note :
1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s .
2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V
3.V IN = 0 to 3. 6V, All other pins are not under test = 0V
4.D O U T is disabled, V O U T = 0 t o 3 . 6 V
Rev. 3. 6/ Apr . 01
5
HY57V161610D
Note1,2
DC CHARACT E RISTICS II ( T A = 0 ° C to 70° C , V DD =3.0V to 3.6V, V S S = 0 V
)
Spe e d
Pa r a me t e r
S y mb o l
Test Condi t i on
Uni t
m A
m A
Not e
-5
- 55
-6
- 7
-8
- 10
Burst Length=1, One bank active
O p e r a t i n g C u r r e n t
ID D 1
t R A S ³ tRAS(min), tRP
³
tRP(min),
130
130
120
110
110
110
2
I O = 0 m A
ID D 2 P
C K E
C K E
£
£
VIL(max), tCK
VIL(max), tCK
=
min.
1
1
P r e c h a r g e S t a n d b y
Current
i n p o w e r d o w n m o d e
ID D 2 P S
=
¥
C K E
min
³ VIH(min), C S ³ V I H ( m i n ) , t C K =
ID D 2 N
Input signals are changed one time
during 2Clks. All other pins ³ V D D - 0 . 2 V
o r 0 . 2 V
2 0
1 5
P r e c h a r g e S t a n d b y
Current
m A
m A
m A
in non power down
m o d e
£
C K E
³ VIH(min), tCK = ¥
ID D 2 N S
Input signals are stable.
ID D 3 P
C K E
C K E
£
£
VIL(max), tCK
VIL(max), tCK
=
=
min
3 0
3 0
Active Standby Current
i n p o w e r d o w n m o d e
ID D 3 P S
¥
C K E
min
³ VIH(min), C S ³ V I H ( m i n ) , t C K =
ID D 3 N
Input signals are changed one time
5 0
3 0
Active Standby Current
in non power down
m o d e
during 2CLKs. All other pins ³ V D D -
0.2V or
£ 0. 2V
C K E
³ VIH(min), tCK = ¥
ID D 3 N S
Input signals are stable
t C K
³
tCK(min),
C L = 3
C L = 2
130
130
130
130
120
110
110
110
110
110
110
-
9 0
-
Burst Mode Operating
Current
t R A S ³ t R A S ( m i n ) ,
I O = 0 m A
I D D 4
m A
3
All banks active
Auto Refresh Current
Self Refresh Current
ID D 5
ID D 6
t R R C
C K E
³
tRRC(min), All banks active
0. 2V
110
110
m A
m A
2
£
Note :
1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s .
2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V
3.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open.
Rev. 3. 6/ Apr . 01
6
HY57V161610D
Note1,2
AC CHARACT E RISTICS ( T A = 0 °C t o 7 0 °C , V DD =3.0V to 3.6V, V S S =0V
)
-5
- 55
- 6
-7
-8
- 10
Pa r a me t e r
Sy mb o l
Uni t
Not e
Mi n
5
Ma x
M in
Ma x
M in
6
Ma x
M in
7
Ma x
M in
Ma x
M in
10
12
3
Ma x
C L = 3
C L = 2
t C K 3
t C K 2
t C H W
tCLW
t A C 3
t A C 2
t O H
5.5
-
-
-
-
8
12
3
-
-
-
-
S y s t e m c l o c k
cycle time
n s
-
10
2
-
10
2.5
2.5
-
3
4
4
Clock high pulse width
Clock low pulse width
1.75
1.75
2
-
-
-
-
n s
n s
2
2
-
-
3
-
3
-
C L = 3
4.5
5
-
5.5
6
6
-
-
6
6
-
-
7
7
-
A c c e s s t i m e
from clock
n s
C L = 2
-
6
-
-
-
-
-
-
-
-
-
-
-
-
3
D a t a - o u t h o l d t i m e
1. 5
1. 5
1
2
1.5
1
2
2.5
1.75
1
2. 5
2
2. 5
2. 5
1
n s
n s
n s
n s
n s
n s
n s
n s
n s
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
C K E s e t u p t i m e
tDS
1.5
1
-
-
-
4
4
4
4
4
4
4
4
tDH
-
1
-
-
t A S
1. 5
1
1.5
1
1.5
1
1.75
1
-
2
-
2. 5
1
-
tAH
-
1
-
-
t C K S
t C K H
tCS
1. 5
1
1.5
1
1.5
1
1.75
1
-
2
-
2. 5
1
-
C K E h o l d t i m e
-
1
-
-
C o m m a n d s e t u p t i m e
C o m m a n d h o l d t i m e
1. 5
1
1.5
1
1.5
1
1.75
1
-
2
-
2. 5
1
-
tCH
-
1
-
-
CLK to data output in low Z-
t i m e
tOLZ
2
2
2
2
2
2
-
2
2
-
2
2
-
2
3
-
n s
n s
CLK to data output in high Z-
t i m e
t O H Z
5
5.5
6
7
8
1 0
Note :
1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s .
2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V
3 . t C K 2 i s 8 . 9 n s o n l y w h e n t A C 2 i s 7 . 9 n s i n H Y 5 7 V 1 6 1 6 1 0 D T C - 6 a n d H Y 5 7 V 1 6 1 6 1 0 D T C - 7 .
4. Assume tR / tF (input rise and fall time ) is 1ns.
Rev. 3. 6/ Apr . 01
7
HY57V161610D
Note1,2
AC CHARACT E RISTICS ( T A = 0 °C t o 7 0 °C , V DD =3.0V to 3.6V, V S S =0V
))
-5
- 55
-6
-7
-8
- 10
Pa r a mt e r
Sy mb o l
U n it
Not e
M a
x
M a
x
M a
x
M a
x
M in
Ma x
M in
Ma x
M in
Mi n
M in
M in
Operation
t R C
55
55
15
55
55
60
60
18
-
-
-
7 0
7 0
2 0
-
-
-
70
70
20
-
-
-
70
80
20
-
-
-
n s
n s
n s
R A S cycle time
A u t o R e f r e s h
t R R C
t R C D
R A S to C A S delay
R A S a c t i v e t i m e
16.5
1 0 0
K
100
K
100
K
100
K
100
K
1 0 0
K
t R A S
40
38.5
40
4 5
45
45
n s
R A S precharge time
t R P
3
2
3
2
3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
C L K
m s
R A S to R A S b a n k a c t i v e d e l a y
C A S to C A S b a n k a c t i v e d e l a y
Write command to data-in delay
D a t a - i n t o p r e c h a r g e c o m m a n d
Data-in to active command
DQM to data-in Hi-Z
t R R D
t C C D
t W T L
t D P L
t D A L
t D Q Z
t D Q M
t M R D
t P R O Z
t P D E
t S R E
t R E F
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
4
4
4
4
4
3
2
2
2
2
2
2
D Q M t o d a t a m a s k
0
0
0
0
0
0
M R S t o n e w c o m m a n d
Precharge to data output Hi-Z
Power down exit time
2
2
2
2
2
2
3
3
3
3
3
3
1
1
1
1
1
1
Self refresh exit time
1
1
1
1
1
1
3
Refresh Time
64
64
64
6 4
64
64
Note :
1. V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s .
2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V
3. A new command can be given tRRC after self refresh exit.
Rev. 3. 6/ Apr . 01
8
HY57V161610D
DE V ICE OP E RAT ING OP T ION T ABL E
HY5 7 V1 6 1 6 1 0 DT C- 5
C A S Latency
3 C L K s
t R C D
3 C L K s
3 C L K s
3 C L K s
t R A S
8 C L K s
7 C L K s
7 C L K s
tRC
t R P
tAC
t O H
1. 5ns
2 n s
2 0 0 MH z
1 8 3 MH z
1 6 6 MH z
1 1 C L K s
1 0 C L K s
1 0 C L K s
3 C L K s
3 C L K s
3 C L K s
4 . 5 n s
5 n s
3 C L K s
3 C L K s
5 . 5 n s
2 n s
HY5 7 V1 6 1 6 1 0 DT C- 5 5
C A S Latency
t R C D
3 C L K s
3 C L K s
3 C L K s
t R A S
7 C L K s
7 C L K s
7 C L K s
tRC
t R P
tAC
t O H
2 n s
1 8 3 MH z
1 6 6 MH z
1 4 3 MH z
3 C L K s
3 C L K s
3 C L K s
1 0 C L K s
1 0 C L K s
1 0 C L K s
3 C L K s
3 C L K s
3 C L K s
5 n s
5 . 5 n s
5 . 5 n s
2 n s
2. 5ns
HY5 7 V1 6 1 6 1 0 DT C- 6
C A S Latency
t R C D
3 C L K s
3 C L K s
2 C L K s
t R A S
7 C L K s
7 C L K s
6 C L K s
tRC
t R P
tAC
t O H
2 n s
1 6 6 MH z
1 4 3 MH z
1 2 5 MH z
3 C L K s
3 C L K s
3 C L K s
1 0 C L K s
1 0 C L K s
9 C L K s
3 C L K s
3 C L K s
3 C L K s
5 . 5 n s
5 . 5 n s
6 n s
2. 5ns
2. 5ns
HY5 7 V1 6 1 6 1 0 DT C- 7
C A S Latency
t R C D
3 C L K s
3 C L K s
2 C L K s
t R A S
7 C L K s
6 C L K s
5 C L K s
tRC
t R P
tAC
5 . 5 n s
6 n s
t O H
1 4 3 MH z
1 2 5 MH z
1 0 0 MH z
3 C L K s
3 C L K s
2 C L K s
1 0 C L K s
9 C L K s
7 C L K s
3 C L K s
3 C L K s
2 C L K s
2. 5ns
2. 5ns
2. 5ns
7 n s
HY5 7 V1 6 1 6 1 0 DT C- 8
C A S Latency
t R C D
3 C L K s
2 C L K s
2 C L K s
t R A S
6 C L K s
5 C L K s
4 C L K s
tRC
t R P
tAC
6 n s
7 n s
7 n s
t O H
1 2 5 MH z
1 0 0 MH z
8 3 MH z
3 C L K s
3 C L K s
2 C L K s
9 C L K s
7 C L K s
6 C L K s
3 C L K s
2 C L K s
2 C L K s
2. 5ns
2. 5ns
2. 5ns
Rev. 3. 6/ Apr . 01
9
HY57V161610D
COMMAND T RUT H T ABL E
A 1 0 /
C o m m a n d
CKEn-1
H
C K E n
X
C S
R A S
C A S
W E
D Q M
X
A 0~ A 9
B A
Note
A P
M o d e R e g i s t e r S e t
L
H
L
L
X
H
L
L
L
X
H
H
O P c o d e
X
H
H
N o O p e r a t i o n
H
H
H
X
X
X
X
X
X
X
Bank Active
L
R o w A d d r e s s
V
V
R e a d
L
Column
L
L
H
H
L
L
L
H
L
Address
H
R e a d w i t h A u t o p r e c h a r g e
Write
L
Column
H
H
X
X
X
V
Address
H
Write with Auto precharge
P r e c h a r g e A l l B a n k
P r e c h a r g e s e l e c t e d B a n k
Burst Stop
H
X
V
X
X
L
L
H
H
L
L
X
L
H
H
H
H
X
L
X
V
X
X
X
X
U / L D Q M
Auto Refresh
H
X
L
L
L
L
L
H
L
A 9 P i n H i g h
( O t h e r P i n s O P c o d e )
B u r s t - R E A D - S i n g l e - W R I T E
H
H
L
X
X
Entry
L
H
L
L
X
H
X
H
X
H
X
V
L
H
X
H
X
H
X
H
X
V
1
X
H
X
H
X
H
X
V
X
Self Refresh
Exit
L
H
L
H
L
X
X
X
H
L
Entry
P r e c h a r g e p o w e r
d o w n
X
H
L
Exit
H
H
L
Entry
H
L
L
X
X
C l o c k S u s p e n d
X
Exit
H
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2 . X = D o n o t c a r e , L = L o w , H = H i g h , B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s , O p c o d e = O p e r a n d C o d e ,
N O P = N o O p e r a t i o n .
Rev. 3. 6/ Apr . 01
1 0
HY57V161610D
P ACKAGE INF ORMAT ION
400mil 50pin Thin Small Outline Package (TC)
1 M x 1 6 S y n c h r o n o u s D R A M
U N I T : I N C H ( m m )
V
D
D
1
2
5
4
0
9
V
D
S
S
1
D
Q
0
Q
5
4
D
Q
1
3
4
4
4
8
7
D
V
Q
S
1
V
S
S
Q
S
Q
D
D
Q
Q
2
3
5
6
4
4
6
5
D
D
Q
Q
1
1
3
2
V
D
D
Q
7
8
4
4
4
3
V
D
D
Q
D
1
Q
D
D
Q
Q
4
5
1
0
9
4
4
4
2
1
0
D
V
D
Q
S
1
V
S
S
Q
1
1
0
1
S
Q
D
D
Q
Q
6
7
Q
9
1
1
2
3
3
3
9
8
D
V
Q
D
8
5
0
p
i
n
T
x
S O P - I I
V
D
D
Q
D
Q
4
0
0
0
m
i
l
8
2
5
m
i
l
L
D
Q
M
1
1
4
5
3
3
7
6
N
U
C
D
.
8
m
m
p
i
n
p
i
t
c
h
W
E
Q
M
C
A
S
S
1
1
6
7
3
3
5
4
C
C
L
K
R
A
K
E
C
S
1
1
8
9
3
3
3
2
N
A
C
9
A
A
1
1
1
0
0
2
2
0
1
3
3
1
0
A
A
8
7
A
A
A
1
2
2
2
2
3
2
2
9
8
A
A
6
5
A
3
2
2
4
5
2
2
7
6
A
V
4
V
D
D
S
S
Rev. 3. 6/ Apr . 01
1 1
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