HYMD116645D8J-D43 [HYNIX]
Unbuffered DDR SDRAM DIMM; 无缓冲DDR SDRAM DIMM型号: | HYMD116645D8J-D43 |
厂家: | HYNIX SEMICONDUCTOR |
描述: | Unbuffered DDR SDRAM DIMM |
文件: | 总18页 (文件大小:262K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD116645D(L)8J
DESCRIPTION
Hynix HYMD116645D(L)8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules(DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix HYMD116645D(L)8J series con-
sists of eight 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.Hynix
HYMD116645D(L)8J series provide a high performance 8-byte interface in 5.25" width form factor of industry standard.
It is suitable for easy interchange and addition.
Hynix HYMD116645D(L)8J series is designed for high speed of up to 200MHz and offers fully synchronous operations
referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD116645D(L)8J series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
128MB (16M x 64) Unbuffered DDR DIMM based on
16Mx8 DDR SDRAM
•
•
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
•
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
Data inputs on DQS centers when write (centered
DQ)
•
•
2.5V +/- 0.2V VDD and VDDQ Power supply
Data strobes synchronized with output data for read
and input data for write
2.6V +/- 0.1V VDD and VDDQ Power supply for
DDR400
•
•
Programmable CAS Latency 3/ 2 / 2.5 supported
•
•
•
All inputs and outputs are compatible with SSTL_2
interface
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Fully differential clock operations (CK & /CK) with
125MHz/133MHz/166MHz/200MHz
•
•
•
•
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency
Interface
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
HYMD116645D(L)8J-D43
VDD=VDDQ=2.6V
VDD=VDDQ=2.6V
VDD=VDDQ=2.5V
200MHz (DDR400)
SSTL_2
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
HYMD116645D(L)8J-D4
HYMD116645D(L)8J-J
200MHz (DDR400)
166MHz (DDR333)
SSTL_2
SSTL_2
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.0 / Apr. 2003
1
HYMD116645D(L)8J
PIN DESCRIPTION
Pin
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Pin
Pin Description
DQs Power Supply
Ground
CK0,/CK0,CK1,/CK1,CK2,/CK2
VDDQ
VSS
CS0
CKE0
VREF
Reference Power Supply
Power Supply for SPD
/RAS, /CAS, /WE
A0 ~ A11
VDDSPD
SA0~SA2
2
E PROM Address Inputs
2
BA0, BA1
Bank Address
SCL
SDA
E PROM Clock
2
DQ0~DQ63
Data Inputs/Outputs
E PROM Data I/O
DQS0~DQS7
DM0~DM7
VDD
Data Strobe Inputs/Outputs
Data-in Mask
VDDID
DU
VDD Identification Flag
Do not Use
Power Supply
NC
No Connection
PIN ASSIGNMENT
Pin
1
Name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Name
A5
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
Pin
93
94
95
96
97
98
99
Name
VSS
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Name
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
2
3
4
5
6
7
8
9
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQ30
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
DQ31
CB4*
CB5*
VDDQ
CK0
/CK0
VSS
DM8*
A10
VSS
DQ8
Vss
A1
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
WP
SDA
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
NC
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ9
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
CB6*
VDDQ
CB7*
Key
key
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
A9
DQ18
A7
VDDQ
DQ19
DM4
DQ38
DQ39
VSS
SCL
DQ23
DQ44
VDDSPD
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.0 / Apr. 2003
2
HYMD116645D(L)8J
FUNCTIONAL BLOCK DIAGRAM
/CS0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS
DQS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D4
DQS1
DM1/DQS10
DQS5
DM5/DQS14
DM
/CS
DM
/CS
I/O0
I/O1
I/O2
I/O0
I/O1
I/O2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
I/O3
I/O4
I/O5
I/O6
I/O7
I/O3
I/O4
I/O5
I/O6
I/O7
DQ43
D1
D5
DQ44
DQ45
DQ46
DQ47
DQS2
DM2/DQS11
DQS6
DM6/DQS15
DM
/CS
DM
/CS
I/O0
I/O1
I/O2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O0
I/O1
I/O2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O3
I/O4
I/O5
I/O6
I/O7
D6
DQS3
DM3/DQS12
DQS7
DM7/DQS16
DM
/CS
DM
/CS
DQ24
DQ25
DQ26
DQ56
DQ57
DQ58
I/O0
I/O1
I/O2
I/O0
I/O1
I/O2
D3
D7
DQ27
DQ28
DQ59
DQ60
I/O3
I/O4
I/O3
I/O4
DQ29
DQ30
DQ31
DQ61
DQ62
DQ63
I/O5
I/O6
I/O7
I/O5
I/O6
I/O7
VDD SPD
VDD /VDDQ
VREF
SPD
Serial PD
*Clock Wiring
SDA
DO-D7
DO-D7
DO-D7
Clock Input
SDRAMs
SCL
W
P
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
A0
A1
A2
VSS
SA0 SA1 SA2
VDDID
*Wire per Clock Loading
Table/Wiring Diagrams
Strap:see Note 4
Note :
1. DQ-to-I/O wiring is shown as recommended but may
BA0-BA1
BA0-BA1 : SDRAMs D0-D7
A0-A11 : SDRAMs D0-D7
/RAS : SDRAMs D0-D7
/CAS : SDRAMs D0-D7
CKE : SDRAMs D0-D7
/WE : SDRAMs D0-D7
be changed.
A0-A11
/RAS
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms ? 5%.
/CAS
CKE
0
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ?V DDQ
/WE
5. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ? 5%
Rev. 0.0 / Apr. 2003
3
HYMD116645D(L)8J
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
oC
Ambient Temperature
TA
0 ~ 70
oC
V
Storage Temperature
TSTG
VIN
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
Voltage on Inputs relative to VSS
Voltage on I/O Pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
VIO
V
VDD
V
VDDQ
IOS
V
mA
W
PD
8
oC / Sec
Soldering Temperature Þ Time
TSOLDER
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Input High Voltage
VDD
VDD
2.3
2.5
2.5
2.7
2.7
V
V
V
V
V
V
V
V
2.6
4
1
VDDQ
VDDQ
VIH
2.3
2.5
2.7
2.5
2.6
2.7
1,4
VREF + 0.15
-0.3
-
-
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
Input Low Voltage
VIL
2
3
Termination Voltage
Reference Voltage
VTT
VREF - 0.04
0.49*VDDQ
VREF
0.5*VDDQ
VREF
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
4. For DDR400, VDD=2.6V +/- 0.1V, VDDQ=2.6V+/-0.1V
Rev. 0.0 / Apr. 2003
4
HYMD116645D(L)8J
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
VREF - 0.31
VDDQ + 0.6
0.7
1
2
Input Crossing Point Voltage, CK and /CK inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
Termination Voltage
VDDQ x 0.5
V
V
VDDQ x 0.5
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
VREF + 0.31
V
VREF - 0.31
V
VREF
VTT
1.5
1
V
V
V
Input minimum Signal Slew Rate
V/ns
Ω
Termination Resistor (RT)
50
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Rev. 0.0 / Apr. 2003
5
HYMD116645D(L)8J
CAPACITANCE (TA=25oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Capacitance
A0 ~ A11, BA0, BA1
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
58
58
58
58
25
8
72
72
72
72
40
12
12
pF
pF
pF
pF
pF
pF
pF
Input Capacitance
/RAS, /CAS, /WE
CKE0
Input Capacitance
Input Capacitance
CS0
Input Capacitance
CK0, /CK0, CK1, /CK1, CK2,/CK2
DM0 ~ DM7
Input Capacitance
Data Input / Output Capacitance
DQ0 ~ DQ63, DQS0 ~ DQS7
7.89
Note :
1. VDD = min. to max., VDDQ = 2.5V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
Ω
RT=50
Output
Ω
Zo=50
VREF
CL=30pF
Rev. 0.0 / Apr. 2003
6
HYMD116645D(L)8J
o
DC CHARACTERISTICS I (TA=0 to 70 C, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min.
Max
Unit
Note
Add, CMD, /CS, /CKE
CK, /CK
-16
16
Input Leakage
Current
ILI
uA
1
-12
12
Output Leakage Current
Output High Voltage
Output Low Voltage
ILO
VOH
VOL
-5
5
uA
V
2
VTT + 0.76
-
-
IOH = -15.2mA
IOL = +15.2mA
VTT - 0.76
V
Note :
1. VIN = 0 to 2.7V, All other pins are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 2.7V
Rev. 0.0 / Apr. 2003
7
HYMD116645D(L)8J
o
DC CHARACTERISTICS II (TA=0 to 70 C, Voltage referenced to VSS = 0V)
Speed
Parameter
Operating Current
Operating Current
Symbol
Test Condition
Unit Note
D43
D4
-J
One bank; Active Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
960
720
mA
One bank; Active - Read Precharge; Burst Length
=2; tRC=tRC(min); tCK=tCK(min); address and
control inputs changing once per clock cycle
IDD1
IDD2P
IDD2F
IDD3P
960
160
480
160
880
160
320
160
mA
mA
mA
mA
Precharge Power
Down Standby Current
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle ; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
Idle Standby Current
Active Power Down
Standby Current
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
Active Standby
Current
IDD3N
520
320
mA
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Operating Current
Operating Current
IDD4R
IDD4W
1840
1840
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM, and DQS
inputs changing twice per clock cycle
mA
1840
1440
1840
1280
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz,
12*tCK for DDR333 at 166Mhz; distributed refresh
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
IDD7
Normal
16
8
16
8
mA
mA
CKE=<0.2V; External clock on;
tCK=tCK(min)
Low Power
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
2400
2400
mA
Rev. 0.0 / Apr. 2003
8
HYMD116645D(L)8J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
DDR400 (D43)
DDR400 (D4)
Parameter
Symbol
Unit
Note
Min
55
70
40
tRCD
15
10
1
Max
Min
58
70
40
tRCD
18
10
1
Max
Row Cycle Time
tRC
tRFC
tRAS
tRAP
tRCD
tRRD
tCCD
tRP
-
-
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
Auto Refresh Row Cycle Time
Row Active Time
-
-
70K
70K
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
15
15
2
18
15
2
Write Recovery Time
tWR
tWTR
Write to Read Command Delay
(tWR/tCK)
+
(tWR/tCK)
+
Auto Precharge Write Recovery + Precharge Time
tDAL
-
-
CK
15
(tRP/tCK)
(tRP/tCK)
System Clock Cycle Time
CL = 3
tCK
tCH
5
10
5
10
ns
CK
CK
ns
Clock High Level Width
0.45
0.45
-0.7
-0.55
-
0.55
0.55
0.7
0.45
0.45
-0.7
-0.55
-
0.55
0.55
0.7
Clock Low Level Width
tCL
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
tAC
tDQSCK
tDQSQ
0.55
0.4
0.55
0.4
ns
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
ns
tHP
-tQHS
tHP
-tQHS
tQH
tHP
-
-
-
-
ns
ns
1, 10
1,9
min
(tCL,tCH)
min
(tCL,tCH)
Clock Half Period
Data Hold Skew Factor
tQHS
tHZ
tLZ
tIS
-
0.5
-
0.5
ns
ns
ns
ns
ns
ns
ns
10
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
tAC(Max)
tAC(Max)
17
tAC(min) tAC(Max) tAC(min) tAC(Max)
17
0.6
0.6
0.6
0.6
-
-
-
-
0.6
0.6
0.6
0.6
-
-
-
-
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
tIH
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
tIS
tIH
Rev. 0.0 / Apr. 2003
9
HYMD116645D(L)8J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
DDR400 (D43)
DDR400 (D4)
Parameter
Symbol
Unit
Note
Min
2.2
0.35
0.35
0.72
0.2
0.2
0.4
0.4
1.6
0.9
0.4
0
Max
Min
2.2
0.35
0.35
0.72
0.2
0.2
0.4
0.4
1.6
0.9
0.4
0
Max
Input Pulse Width
tIPW
tDQSH
tDQSL
tDQSS
tDSS
-
-
ns
CK
CK
CK
CK
CK
ns
6
Write DQS High Level Width
-
-
-
-
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
1.28
1.28
tDSH
tDS
-
-
-
-
6,7,11,
12,13
tDH
ns
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
-
-
ns
6
Read DQS Preamble Time
1.1
0.6
-
1.1
0.6
-
CK
CK
CK
CK
CK
CK
ns
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
0.25
0.4
2
-
0.25
0.4
2
-
0.6
-
0.6
-
Mode Register Set Delay
Exit self refresh to non-READ command
Exit self refresh to READ command
Average Periodic Refresh Interval
tXSNR
tXSRD
tREFI
75
-
75
-
8
8
200
-
-
200
-
-
CK
us
7.8
7.8
Rev. 0.0 / Apr. 2003
10
HYMD116645D(L)8J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
DDR333(J)
Parameter
Symbol
Unit
Note
Min
Max
Row Cycle Time
tRC
tRFC
tRAS
tRAP
tRCD
tRRD
tCCD
tRP
60
72
42
18
18
12
1
-
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
Auto Refresh Row Cycle Time
Row Active Time
-
70K
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
-
-
-
-
-
-
-
16
18
15
1
Write Recovery Time
tWR
tDRL
Last Data-In to Read Command
(tWR/tCK)
+
Auto Precharge Write Recovery + Precharge Time
tDAL
tCK
-
CK
15
(tRP/tCK)
CL = 2.5
CL = 2
6
12
12
ns
ns
System Clock Cycle Time
7.5
0.45
0.45
-0.7
-0.6
-
Clock High Level Width
tCH
tCL
0.55
0.55
0.7
CK
CK
ns
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tAC
tDQSCK
tDQSQ
0.6
ns
0.45
ns
tHP
Data-Out hold time from DQS
tQH
tHP
-
-
ns
ns
1, 10
1,9
-tQHS
min
(tCL,tCH)
Clock Half Period
Data Hold Skew Factor
tQHS
tHZ
tLZ
tIS
-
0.55
ns
ns
ns
ns
ns
ns
ns
10
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
-0.7
-0.7
0.75
0.75
0.8
0.7
17
0.7
17
-
-
-
-
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
Input Hold Time (fast slew rate)
tIH
Input Setup Time (slow slew rate)
tIS
Input Hold Time (slow slew rate)
tIH
0.8
Rev. 0.0 / Apr. 2003
11
HYMD116645D(L)8J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
DDR333(J)
Parameter
Symbol
Unit
Note
Min
Max
Input Pulse Width
tIPW
tDQSH
tDQSL
tDQSS
tDS
2.2
0.35
0.35
0.75
0.45
0.45
1.75
0.9
0.4
0
ns
CK
CK
CK
ns
6
Write DQS High Level Width
-
Write DQS Low Level Width
-
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
1.25
-
6,7, 11~13
6,7, 11~13
tDH
-
-
ns
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
ns
Read DQS Preamble Time
1.1
0.6
-
CK
CK
CK
CK
CK
CK
ns
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
0.25
0.4
2
-
0.6
-
Mode Register Set Delay
tXSNR
tXSRD
tREFI
Exit self refresh to non-READ command
Exit self refresh to READ command
Average Periodic Refresh Interval
75
-
8
8
200
-
-
CK
us
7.8
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11., BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
ps
Delta tIH
V/ns
0.5
ps
0
0
0.4
+50(+150)
+100(+225)
0
0.3
0
( ) → DDR400 Operation
5. CK, /CK slew rates are >=1.0V/ns, ie, >=2.0V/ns differential.
6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
Rev. 0.0 / Apr. 2003
12
HYMD116645D(L)8J
8.
9.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, are
required for READ command to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
For other commands, time interval of tRFC+2~5ns is required after Self Refresh Exit command.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
0.5
ps
ps
0
0
0.4
+75
+75(+100)
+150(+170)
0.3
+150
( ) → DDR400 Operation
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
0
ps
0
ps
0
+/-0.25
+/- 0.5
+50
+100
+50
+100
14.
15.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transi tions through the DC region must be monotonic.
tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR400 at CL=3 and tCK = 5 ns,
tDAL = (15 ns / 5.0 ns) + (18 ns / 5.0 ns) = (3.00) + (3.6)
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 7 clock
16.
17.
For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Rev. 0.0 / Apr. 2003
13
HYMD116645D(L)8J
SIMPLIFIED COMMAND TRUTH TABLE
A10/
ADDR
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
BA
Note
AP
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
H
H
X
X
L
L
H
L
L
L
L
L
L
L
L
OP code
OP code
1,2
1,2
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active
RA
V
V
1
1
Read
L
H
L
L
L
L
H
H
L
L
L
H
L
L
CA
CA
X
Read with Autoprecharge
Write
1,3
1
H
H
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
H
H
L
1,4
1,5
1
X
V
H
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
L
L
L
1
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry
Precharge
Power Down
H
L
Mode
Exit
H
H
L
Entry
H
L
L
Active Power
Down Mode
Exit
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.0 / Apr. 2003
14
HYMD116645D(L)8J
PACKAGE DIMENSIONS
Front
133.35
5.25
131.35
5.171
Side
128.95
5.077
3.18
0.125MAX
31.75
1.250
(Front)
1.27+/-0.10
0.050+/-.004
(2) 0
2.5
0.098
Rev. 0.0 / Apr. 2003
15
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(16Mx64 Unbuffered DDR DIMM)
Rev. 0.0 / Apr. 2003
16
HYMD116645D(L)8J
SERIAL PRESENCE DETECT
Bin Sort : D4/D43(DDR400@CL=3), J(DDR333@CL=2.5)
Function Supported
Hexa Value
D4
Note
Byte#
Function Description
D43
D4
J
D43
J
0
1
2
3
4
5
6
7
8
Number of Bytes written into serial memory at module manufacturer
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of physical banks on DIMM
Module data width
128 Bytes
256 Bytes
DDR SDRAM
12
10
1Bank
64 Bits
-
SSTL 2.5V
5.0ns
80h
08h
07h
0Ch
0Ah
01h
40h
00h
04h
50h
1
1
Module data width (continued)
Module voltage Interface levels(VDDQ)
DDR SDRAM cycle time at CAS Latency=2.5(tCK)@DDR333,
5.0ns
6.0ns
50h
60h
2
2
9
3(tCK)@DDR400
10
11
12
13
14
DDR SDRAM access time from clock at CL=2.5 (tAC)
Module configuration type
Refresh rate and type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
+/-0.7ns
Non-ECC
15.6us & Self refresh
70h
00h
80h
08h
00h
x8
N/A
Minimum clock delay for back-to-back random column
15
1 CLK
01h
address(tCCD)
16
17
18
19
20
21
Burst lengths supported
Number of banks on each DDR SDRAM
CAS latency supported
CS latency
WE latency
DDR SDRAM module attributes
2,4,8
4 Banks
2, 2.5, 3 2, 2.5, 3
0Eh
04h
1Ch
01h
02h
20h
2, 2.5
1Ch
0Ch
0
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
22
DDR SDRAM device attributes : General
C0h
23
24
25
26
27
28
29
30
31
32
33
34
35
DDR SDRAM cycle time at CL=2.0(tCK), 2.5(tCK)
DDR SDRAM access time from clock at CL=2.0(tAC), 2.5(tAC)
DDR SDRAM cycle time at CL=1.5(tCK), 2.0(tCK)
DDR SDRAM access time from clock at CL=1.5(tAC), 2.0(tAC)
Minimum row precharge time(tRP)
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
6ns
6ns
7.5ns
60h
70h
75h
75h
3Ch
28h
3Ch
28h
60h
70h
75h
75h
48h
28h
48h
28h
20h
60h
60h
40h
40h
00h
3Ah
75h
70h
00h
00h
48h
30h
48h
2Ah
2
2
2
2
+/-0.7ns +/-0.7ns +/-0.7ns
7.5ns
+/-0.75ns +/-0.75ns
15ns
10ns
15ns
40ns
7.5ns
-
-
18ns
10ns
18ns
18ns
12ns
18ns
42ns
40n
128MB
0.6ns
0.6ns
0.4ns
0.4ns
Undefined
58ns
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
0.6ns
0.6ns
0.4ns
0.4ns
0.75ns
0.75ns
0.45ns
0.45ns
60h
60h
40h
40h
75h
75h
45h
45h
Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41
Minimum active / auto-refresh time ( tRC)
55ns
70ns
60ns
72ns
37h
46h
3Ch
48h
Minimum auto-refresh to active/auto-refresh
42
70ns
46h
command period(tRFC)
43
44
45
Maximum cycle time (tCK max)
Maximim DQS-DQ skew time(tDQSQ)
Maximum read data hold skew factor(tQHS)
10ns
0.4ns
0.50ns
10ns
0.4ns
0.50ns
12ns
0.45ns
0.55ns
28h
28h
50h
28h
28h
50h
00h
00h
5Eh
ADh
00h
30h
2Dh
55h
46~61 Superset information(Reserved for IDD values, Tcase, etc.)
Undefined
Initial release
-
62
63
64
SPD Revision code
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
43h
DDh
Hynix JEDEC ID
-
65~71 --------- Manufacturer JEDEC ID Code
Rev. 0.0 / Apr. 2003
17
HYMD116645D(L)8J
SERIAL PRESENCE DETECT
- continued -
Function Supported
D43 D4
Hynix(Korea Area)
Hexa Value
Note
Byte #
Function Description
J
D43
D4
J
0*h
1*h
2*h
3*h
4*h
5*h
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
72
Manufacturing location
6
Asia Area
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
Manufacture part number (DDR SDRAM)
Manufacture part number(Memory density)
Manufacture part number(Module Depth)
------- Manufacture part number(Module Depth)
Manufacture part number(Module type)
Manufacture part number(Data width)
-------Manufacture part number(Data width)
Manufacture part number(Refresh, # of Bank.)
Manufacture part number(Component Generation)
Manufacture part number(Component configuration)
Manufacture part number(Module Type)
Manufacture part number(Hyphen)
H
Y
M
D
1
1
6
Blank
6
4
48h
59h
4Dh
44h
31h
31h
36h
20h
36h
34h
35h
44h
38h
4Ah
2Dh
44h
34h
20h
-
5(4K refresh,4Bank)
D
8
J
‘-’
D
Manufacture part number(Minimum cycle time)
Manufacture part number(Minimum cycle time)
Manufacture part number(Minimum cycle time
Manufacture revision code(for Component)
Manufacture revision code (for PCB)
D
4
3
J
44h
34h
33h
4Ah
20h
20h
4
Blank
Blank
Blank
-
-
-
-
-
-
-
-
-
Manufacturing date(Year)
Manufacturing date(Week)
3
3
4
5
5
95~98 Module serial number
99~127 Manufacturer specific data (may be used in future)
128~255 Open for customer use
Undefined
Undefined
00h
00h
Note :
1. The bank address is excluded
2. These value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number system
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix web site
Byte 85~86, Low power part
Function
Supported
Byte#
Function Description
Hexa Value
Note
85
86
Manufacture part number(Low power part)
L
8
4Ch
38h
Manufacture part number(Component configuration)
Rev. 0.0 / Apr. 2003
18
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