HYMD116M645B8-H_技术文档

16Mx64 bits

Unbuffered DDR SDRAM SO-DIMM

HYMD116M645B(L)8-J/M/K/H/L

DESCRIPTION

Hynix HYMD116M645B(L)8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline

Dual In-Line Memory Modules (SO-DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix

HYMD116M645B(L)8-J/M/K/H/L series consists of eight 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin

glass-epoxy substrate. Hynix HYMD116M645B(L)8-J/M/K/H/L series provide a high performance 8-byte interface in

67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD116M645B(L)8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control

inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on

both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high

bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable

latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD116M645B(L)8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function

is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden-

tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

128MB (16M x 64) Unbuffered DDR SO-DIMM based

on 16Mx8 DDR SDRAM

•

Data inputs on DQS centers when write (centered

DQ)

•

JEDEC Standard 200-pin small outline dual in-line

memory module (SO-DIMM)

Data strobes synchronized with output data for read

and input data for write

•

2.5V +/- 0.2V VDD and VDDQ Power supply

•

Programmable CAS Latency 2 / 2.5 supported

All inputs and outputs are compatible with SSTL_2

interface

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz/166MHz

•

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

4096 refresh cycles / 64ms

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

•

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Factor

HYMD116M645B(L)8-J

HYMD116M645B(L)8-M

HYMD116M645B(L)8-K

HYMD116M645B(L)8-H

HYMD116M645B(L)8-L

166MHz (*DDR333)

133MHz (*DDR266:2-2-2)

133MHz (*DDR266A)

133MHz (*DDR266B)

125MHz (*DDR200)

VDD=2.5V

VDDQ=2.5V

200pin Unbuffered SO-DIMM

67.6 x 31.75 x 1 mm

SSTL_2

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.3/May. 02

1

HYMD116M645B(L)8-J/M/K/H/L

PIN DESCRIPTION

Pin Description

Differential Clock Inputs

Chip Select Input

Clock Enable Input

Commend Sets Inputs

Address

Pin Description

DQs Power Supply

Ground

CK0, /CK0, CK1, /CK1

CS0, CS1

VDDQ

VSS

CKE0, CKE1

/RAS, /CAS, /WE

A0 ~ A11

VREF

Reference Power Supply

Power Supply for SPD

VDDSPD

SA0~SA2

2

E PROM Address Inputs

2

BA0, BA1

Bank Address

SCL

E PROM Clock

2

DQ0~DQ63

Data Inputs/Outputs

SDA

E PROM Data I/O

DQS0~DQS7

DM0~DM7

VDD

Data Strobe Inputs/Outputs

Data-in Mask

VDDID

DU

VDD Identification Flag

Do not Use

Power Supply

NC

No Connection

PIN ASSIGNMENT

Name

1

A9

VREF

2

VREF

51

VSS

52

VSS

101

102

A8

151

DQ42

152

DQ46

3

VSS

DQ0

DQ1

VDD

DQS0

DQ2

VSS

4

VSS

DQ4

DQ5

VDD

DM0

DQ6

VSS

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

DQ19

DQ24

VDD

DQ25

DQS3

VSS

DQ26

DQ27

VDD

NC

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

DQ23

DQ28

VDD

DQ29

DM3

VSS

DQ30

DQ31

VDD

NC

103

105

107

109

111

113

VSS

A7

104

106

108

110

112

114

VSS

A6

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

DQ43

VDD

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

DQ47

VDD

/CK1

CK1

5

6

7

8

A5

A4

VDD

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

A3

A2

VSS

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

A1

A0

VSS

VDD

BA1

DQ48

DQ49

VDD

DQ52

DQ53

VDD

DM6

DQ54

VSS

115 A10/AP 116

DQ3

DQ8

VDD

DQ9

DQS1

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

BA0

/WE

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

/RAS

/CAS

/CS1

DU

DQS6

DQ50

VSS

/CS0

DU

NC

VSS

NC

VSS

NC

VSS

DQ51

DQ56

VDD

DQ55

DQ60

VDD

DQ61

DM7

VSS

DQ32

DQ33

VDD

DQS4

DQ34

VSS

DQ36

DQ37

VDD

DM4

DQ38

VSS

DQ10

DQ11

VDD

CK0

DQ14

DQ15

VDD

VSS

NC

VDD

NC

VDD

NC

DQ57

DQS7

VSS

DU

/CK0

VSS

NC

VSS

VDD

CKE0

DU

DQ58

DQ59

VDD

DQ62

DQ63

VDD

SA0

VSS

DQ35

DQ40

VDD

DQ41

DQS5

VSS

DQ39

DQ44

VDD

DQ45

DM5

VSS

DQ16

DQ17

VDD

DQS2

DQ18

DQ20

DQ21

VDD

DM2

DQ22

NC

VDD

CKE1

NC

SDA

SCL

SA1

197 VDDSPD 198

199 VDDID 200

SA2

NC

A11

DU

Rev. 0.3/May. 02

2

HYMD116M645B(L)8-J/M/K/H/L

FUNCTIONAL BLOCK DIAGRAM

/CS0

DQS0

DM0

DQS4

DM4

DQS

DM

/CS

DM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D4

DQS1

DM1

DQS5

DM5

DQS

DM

/CS

DM

/CS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

/CS

DM

/CS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS3

DM3

DQS7

DM7

DM

/CS

DM

/CS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D7

Serial PD

.

SPD

VDDSPD

.

D0 - D7

VDD/VDDQ

SCL

WP

= =

.

SDA

VREF

VSS

=

. . . .

A0

A1

A2

D0 - D7

..

VDDID

Strap:see Note 4

SA0

SA1

SA2

Notes:

1. DQ-to-I/O wiring is shown as recommended

but may be changed

BA0-BA1

A0 - A11

BA0-BA1 : SDRAMs D0 - D7

A0 - A11 : SDRAMs D0 - D7

/RAS : SDRAMs D0 - D7

/CAS : SDRAMs D0 - D7

CKE : SDRAMs D0 - D7

/WE : SDRAMs D0 - D7

2. DQ/DQS/DM/CKE/S relationships must be

maintained as shown

/RAS

/CAS

CKE0

/WE

3. DQ, DQS, DM/DQS resistors : 22Ohms+/-5%

4. VDDID strap connections

(for memory device VDD, VDDQ) :

Strap out :(open) : VDD=VDDQ

Strap In (Vss) : VDD= VDDQ

Rev. 0.3/May. 02

3

HYMD116M645B(L)8-J/M/K/H/L

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

0 ~ 70

^oC

V

Storage Temperature

TSTG

-55 ~ 125

-0.5 ~ 3.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Output Short Circuit Current

Power Dissipation

VIN, VOUT

VDD

V

VDDQ

IOS

V

mA

W

PD

8

^oC / Sec

Soldering Temperature / Time

TSOLDER

260 / 10

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70 ^oC, Voltage referenced to VSS=0V)

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

Input High Voltage

Input Low Voltage

Termination Voltage

Reference Voltage

Note :

VDD

VDDQ

VIH

2.3

2.5

-

2.7

V

1

2

3

VREF + 0.15

-0.3

VDDQ + 0.3

VREF - 0.15

VREF + 0.04

1.35

VIL

-

VTT

VREF - 0.04

1.15

VREF

1.25

VREF

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. The value of VREF is approximately equal to 0.5VDDQ.

AC OPERATING CONDITIONS (TA=0 to 70 ^oC, Voltage referenced to VSS=0V)

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

Input Differential Voltage, CK and /CK inputs

Input Crossing Point Voltage, CK and /CK inputs

Note :

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

VREF + 0.31

V

VREF - 0.31

VDDQ + 0.6

0.7

1

2

0.5*VDDQ-0.2

0.5*VDDQ+0.2

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

Rev. 0.3/May. 02

4

HYMD116M645B(L)8-J/M/K/H/L

AC OPERATING TEST CONDITIONS (TA=0 to 70^oC, Voltage referenced to VS=0V)

Parameter

Value

Unit

Reference Voltage

Termination Voltage

VDDQ x 0.5

V

VDDQ x 0.5

AC Input High Level Voltage (VIH, min)

AC Input Low Level Voltage (VIL, max)

Input Timing Measurement Reference Level Voltage

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

VREF + 0.31

V

VREF - 0.31

V

VREF

VTT

1.5

1

V

Input minimum Signal Slew Rate

V/ns

Ω

Termination Resistor (RT)

50

Series Resistor (RS)

25

Ω

Output Load Capacitance for Access Time Measurement (CL)

30

pF

Rev. 0.3/May. 02

5

HYMD116M645B(L)8-J/M/K/H/L

CAPACITANCE (TA=25^oC, f=100MHz )

Parameter

Symbol

Min

Max

Unit

Input Capacitance

A0 ~ A11, BA0, BA1

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIO1

TBD

pF

Input Capacitance

/RAS, /CAS, /WE

CKE0, CKE1

Input Capacitance

/CS0, /CS1

Input Capacitance

CK0, /CK0, CK1, /CK1

DM0 ~ DM7

Input Capacitance

Data Input / Output Capacitance

DQ0 ~ DQ63, DQS0 ~ DQS7

Note :

1. VDD=min. to max., VDDQ=2.3V to 2.7V, VODC=VDDQ/2, VOpeak-to-peak=0.2V

2. Pins not under test are tied to GND.

3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

VTT

Ω

RT=50

Output

Ω

Zo=50

REF

V

CL=30pF

Rev. 0.3/May. 02

6

HYMD116M645B(L)8-J/M/K/H/L

DC CHARACTERISTICS I (TA=0 to 70^oC, Voltage referenced to VSS=0V)

Parameter

Symbol

Min.

Max

Unit

Note

Add, CMD, /CS, /CKE

-16

16

Input Leakage

Current

CK0, /CK0, CK1, /CK1

CK2, /CK2

ILI

-8

8

uA

1

0

Output Leakage Current

Output High Voltage

Output Low Voltage

ILO

VOH

VOL

-5

5

uA

V

2

VTT + 0.76

-

IOH = -15.2mA

IOL = +15.2mA

VTT - 0.76

V

Note :

1. VIN=0 to 3.6V, All other pins are not tested under VIN=0V

2. DOUT is disabled, VOUT=0 to 2.7V

Rev. 0.3/May. 02

7

HYMD116M645B(L)8-J/M/K/H/L

DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Speed

-M -K

Parameter

Symbol

Test Condition

Unit Note

-J

-H

-L

One bank; Active - Precharge; tRC=tRC(min);

tCK=tCK(min); DQ,DM and DQS inputs changing

twice per clock cycle; address and control inputs

changing once per clock cycle

IDD0

720

640

mA

Operating Current

One bank; Active - Read - Precharge;

Burst Length= 2; tRC=tRC(min); tCK=tCK(min);

address and control inputs changing once per

clock cycle

Operating Current

IDD1

880

160

320

880

120

280

800

120

800

120

280

640

120

280

mA

Precharge Power

Down Standby

Current

All banks idle; Power down mode ; CKE=Low,

tCK=tCK(min)

IDD2P

/CS=High, All banks idle; tCK=tCK(min);

CKE=High; address and control inputs changing

once per clock cycle.

Idle Standby Current

IDD2F

IDD3P

280

160

mA

VIN=VREF for DQ, DQS and DM

Active Power Down

Standby Current

One bank active; Power down mode; CKE=Low,

tCK=tCK(min)

/CS=HIGH; CKE=HIGH; One bank; Active-

Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,

Active Standby

Current

IDD3N DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing

once per clock cycle

320

mA

Burst=2; Reads; Continuous burst; One bank

Operating Current

IDD4R active; Address and control inputs changing once 1840 1520 1520 1520 1200 mA

per clock cycle; tCK=tCK(min); IOUT = 0mA

Burst=2; Writes; Continuous burst; One bank

active; Address and control inputs changing once

IDD4W

IDD5

1840 1520 1520 1520 1200 mA

1280 1200 1200 1200 1120 mA

per clock cycle; tCK=tCK(min); DQ, DM and DQS

inputs changing twice per clock cycle

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz;

distributed refresh

Auto Refresh

Current

Normal

16

8

mA

CKE=<0.2V; External clock on;

tCK=tCK(min)

Self Refresh Current

IDD6

IDD7

Low Power

Operating Current -

Four Bank Operation

Four bank interleaving with BL=4, Refer to the

following page for detailed test condition

2400 2080 2080 2080 1760 mA

Rev. 0.3/May. 02

8

HYMD116M645B(L)8-J/M/K/H/L

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

<DDR333, DDR266(2-2-2)>

DDR333

DDR266(2-2-2)

Parameter

Symbol

Unit

Note

Min

Max

Min

60

75

45

15

1

Max

Row Cycle Time

tRC

tRFC

tRAS

tRAP

tRCD

tRRD

tCCD

tRP

60

72

42

18

12

1

-

ns

CK

ns

CK

Auto Refresh Row Cycle Time

Row Active Time

-

70K

120K

Active to Read with Auto Precharge Delay

Row Address to Column Address Delay

Row Active to Row Active Delay

Column Address to Column Address Delay

Row Precharge Time

-

16

18

15

1

15

1

Write Recovery Time

tWR

tWTR

Write to Read Command Delay

(tWR/tCK)

+

(tWR/tCK)

+

Auto Precharge Write Recovery + Precharge Time

tDAL

tCK

-

CK

15

(tRP/tCK)

CL = 2.5

System Clock Cycle Time

CL = 2

6

12

7.5

12

ns

CK

ns

7.5

12

Clock High Level Width

tCH

tCL

0.45

-0.7

-0.6

-

0.55

0.7

0.45

-0.75

-

0.55

0.75

0.5

Clock Low Level Width

Data-Out edge to Clock edge Skew

DQS-Out edge to Clock edge Skew

DQS-Out edge to Data-Out edge Skew

tAC

tDQSCK

tDQSQ

0.6

0.45

tHP

-tQHS

tHP

-tQHS

Data-Out hold time from DQS

Clock Half Period

tQH

tHP

-

ns

1, 10

min

(tCL,tCH)

min

(tCL,tCH)

-

1,9

10

Data Hold Skew Factor

tQHS

tDV

tHZ

tLZ

-

0.55

-

0.75

ns

Valid Data Output Window

tQH-tDQSQ

Data-out high-impedance window from CK, /CK

Data-out low-impedance window from CK, /CK

Input Setup Time (fast slew rate)

Input Hold Time (fast slew rate)

Input Setup Time (slow slew rate)

Input Hold Time (slow slew rate)

Input Pulse Width

-0.7

0.75

0.8

0.7

-0.75

0.9

0.75

17

0.7

0.75

tIS

-

2,3,5,6

2,4,5,6

6

tIH

0.9

tIS

1.0

tIH

0.8

1.0

tIPW

2.2

Rev. 0.3/May. 02

9

HYMD116M645B(L)8-J/M/K/H/L

DDR333

DDR266(2-2-2)

Parameter

Symbol

Unit

Note

Min

Max

Min

0.35

0.72

0.5

1.75

0.9

0.4

0

Max

Write DQS High Level Width

tDQSH

tDQSL

tDQSS

tDS

0.35

0.75

0.45

1.75

0.9

0.4

0

-

CK

ns

Write DQS Low Level Width

-

Clock to First Rising edge of DQS-In

Data-In Setup Time to DQS-In (DQ & DM)

Data-in Hold Time to DQS-In (DQ & DM)

DQ & DM Input Pulse Width

1.25

1.28

-

6,7, 11~13

tDH

-

ns

tDIPW

tRPRE

tRPST

tWPRES

tWPREH

tWPST

tMRD

ns

Read DQS Preamble Time

1.1

0.6

-

1.1

0.6

-

CK

us

Read DQS Postamble Time

Write DQS Preamble Setup Time

Write DQS Preamble Hold Time

Write DQS Postamble Time

0.25

0.4

2

-

0.25

0.4

2

-

0.6

-

0.6

-

Mode Register Set Delay

Exit Self Refresh to Any Execute Command

Average Periodic Refresh Interval

tXSC

200

-

200

-

8

tREFI

15.6

Rev. 0.3/May. 02

10

HYMD116M645B(L)8-J/M/K/H/L

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

DDR266A

Min Max

DDR266B

DDR200

Parameter

Symbol

Unit

Note

Min

65

75

45

20

15

1

Max

Min

70

80

50

20

15

1

Max

Row Cycle Time

tRC

tRFC

tRAS

tRAP

tRCD

tRRD

tCCD

tRP

65

75

45

20

15

1

-

ns

CK

ns

CK

Auto Refresh Row Cycle Time

Row Active Time

-

120K

120k

Active to Read with Auto Precharge Delay

Row Address to Column Address Delay

Row Active to Row Active Delay

Column Address to Column Address Delay

Row Precharge Time

-

16

20

15

1

20

15

1

20

15

1

Write Recovery Time

tWR

tWTR

Write to Read Command Delay

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

Auto Precharge Write Recovery + Precharge

Time

tDAL

tCK

-

CK

15

CL = 2.5

System Clock Cycle Time

CL = 2

7.5

12

7.5

10

12

8.0

10

12

ns

CK

ns

12

Clock High Level Width

tCH

tCL

0.45

-0.75

-

0.55

0.75

0.5

0.45

-0.75

-

0.55

0.75

0.5

0.45

-0.8

-

0.55

0.8

0.6

Clock Low Level Width

Data-Out edge to Clock edge Skew

DQS-Out edge to Clock edge Skew

DQS-Out edge to Data-Out edge Skew

tAC

tDQSCK

tDQSQ

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

Data-Out hold time from DQS

Clock Half Period

tQH

tHP

-

ns

1, 10

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

-

1,9

10

Data Hold Skew Factor

tQHS

tDV

tHZ

-

0.75

-

0.75

-

0.75

ns

CK

Valid Data Output Window

tQH-tDQSQ

Data-out high-impedance window from CK, /CK

Data-out low-impedance window from CK, /CK

Input Setup Time (fast slew rate)

Input Hold Time (fast slew rate)

Input Setup Time (slow slew rate)

Input Hold Time (slow slew rate)

Input Pulse Width

-0.75

0.9

0.75

-0.75

0.9

0.75

-0.8

1.1

0.8

17

tLZ

0.75

0.8

tIS

-

2,3,5,6

2,4,5,6

6

tIH

0.9

1.1

tIS

1.0

1.1

tIH

1.0

1.1

tIPW

tDQSH

2.2

2.5

Write DQS High Level Width

0.35

-

0.35

-

0.35

Rev. 0.3/May. 02

11

HYMD116M645B(L)8-J/M/K/H/L

DDR266A

DDR266B

Max

DDR200

Parameter

Symbol

Unit

Note

Min

Max

Min

0.35

0.75

0.5

1.75

0.9

0.4

0

Min

Max

Write DQS Low Level Width

tDQSL

tDQSS

tDS

0.35

0.75

0.5

1.75

0.9

0.4

0

-

0.35

0.75

0.6

2

-

CK

ns

Clock to First Rising edge of DQS-In

Data-In Setup Time to DQS-In (DQ & DM)

Data-in Hold Time to DQS-In (DQ & DM)

DQ & DM Input Pulse Width

1.25

-

6,7,

11~13

tDH

-

ns

tDIPW

tRPRE

tRPST

tWPRES

tWPREH

tWPST

tMRD

ns

Read DQS Preamble Time

1.1

0.6

-

1.1

0.6

-

0.9

0.4

0

1.1

0.6

-

CK

us

Read DQS Postamble Time

Write DQS Preamble Setup Time

Write DQS Preamble Hold Time

Write DQS Postamble Time

0.25

0.4

2

-

0.25

0.4

2

-

0.25

0.4

2

-

0.6

-

0.6

-

0.6

-

Mode Register Set Delay

Exit Self Refresh to Any Execute Command

Average Periodic Refresh Interval

tXSC

200

-

200

-

200

-

8

tREFI

15.6

Rev. 0.3/May. 02

12

HYMD116M645B(L)8-J/M/K/H/L

Note :

1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3. For command/address input slew rate >=1.0V/ns

4. For command/address input slew rate >=0.5V/ns and <1.0V/ns

This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

Delta tIS

ps

Delta tIH

V/ns

0.5

ps

0

0.4

+50

0

0.3

+100

0

5. CK, /CK slew rates are >=1.0V/ns

6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester correlation.

7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of

tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to

n-channel variation of the output drivers.

¹¹.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

Delta tDS

Delta tDH

V/ns

0.5

ps

0

ps

0

0.4

+75

+150

+75

+150

0.3

12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF

+/-310mV for a duration of up to 2ns.

I/O Input Level

mV

Delta tDS

ps

Delta tDH

ps

+280

+50

13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS

slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns

and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.

(1/SlewRate1)-(1/SlewRate2)

Delta tDS

Delta tDH

ns/V

0

ps

0

ps

0

+/-0.25

+/- 0.5

+50

+100

+50

+100

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotonic.

Rev. 0.3/May. 02

13

HYMD116M645B(L)8-J/M/K/H/L

15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.

tCK is equal to the actual system clock cycle time.

Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,

tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)

Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock

16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be

tRAS - BL/2 x tCK

17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced

to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

Rev. 0.3/May. 02

14

HYMD116M645B(L)8-J/M/K/H/L

SIMPLIFIED COMMAND TRUTH TABLE

A10/

AP

ADDR

Command

CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

BA

Note

Extended Mode Register Set

Mode Register Set

Device Deselect

No Operation

H

X

L

OP code

1,2

H

L

X

H

L

X

H

X

H

X

1

Bank Active

L

RA

V

1

Read

L

H

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

1,3

1

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Read Burst Stop

Auto Refresh

H

L

1,4

1,5

1

X

V

H

L

H

X

H

L

H

L

H

L

H

X

H

X

H

X

H

X

V

X

1

Entry

L

1

Self Refresh

Exit

H

L

X

H

X

H

X

H

X

V

X

H

X

H

X

H

X

V

X

L

H

L

H

L

1

H

L

1

Entry

Precharge Power

Down Mode

H

L

Exit

H

L

Active Power

Down Mode

(Clock Suspend)

Entry

Exit

H

L

H

X

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note :

1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

Rev. 0.3/May. 02

15

HYMD116M645B(L)8-J/M/K/H/L

PACKAGE DIMENSIONS

Front

2.00 mm

Component

Keepout

Area

31.75 mm

20.00 mm

1

39

41

199

Back

Side

2.0 mm

1

39

41

1.9mm

MAX.

(Front)

Rev. 0.3/May. 02

16

SERIAL PRESENCE DETECT

SPD SPECIFICATION

(16Mx64 Unbuffered DDR SO-DIMM)

Rev. 0.3/May. 02

17

HYMD116M645B(L)8-J/M/K/H/L

Bin Sort :J(DDR333),M(DDR266(2-2-2),K(DDR266A@CL=2)

H(DDR266B@CL=2.5),L(DDR200@CL=2)

SERIAL PRESENCE DETECT

Function Supported

Hexa Value

Byte#

Function Description

Note

J

M

K

H

L

J

M

K

H

L

Number of Bytes written into serial memory at module

manufacturer

0

128 Bytes

80h

1

2

3

4

5

6

7

8

9

Total number of Bytes in SPD device

Fundamental memory type

Number of row address on this assembly

Number of column address on this assembly

Number of physical banks on DIMM

Module data width

Module data width (continued)

Module voltage Interface levels(VDDQ)

DDR SDRAM cycle time at CAS Latency =2.5(tCK)

256 Bytes

DDR SDRAM

08h

07h

0Ch

0Ah

01h

40h

00h

04h

12

10

1Bank

64 Bits

-

1

SSTL 2.5V

7.5ns 7.5ns 7.5ns

6.0ns

8.0ns

60h 75h 75h 75h 80h

2

10

11

12

13

14

DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.7ns

Module configuration type

Refresh rate and type

Primary DDR SDRAM width

Error checking DDR SDRAM data width

+/-0.75ns

Non-ECC

15.6us & Self refresh

+/-0.8ns 70h 75h 75h 75h 80h

00h

80h

08h

00h

x8

N/A

Minimum clock delay for back-to-back random column

15

1 CLK

01h

address(tCCD)

16

17

18

19

20

21

Burst lengths supported

Number of banks on each DDR SDRAM

CAS latency supported

CS latency

WE latency

DDR SDRAM module attributes

2,4,8

4 Banks

2, 2.5

0

0Eh

04h

0Ch

01h

02h

20h

1

Differential Clock Input

+/-0.2Voltage tolerance,

Concurrent Auto Precharge

tRAS Lock Out

C0h

22

DDR SDRAM device attributes : General

23

24

25

DDR SDRAM cycle time at CL=2.0(tCK)

DDR SDRAM access time from clock at CL=2.0(tAC) +/-0.7ns

DDR SDRAM cycle time at CL=1.5(tCK)

7.5ns

7.5ns 7.5ns 10ns

10ns

75h 75h 75h A0h A0h

+/-0.75ns

+/-0.8ns 70h 75h 75h 75h 80h

-

00h

26

DDR SDRAM access time from clock at CL=1.5(tAC)

27

28

29

30

Minimum row precharge time(tRP)

Minimum row activate to row active delay(tRRD)

Minimum RAS to CAS delay(tRCD)

Minimum active to precharge time(tRAS)

Module row density

18ns

12ns

18ns

42ns

15ns

45ns

20ns

15ns

20ns

45ns

128MB

20ns

15ns

20ns

45ns

20ns

15ns

20ns

50ns

48h 3Ch 50h 50h 50h

30h 3Ch 3Ch 3Ch 3Ch

48h 3Ch 50h 50h 50h

2Ah 2Dh 2Dh 2Dh 32h

20h

31

32

33

34

35

36~40

41

Command and address signal input setup time(tIS)

Command and address signal input hold time(tIH)

Data signal input setup time(tDS)

Data signal input hold time(tDH)

Reserved for VCSDRAM

0.75ns 0.9ns 0.9ns 0.9ns

0.45ns 0.5ns 0.5ns 0.5ns

Undefined

1.1ns

0.6ns

75h 90h 90h 90h B0h

45h 50h 50h 50h 60h

00h

Minimum active / auto-refresh Time (tRC)

60ns

72ns

12ns

60ns

75ns

12ns

65ns

75ns

12ns

65ns

75ns

12ns

70ns

80ns

3Ch 3Ch 41h 41h 46h

Minimum auto-refresh to active / auto-refresh com-

42

48h 4Bh 4Bh 4Bh 50h

mand period(tRFC)

43

44

45

46~61

62

Maximum cycle time (tCK max)

Maximum DQS-DQ skew time (tDQSQ)

Maximum read data hold skew factor (tQHS)

Superset Information (may be used in future)

SPD Revision code

12ns

0.6ns

30h 30h 30h 30h 30h

2Dh 32h 32h 32h 3Ch

0.45ns 0.5ns 0.5ns 0.5ns

0.55ns 0.75ns 0.75ns 0.75ns 0.75ns 55h 75h 75h 75h 75h

Undefined

Initial release

00h

63

Checksum for Bytes 0~62

-

DDh 67h 94h BFh 59h

64

65~71

Manufacturer JEDEC ID Code

------ Manufacturer JEDEC ID Code

Hynix JEDEC ID

-

ADh

00h

Rev. 0.3/May. 02

18

HYMD116M645B(L)8-J/M/K/H/L

SERIAL PRESENCE DETECT(continued)

Function Supported

Hexa Value

Byte#

Function Description

Note

J

M

K

H

L

J

M

K

H

L

Hynix(Korea Area)

HSA(United States Area)

HSE(Europe Area)

HSJ(Japan Area)

Singapore

0*h

1*h

2*h

3*h

4*h

5*h

72

Manufacturing location

6

Asia Area

73

74

75

76

77

78

79

80

81

82

83

84

85

Manufacture part number(Hynix Memory Module)

----- Manufacture part number(Hynix Memory Module)

Manufacture part number (DDR SDRAM)

Manufacture part number(Memory density)

Manufacture part number(Module Depth)

------- Manufacture part number(Module Depth)

Manufacture part number(Module type)

Manufacture part number(Data width)

-------Manufacture part number(Data width)

Manufacture part number(Refresh, # of Bank.)

Manufacture part number(Component Generation)

Manufacture part number(Component Configuration)

Manufacture part number(Hyphen)

H

Y

M

D

1

6

M

48h

59h

4Dh

44h

31h

36h

4Dh

36h

34h

35h

42h

38h

2Dh

6

4

5(4K refresh,4Bank)

B

8

‘-’

86

87

88~90

91

92

93

Manufacture part number(Minimum cycle time)

Manufacture part number(T.B.D)

Manufacture revision code(for Component)

Manufacture revision code (for PCB)

J

M

K

-

Blank

0

H

L

4Ah 4Dh 4Bh 48h 4Ch

20h

30h

-

Manufacturing date(Year)

-

3

4

5

94

95~98

Manufacturing date(Week)

Module serial number

-

99~127 Manufacturer specific data (may be used in future)

128~255 Open for customer use

Undefined

00h

Note :

1. The bank address is excluded

2. These value is based on the component specification

3. These bytes are programmed by code of date week & date year

4. These bytes apply to Hynix’s own Module Serial Number system

5. These bytes undefined and coded as ‘00h’

6. Refer to Hynix web site

Byte 85~86, Low power part

Function Supported

Hexa Value

Byte#

Function Description

Note

J

M

K

H

L

J

M

K

H

L

85

86

Manufacture part number(Low power part)

Manufacture part number(Component Configuration)

L

8

4Ch

38h

Rev. 0.3/May. 02

19


型号：	HYMD116M645B8-H
厂家：	HYNIX SEMICONDUCTOR
描述：	DDR DRAM Module, 16MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200 时钟动态存储器双倍数据速率内存集成电路
文件：	总19页 (文件大小：251K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYMD116M645B8-H [HYNIX]

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