HYMD216726AL6J-J [HYNIX]
Unbuffered DDR SO-DIMM; 无缓冲DDR SO -DIMM型号: | HYMD216726AL6J-J |
厂家: | HYNIX SEMICONDUCTOR |
描述: | Unbuffered DDR SO-DIMM |
文件: | 总16页 (文件大小:213K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16Mx72 bits
Unbuffered DDR SO-DIMM
HYMD216726A(L)6J-J
DESCRIPTION
Hynix HYMD216726A(L)6J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD216726A(L)6J-J series
consists of eighteen 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix
HYMD216726A(L)6J-J series provide a high performance 8-byte interface in 5.25" width form factor of industry stan-
dard. It is suitable for easy interchange and addition.
Hynix HYMD216726A(L)6J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera-
tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD216726A(L)6J-J series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
128MB (16M x72) Unbuffered DDR DIMM based on
16Mx16 DDR SDRAM
•
•
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
•
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
Data inputs on DQS centers when write (centered
DQ)
•
•
•
Error Check Correction (ECC) Capability
2.5V +/- 0.2V VDD and VDDQ Power supply
Data strobes synchronized with output data for read
and input data for write
•
•
Programmable CAS Latency 2 / 2.5 supported
All inputs and outputs are compatible with SSTL_2
interface
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
•
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz/166MHz
•
•
•
•
tRAS Lock-out function supported
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192refresh cycles / 64ms
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency
Interface
Form Pactor
VDD=2.5V
VDDQ=2.5V
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
HYMD216726A(L)6J-J
166MHz (*DDR333)
SSTL_2
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/Jul. 02
1
HYMD216726A(L)6J-J
PIN DESCRIPTION
Pin
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Pin
Pin Description
DQs Power Supply
Ground
CK0,/CK0,CK1,/CK1,CK2,/CK2
CS0, CS1
VDDQ
VSS
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A12
VREF
Reference Power Supply
Power Supply for SPD
VDDSPD
SA0~SA2
2
E PROM Address Inputs
2
BA0, BA1
Bank Address
SCL
SDA
E PROM Clock
2
DQ0~DQ63
Data Inputs/Outputs
E PROM Data I/O
CB0~CB7
DQS0~DQS7
DM0~8
Check Bit
WP
Write Protect Flag
VDD Identification Flag
Do not Use
Data Strobe Inputs/Outputs
Data-in Mask
VDDID
DU
VDD
Power Supply
NC
No Connection
PIN ASSIGNMENT
Pin
1
Name
VREF
DQ0
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Name
A5
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
Pin
93
94
95
96
97
98
99
Name
VSS
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Name
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
2
3
4
5
6
7
8
9
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
Vss
A1
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
WP
SDA
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ9
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
CB6
VDDQ
CB7
Key
key
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
A9
DQ18
A7
VDDQ
DQ19
DM4
DQ38
DQ39
VSS
SCL
DQ23
DQ44
VDDSPD
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.2/Jul. 02
2
HYMD216726A(L)6J-J
FUNCTIONAL BLOCK DIAGRAM
/CS0
DQS1
DQS5
/CS
/CS
LDQS
LDM
I/O0
LDQS
LDM
I/O0
DM1/DQS10
DM5/DQS14
DQ8
DQ40
DQ9
DQ10
DQ41
DQ42
I/O1
I/O1
I/O2
I/O2
DQ11
DQ12
DQ43
DQ44
I/O3
I/O4
I/O3
I/O4
D0
D2
DQ13
DQ14
DQ15
DQ45
DQ46
DQ47
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ32
DQ33
DQ34
DQ35
DQ36
I/O13
I/O14
I/O15
I/O13
I/O14
I/O15
DQ5
DQ6
DQ7
DQ37
DQ38
DQ39
DQS3
DM3/DQS12
DQS7
DM7/DQS16
/CS
/CS
LDQS
LDM
I/O0
I/O1
I/O2
LDQS
LDM
I/O0
I/O1
I/O2
DQ24
DQ56
DQ25
DQ26
DQ57
DQ58
DQ27
DQ28
DQ59
DQ60
I/O3
I/O4
I/O3
I/O4
D1
D3
DQ29
DQ30
DQ31
DQ61
DQ62
DQ63
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
DQS2
DQS6
DM2/DQS11
DM6/DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ48
DQ49
DQ50
DQ51
DQ52
I/O13
I/O14
I/O15
I/O13
I/O14
I/O15
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
Serial PD
VCC
100K
100K
SDA
SCL
/CS
LDQS
LDM
I/O0
I/O1
I/O2
WP
A0
A1
A2
NU
NU
NU
SA0 SA1 SA2
NU
NU
I/O3
I/O4
D4
NU
NU
NU
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
VDD SPD
SPD
*Clock Wiring
VDD /VDDQ
VREF
DO-D4
DO-D4
DO-D4
Clock Input
SDRAMs
DQS8
DM8/DQS17
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
1 SDRAMs
2 SDRAMs
2 SDRAMs
CB0
VSS
CB1
CB2
VDDID
Strap:see Note 4
*Wire per Clock Loading
Table/Wiring Diagrams
CB3
CB4
I/O13
I/O14
I/O15
CB5
CB6
CB7
Notes :
1. DQ-to-I/O wiring is shown as recommended but may
BA0-BA1
A0-A13
/RAS
BA0-BA1 : SDRAMs D0-D4
A0-A13 : SDRAMs D0-D4
/RAS : SDRAMs D0-D4
/CAS : SDRAMs D0-D4
CKE : SDRAMs D0-D4
/WE : SDRAMs D0-D4
be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
±
3. DQ, DQS, DM/DQS resistors : 22 Ohms
5%.
/CAS
4. VDDID strap connections
CKE0
/WE
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
≠
STRAP IN (VSS) : VDD V DDQ
±
5. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms 5%
Rev. 0.2/Jul. 02
3
HYMD216726A(L)6J-J
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
oC
Ambient Temperature
TA
0 ~ 70
oC
V
Storage Temperature
TSTG
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
VIN, VOUT
VDD
V
VDDQ
IOS
V
mA
W
PD
8
oC / Sec
Soldering Temperature Þ Time
TSOLDER
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDD
2.3
2.3
2.5
2.5
-
2.7
2.7
V
V
V
V
V
V
VDDQ
VIH
1
2
3
VREF + 0.15
-0.3
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
1.35
VIL
-
Termination Voltage
Reference Voltage
VTT
VREF - 0.04
1.15
VREF
1.25
VREF
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
VREF - 0.31
VDDQ + 0.6
0.7
1
2
Input Crossing Point Voltage, CK and /CK inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2/Jul. 02
4
HYMD216726A(L)6J-J
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
Termination Voltage
VDDQ x 0.5
V
V
VDDQ x 0.5
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
VREF + 0.31
V
VREF - 0.31
V
VREF
VTT
1.5
1
V
V
V
Input minimum Signal Slew Rate
V/ns
W
W
pF
Termination Resistor (RT)
50
Series Resistor (RS)
25
Output Load Capacitance for Access Time Measurement (CL)
30
Rev. 0.2/Jul. 02
5
HYMD216726A(L)6J-J
CAPACITANCE (TA=25oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Capacitance
A0 ~ A12, BA0, BA1
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
pF
pF
pF
pF
pF
pF
Input Capacitance
/RAS, /CAS, /WE
CKE0, CKE1
Input Capacitance
Input Capacitance
/CS0, /CS1
Input Capacitance
CK0, /CK0, CK1, /CK1
DM0 ~ DM8
Input Capacitance
Data Input / Output Capacitance
DQ0 ~ DQ63, DQS0 ~ DQS8
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
Ω
T
R =50
Output
Ω
Zo=50
VREF
L
C =30pF
Rev. 0.2/Jul. 02
6
HYMD216726A(L)6J-J
DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min.
Max
Unit
Note
Add, CMD, /CS, /CKE
CK, /CK
-10
10
Input Leakage
Current
ILI
uA
1
-12
12
Output Leakage Current
Output High Voltage
Output Low Voltage
ILO
VOH
VOL
-5
5
uA
V
2
VTT + 0.76
-
-
IOH = -15.2mA
IOL = +15.2mA
VTT - 0.76
V
Note :
1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 2.7V
Rev. 0.2/Jul. 02
7
HYMD216726A(L)6J-J
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
Parameter
Operating Current
Operating Current
Symbol
Test Condition
Unit
Note
-J
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
525
mA
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
IDD1
IDD2P
IDD2F
IDD3P
750
100
250
125
mA
mA
mA
mA
Precharge Power Down
Standby Current
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
Idle Standby Current
Active Power Down
Standby Current
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle
Active Standby Current
IDD3N
300
mA
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
Operating Current
Operating Current
IDD4R
IDD4W
IDD5
1450
1450
1150
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
mA
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
Auto Refresh Current
Self Refresh Current
Normal
15
mA
mA
CKE=<0.2V; External clock on; tCK
=tCK(min)
IDD6
IDD7
Low Power
7.5
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
1675
mA
Rev. 0.2/Jul. 02
8
HYMD216726A(L)6J-J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
DDR333
Parameter
Symbol
Unit
Note
Min
60
72
42
18
18
12
1
Max
Row Cycle Time
tRC
tRFC
tRAS
tRAP
tRCD
tRRD
tCCD
tRP
-
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
Auto Refresh Row Cycle Time
Row Active Time
-
70K
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
-
-
-
-
-
-
-
16
18
15
1
Write Recovery Time
tWR
tDRL
Last Data-In to Read Command
(tWR/tCK)
+
Auto Precharge Write Recovery + Precharge Time
tDAL
tCK
-
CK
15
(tRP/tCK)
CL = 2.5
CL = 2
6
12
12
ns
ns
System Clock Cycle Time
7.5
0.45
0.45
-0.7
-0.6
-
Clock High Level Width
tCH
tCL
0.55
0.55
0.7
CK
CK
ns
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tAC
tDQSCK
tDQSQ
0.6
ns
0.45
ns
tHP
Data-Out hold time from DQS
Clock Half Period
tQH
tHP
-
ns
ns
1, 10
-tQHS
min
(tCL,tCH)
-
1,9
10
Data Hold Skew Factor
tQHS
tDV
tHZ
tLZ
tIS
-
0.55
ns
ns
ns
ns
ns
ns
ns
ns
Valid Data Output Window
tQH-tDQSQ
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
-0.7
-0.7
0.75
0.75
0.8
0.7
17
0.7
17
-
-
-
-
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
Input Hold Time (fast slew rate)
tIH
Input Setup Time (slow slew rate)
tIS
Input Hold Time (slow slew rate)
tIH
0.8
Rev. 0.2/Jul. 02
9
HYMD216726A(L)6J-J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
DDR333
Parameter
Symbol
Unit
Note
Min
2.2
0.35
0.35
0.75
0.45
0.45
1.75
0.9
0.4
0
Max
Input Pulse Width
tIPW
tDQSH
tDQSL
tDQSS
tDS
ns
CK
CK
CK
ns
6
Write DQS High Level Width
-
Write DQS Low Level Width
-
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
1.25
-
-
6,7, 11~13
6,7, 11~13
tDH
ns
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
-
ns
Read DQS Preamble Time
1.1
0.6
-
CK
CK
CK
CK
CK
CK
CK
us
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
0.25
0.4
2
-
0.6
-
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
tXSC
200
-
-
8
tREFI
7.8
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
ps
Delta tIH
V/ns
0.5
ps
0
0
0.4
+50
0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
7.
8.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Rev. 0.2/Jul. 02
10
HYMD216726A(L)6J-J
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
0.5
ps
0
ps
0
0.4
+75
+150
+75
+150
0.3
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
0
ps
0
ps
0
+/-0.25
+/- 0.5
+50
+100
+50
+100
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transi tions through the DC region must be monotonic.
15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Rev. 0.2/Jul. 02
11
HYMD216726A(L)6J-J
SIMPLIFIED COMMAND TRUTH TABLE
A10/
ADDR
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
BA
Note
AP
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
H
H
X
X
L
L
H
L
L
L
L
L
L
L
L
OP code
OP code
1,2
1,2
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active
RA
V
V
1
1
Read
L
H
L
L
L
L
H
H
L
L
L
H
L
L
CA
CA
X
Read with Autoprecharge
Write
1,3
1
H
H
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
H
H
L
1,4
1,5
1
X
V
H
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
L
L
L
1
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry
Precharge
Power Down
H
L
Mode
Exit
H
H
L
Active Power
Down Mode
(Clock Suspend)
Entry
Exit
H
L
L
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.2/Jul. 02
12
HYMD216726A(L)6J-J
PACKAGE DIMENSIONS
Front
133.35
5.25
131.35
5.171
Side
128.95
5.077
3.18
.125MAX
31.75
1.250
(Front)
1.27+/-0.10
.050+/-.004
(2) 0
2.5
0.098
Rev. 0.2/Jul. 02
13
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(16Mx72 Unbuffered DDR DIMM)
Rev. 0.2/Jul. 02
14
HYMD216726A(L)6J-J
SERIAL PRESENCE DETECT
Bin Sort : J(DDR333@CL=2.5)
Byte#
Function Description
Function Supported
Hexa Value
Note
0
1
2
3
4
5
6
7
8
Number of Bytes written into serial memory at module manufacturer
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of physical banks on DIMM
Module data width
128 Bytes
256 Bytes
DDR SDRAM
80h
08h
07h
0Dh
09h
01h
48h
00h
04h
60h
70h
02h
82h
10h
08h
13
9
1Bank
72 Bits
-
SSTL 2.5V
6.0ns
+/-0.7ns
ECC
1
1
Module data width (continued)
Module voltage Interface levels(VDDQ)
DDR SDRAM cycle time at CAS Latency=2.5(tCK)
DDR SDRAM access time from clock at CL=2.5 (tAC)
Module configuration type
Refresh rate and type
Primary DDR SDRAM width
9
2
2
10
11
12
13
14
7.8us & Self refresh
x16
Error checking DDR SDRAM data width
x8
Minimum clock delay for back-to-back random column
15
1 CLK
01h
address(tCCD)
16
17
18
19
20
21
Burst lengths supported
Number of banks on each DDR SDRAM
CAS latency supported
CS latency
WE latency
DDR SDRAM module attributes
2,4,8
4 Banks
2, 2.5
0
0Eh
04h
0Ch
01h
02h
20h
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
22
DDR SDRAM device attributes : General
C0h
23
24
25
26
27
28
29
30
31
32
33
34
35
DDR SDRAM cycle time at CL=2.0(tCK)
DDR SDRAM access time from clock at CL=2.0(tAC)
DDR SDRAM cycle time at CL=1.5(tCK)
DDR SDRAM access time from clock at CL=1.5(tAC)
Minimum row precharge time(tRP)
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
7.5ns
+/-0.7ns
-
75h
70h
00h
00h
48h
30h
48h
2Ah
20h
75h
75h
45h
45h
00h
3Ch
2
2
2
2
-
18ns
12ns
18ns
42ns
128MB
0.75ns
0.75ns
0.45ns
0.45ns
Undefined
60ns
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41
Minimum active / auto-refresh time ( tRC)
Minimum auto-refresh to active/auto-refresh
42
72ns
48h
command period(tRFC)
43
44
45
Maximum cycle time (tCK max)
Maximim DQS-DQ skew time(tDQSQ)
Maximum read data hold skew factor(tQHS)
12ns
0.45ns
0.55ns
30h
2Dh
55h
00h
00h
F9h
ADh
00h
46~61 Superset information(may be used in future)
Undefined
Initial release
-
Hynix JEDEC ID
-
62
63
64
SPD Revision code
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
65~71 --------- Manufacturer JEDEC ID Code
Rev. 0.2/Jul. 02
15
HYMD216726A(L)6J-J
SERIAL PRESENCE DETECT
- continued -
Byte #
Function Description
Function Supported
Hexa Value
Note
Hynix(Korea Area)
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
0*h
1*h
2*h
3*h
4*h
5*h
72
Manufacturing location
6
Asia Area
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
Manufacture part number (DDR SDRAM)
Manufacture part number(Memory density)
Manufacture part number(Module Depth)
------- Manufacture part number(Module Depth)
Manufacture part number(Module type)
Manufacture part number(Data width)
-------Manufacture part number(Data width)
Manufacture part number(Refresh, # of Bank.)
Manufacture part number(Component Generation)
Manufacture part number(Component configuration)
Manufacture part number(Module Type)
H
Y
M
D
2
1
6
Blank
7
2
48h
59h
4Dh
44h
32h
31h
36h
20h
37h
32h
36h
41h
36h
4Ah
2Dh
4Ah
20h
-
6(8K refresh,4Bank)
A
6
J
‘-’
J
-
-
-
Manufacture part number(Hyphen)
Manufacture part number(Minimum cycle time)
89~90 Manufacture part number(T.B.D)
91
92
93
94
Manufacture revision code(for Component)
Manufacture revision code (for PCB)
Manufacturing date(Year)
-
-
-
-
-
3
3
4
5
5
Manufacturing date(Week)
95~98 Module serial number
99~127 Manufacturer specific data (may be used in future)
128~255 Open for customer use
-
-
Undefined
Undefined
00h
00h
Note :
1. The bank address is excluded
2. These value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number system
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix web site
Byte 85~86, Low power part
Function
Hexa
Value
Byte #
Function Description
Note
Supported
85
86
Manufacture part number(Low power part)
Manufacture part number(Component configuration)
L
6
4Ch
36h
Rev. 0.2/Jul. 02
16
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