HYMD216M726AL6-K [HYNIX]
Unbuffered DDR SO-DIMM; 无缓冲DDR SO -DIMM
| 型号： | HYMD216M726AL6-K |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Unbuffered DDR SO-DIMM |
| 文件： | 总19页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16Mx72 bits
Unbuffered DDR SO-DIMM
HYMD216M726A(L)6-J/M/K/H/L
DESCRIPTION
Hynix HYMD216M726A(L)6-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Out-
line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix
HYMD216M726A(L)6-J/M/K/H/L series consists of five 16Mx16 DDR SDRAM in 400mil TSOP II packages on a
200pin glass-epoxy substrate. Hynix HYMD216M726A(L)6-J/M/K/H/L series provide a high performance 8-byte inter-
face in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD216M726A(L)6-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchro-
nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD216M726A(L)6-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
128MB (16M x72) Unbuffered DDR SO-DIMM ECC-
based on 16Mx16 DDR SDRAM
•
•
Data inputs on DQS centers when write (centered
DQ)
•
JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
Data strobes synchronized with output data for read
and input data for write
•
•
2.5V +/- 0.2V VDD and VDDQ Power supply
•
•
Programmable CAS Latency 2 / 2.5 supported
All inputs and outputs are compatible with SSTL_2
interface
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
•
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz/166MHz
•
•
•
•
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency
Interface
Form Factor
HYMD216M726A(L)6-J
HYMD216M726A(L)6-M
HYMD216M726A(L)6-K
HYMD216M726A(L)6-H
HYMD216M726A(L)6-L
166MHz (*DDR333)
133MHz (*DDR266:2-2-2)
133MHz(*DDR266A)
133MHz(*DDR266B)
100MHz(*DDR200)
VDD=2.5V
VDDQ=2.5V
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 1mm
SSTL_2
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3/Oct. 02
1
HYMD216M726A(L)6-J/M/K/H/L
PIN DESCRIPTION
Pin
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Pin
Pin Description
CK0, /CK0, CK1, /CK1
CS0
VDDQ
DQs Power Supply
Ground
VSS
CKE0
VREF
Reference Power Supply
Power Supply for SPD
/RAS, /CAS, /WE
A0 ~ A12
VDDSPD
SA0~SA2
2
E PROM Address Inputs
2
BA0, BA1
Bank Address
SCL
SDA
E PROM Clock
2
DQ0~DQ63
Data Inputs/Outputs
E PROM Data I/O
DQS0~DQS8
DM0~DM8
VDD
Data Strobe Inputs/Outputs
Data-in Mask
VDDID
DU
VDD Identification Flag
Do not Use
Power Supply
NC
No Connection
PIN ASSIGNMENT
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
A9
VREF
2
VREF
51
VSS
52
VSS
101
102
A8
151
DQ42
152
DQ46
3
VSS
DQ0
4
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
VSS
A7
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
VSS
A6
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
DQ43
VDD
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
DQ47
VDD
/CK1
CK1
5
6
7
DQ1
8
A5
A4
VDD
9
VDD
DQS0
DQ2
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
A3
A2
VSS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
A1
A0
VSS
VSS
VDD
A10/AP
BA0
VDD
BA1
/RAS
/CAS
NC
DQ48
DQ49
VDD
DQ52
DQ53
VDD
DM6
DQ54
VSS
VSS
DQ3
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ8
/WE
DQS6
DQ50
VSS
VDD
DQ9
/CS0
DU
DU
DQS1
VSS
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ51
DQ56
VDD
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ10
DQ11
VDD
CK0
DQ14
DQ15
VDD
VDD
VSS
DQ57
DQS7
VSS
/CK0
VSS
VSS
NC
VSS
VSS
VDD
VDD
CKE0
DU
DQ58
DQ59
VDD
DQ62
DQ63
VDD
SA0
VSS
DQ16
DQ17
VDD
DQS2
DQ18
DQ20
DQ21
VDD
DM2
DQ22
NC
VDD
NC
SDA
SCL
SA1
NC
197 VDDSPD 198
199 VDDID 200
SA2
A12
A11
DU
Rev. 0.3/Oct. 02
2
HYMD216M726A(L)6-J/M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
/CS0
/CS0
/CS
/CS
/CS
DQS1
DQS1
LDQS
DQS5
DQS5
LDQS
LDQS
VDDQ
VDDQ
DM1
DM1
LDM
DM5
DM5
LDM
LDM
DQ8
DQ9
DQ9
DQ8
D0
DQ40
DQ40
D2
D4
I/O 6
I/O 6
I/O 6
DQ41
DQ41
I/O 4
I/O 4
I/O 4
DQ10
DQ10
DQ42
DQ42
I/O 1
I/O 1
I/O 1
DQ11
DQ11
DQ43
DQ43
I/O 3
I/O 3
I/O 3
DQ12
DQ12
DQ44
DQ44
I/O 2
I/O 2
I/O 2
DQ13
DQ13
DQ45
DQ45
I/O 0
I/O 0
I/O 0
DQ14
DQ14
DQ46
DQ46
I/O 5
I/O 5
I/O 5
DQ15
DQ15
DQ47
DQ47
I/O 7
I/O 7
I/O 7
DQS0
DQS0
DQS4
DQS4
UDQS
DQS8
DQS8
UDQS
UDQS
DM0
DM0
DM4
DM4
UDM
DM8
DM8
UDM
UDM
DQ0
DQ0
DQ32
DQ32
CB0
CB0
I/O 8
I/O 8
I/O 8
DQ1
DQ1
DQ33
DQ33
CB1
CB1
I/O 10
I/O 10
I/O 10
DQ2
DQ2
DQ34
DQ34
CB2
CB2
I/O 15
I/O 15
I/O 15
DQ3
DQ3
DQ35
DQ35
CB3
CB3
I/O 13
I/O 13
I/O 13
DQ4
DQ4
DQ36
DQ36
CB4
CB4
I/O 12
I/O 12
I/O 12
DQ5
DQ5
DQ37
DQ37
CB5
CB5
I/O 14
I/O 14
I/O 14
DQ6
DQ6
DQ38
DQ38
CB6
CB6
I/O 11
I/O 11
I/O 11
DQ7
DQ7
DQ39
DQ39
CB7
CB7
I/O 9
I/O 9
I/O 9
/CS
/CS
DQSS3
DQS3
LDQS
DQS7
DQS7
LDQS
DDM3
DM3
LDM
DM7
DM7
LDM
D
D
Q
Q
2
2
4
4
D1
DQ56
DQ56
D3
I/O 6
I/O 6
DQ225
DQ25
DQ57
DQ57
I/O 4
I/O 4
DQ226
DQ26
DQ58
DQ58
I/O 1
I/O 1
DQ227
DQ27
DQ59
DQ59
I/O 3
I/O 3
DQ228
DQ28
DQ60
DQ60
I/O 2
I/O 2
DQ229
DQ29
DQ61
DQ61
I/O 0
I/O 0
DQ330
DQ30
DQ62
DQ62
I/O 5
I/O 5
DQ331
DQ31
DQ63
DQ63
I/O 7
I/O 7
DQSS2
DQS2
DM2
DDM2
U
D
Q
S
DQS6
DQS6
DM6
DM6
UDQS
UDM
I/O 8
DQ116
DQ16
DQ48
DQ48
DQ117
DQ17
DQ49
DQ49
I/O 10
I/O 10
DQ118
DQ18
DQ50
DQ50
I/O 15
I/O 15
DQ119
DQ19
DQ51
DQ51
I/O 13
I/O 13
DQ220
DQ20
DQ52
DQ52
I/O 12
I/O 12
DQ221
DQ21
DQ53
DQ53
I/O 14
I/O 14
DQ222
DQ22
DQ54
DQ54
I/O 11
I/O 11
DQ223
DQ23
DQ55
DQ55
I/O 9
I/O 9
Serial PD
Serial PD
.
.
Q
Q
SSPD
SPD
VVDDDSSPPD
VDDSPD
.
.
=
=
SCL
SCL
D0 –– D4
D0 – D4
V
V
D
D
D
D
/
/
V
V
D
D
D
D
=
=
SDA
SDA
WP
WP
.
.
=
=
D
D
D0 –– D4
D0 – D4
VREEF
VREF
A
0
A
1
A2
=
. . .. .
. . . .
D
D
SStrrap::see
Strap:see
VVSS
VSS
00 – D4
0 – D4
S
S
A
A
0
0
S
S
A
A
1
1
SA2
SA2
....
..
V
V
D
D
D
D
I
I
Notee 4
Note 4
B
A
0
-
-
B
B
A
A
1
1
BA0-BA1 : SDRAMs D0 – D4
BA0-BA1 : SDRAMs D0 – D4
NNoottes:
Notes:
DQ wiriinngg mmaayy difffeer ffrrom that dessccrribeed iin thhiis
DQ wiring may differ from that described in this
drawing; however DQ/DM/DQS relationships
drraawiinngg; hhooweveerr DDQQ//DDMM/DDQQS reellaattionnshhipps
are maintained as shown.
arree mmaiinntained as sshhownn.
A0
-
A
A
1
1
2
2
A0 - A12 : SDRAMs D0 – D4
A0 - A12 : SDRAMs D0 – D4
R
R
A
A
S
S
/RAS : SDRAMs D0 – D4
/RAS : SDRAMs D0 – D4
VDDDDIID ssttrap conneccttionns
VDDID strap connections
/
C
C
A
A
S
S
/CAS : SDRAMs D0 – D4
/CAS : SDRAMs D0 – D4
(forr mmemoryy deevviicce VVDDD,, VDDDDQQ)) :
(for memory device VDD, VDDQ) :
C
K
K
E
E
0
0
CKE : SDRAMs D0 – D4
CKE : SDRAMs D0 – D4
Sttrap oout :(oppenn) :: VVDDD=VVDDQ
Strap out :(open) : VDD=VDDQ
/
/
W
W
E
E
/WE : SDRAMs D0 – D4
/WE : SDRAMs D0 – D4
Sttrraap IInn (Vss) : VDDD == VDDDQ
Strap In (Vss) : VDD = VDDQ
Rev. 0.3/Oct. 02
3
HYMD216M726A(L)6-J/M/K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
oC
Operating Temperature (Ambient)
TA
0 ~ 70
oC
V
Storage Temperature
TSTG
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
VIN, VOUT
VDD
V
VDDQ
IOS
V
mA
W
PD
1.0 x # of Components
oC / Sec
Soldering Temperature ⋅ Time
TSOLDER
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDD
2.3
2.3
2.5
2.5
-
2.7
2.7
V
V
V
V
V
V
VDDQ
VIH
1
2
3
VREF + 0.15
-0.3
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
1.35
VIL
-
Termination Voltage
Reference Voltage
VTT
VREF - 0.04
1.15
VREF
1.25
VREF
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
VREF - 0.31
VDDQ + 0.6
0.7
1
2
Input Crossing Point Voltage, CK and /CK inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.3/Oct. 02
4
HYMD216M726A(L)6-J/M/K/H/L
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
Termination Voltage
VDDQ x 0.5
V
V
VDDQ x 0.5
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
VREF + 0.31
V
VREF - 0.31
V
VREF
VTT
1.5
1
V
V
V
Input minimum Signal Slew Rate
V/ns
Ω
Termination Resistor (RT)
50
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Rev. 0.3/Oct. 02
5
HYMD216M726A(L)6-J/M/K/H/L
CAPACITANCE (TA=25oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Capacitance
A0 ~ A12, BA0, BA1
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
CIO2
32
32
32
32
17
7
43
43
43
43
21
9
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance
/RAS, /CAS, /WE
CKE0, CKE1
Input Capacitance
Input Capacitance
/CS0, /CS1
Input Capacitance
CK0, /CK0, CK1, /CK1
DM0 ~ DM8
Input Capacitance
Data Input / Output Capacitance
Data Input / Output Capacitance
DQ0 ~ DQ63, DQS0 ~ DQS8
CB0 ~ CB7
7
9
7
9
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
Ω
RT=50
Output
Ω
Zo=50
VREF
CL=30pF
Rev. 0.3/Oct. 02
6
HYMD216M726A(L)6-J/M/K/H/L
DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min.
Max
Unit
Note
Add, CMD, /CS, /CKE
-10
10
Input Leakage
Current
CK0, /CK0, CK1, /CK1
CK2, /CK2
ILI
-8
8
uA
1
0
0
Output Leakage Current
Output High Voltage
Output Low Voltage
ILO
VOH
VOL
-5
5
uA
V
2
VTT + 0.76
-
-
IOH = -15.2mA
IOL = +15.2mA
VTT - 0.76
V
Note :
1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 2.7V
Rev. 0.3/Oct. 02
7
HYMD216M726A(L)6-J/M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
-K
Parameter
Symbol
Test Condition
Unit Note
-J
-M
-H
-L
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
control inputs changing once per clock cycle
Operating Current
IDD0
525
525
475
475
450
mA
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
clock cycle
Operating Current
IDD1
IDD2P
IDD2F
IDD3P
750
250
750
250
650
100
200
650
200
600
175
mA
mA
mA
Precharge Power
Down Standby Current
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min);
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF for
DQ, DQS and DM
Idle Standby Current
Active Power Down
Standby Current
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
125
mA
mA
/CS>=Vih(min); All banks idle;
IDD2Q CKE>=Vih(min); Addresses and other control
inputs stable, Vin=Vref for DQ, DQS and DM
Idle Quiet Standby
Current
TBD
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
Active Standby
Current
300
300
250
250
250
mA
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
Operating Current
Operating Current
IDD4R
1450 1450 1250 1250 950
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
IDD4W once per clock cycle; tCK=tCK(min); DQ, DM 1450 1450 1250 1250 950
mA
and DQS inputs changing twice per clock
cycle
tRC=tRFC(min) - 8*tCK for DDR200 at
Auto Refresh Current
Self Refresh Current
IDD5
100Mhz, 10*tCK for DDR266A & DDR266B at 1150 1150 1050 1050 975
133Mhz; distributed refresh
Normal
15
mA
mA
CKE=<0.2V; External clock on;
tCK =tCK(min)
IDD6
IDD7
Low Power
7.5
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
1675 1675 1625 1625 1450 mA
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
tRCD=3, IOUT=0 mA, 100% DQ, DM and
DQS inputs changing twice per clock cycle;
100% addresses changing once per clock
cycle
Random Read Current
IDD7A
TBD
mA
Rev. 0.3/Oct. 02
8
HYMD216M726A(L)6-J/M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
<DDR333, DDR266(2-2-2)>
DDR333
DDR266(2-2-2)
Parameter
Symbol
Unit
Note
Min
Max
Min
60
75
45
15
15
15
1
Max
Row Cycle Time
tRC
tRFC
tRAS
tRAP
tRCD
tRRD
tCCD
tRP
60
72
42
18
18
12
1
-
-
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
Auto Refresh Row Cycle Time
Row Active Time
-
-
70K
120K
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
18
15
1
15
15
1
Write Recovery Time
tWR
tWTR
Write to Read Command Delay
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Auto Precharge Write Recovery + Precharge Time
tDAL
tCK
-
-
CK
15
CL = 2.5
System Clock Cycle Time
CL = 2
6
12
12
7.5
7.5
12
ns
ns
7.5
0.45
0.45
-0.7
-0.6
-
12
Clock High Level Width
tCH
tCL
0.55
0.55
0.7
0.45
0.45
-0.75
-0.75
-
0.55
0.55
0.75
0.75
0.5
CK
CK
ns
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tAC
tDQSCK
tDQSQ
0.6
ns
0.45
ns
tHP
-tQHS
tHP
-tQHS
Data-Out hold time from DQS
Clock Half Period
tQH
tHP
-
-
ns
ns
1, 10
min
(tCL,tCH)
min
(tCL,tCH)
-
-
1,9
10
Data Hold Skew Factor
tQHS
tDV
tHZ
tLZ
-
0.55
-
0.75
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
Valid Data Output Window
tQH-tDQSQ
tQH-tDQSQ
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Input Pulse Width
-0.7
-0.7
0.75
0.75
0.8
0.7
-0.75
-0.75
0.9
0.75
17
17
0.7
0.75
tIS
-
-
-
-
-
-
-
-
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
6
tIH
0.9
tIS
1.0
tIH
0.8
1.0
tIPW
tDQSH
2.2
2.2
Write DQS High Level Width
0.35
-
0.35
-
Rev. 0.3/Oct. 02
9
HYMD216M726A(L)6-J/M/K/H/L
- continued -
DDR333
DDR266(2-2-2)
Parameter
Symbol
Unit
Note
Min
Max
Min
0.35
0.72
0.5
0.5
1.75
0.9
0.4
0
Max
Write DQS Low Level Width
tDQSL
tDQSS
tDS
0.35
0.75
0.45
0.45
1.75
0.9
0.4
0
-
-
CK
CK
ns
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
1.25
1.28
-
-
6,7, 11~13
6,7, 11~13
tDH
-
-
ns
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
-
1.1
0.6
-
-
1.1
0.6
-
ns
Read DQS Preamble Time
CK
CK
CK
CK
CK
CK
CK
us
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
0.25
0.4
2
-
0.25
0.4
2
-
0.6
-
0.6
-
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
tXSC
200
-
-
200
-
-
8
tREFI
15.6
15.6
Rev. 0.3/Oct. 02
10
HYMD216M726A(L)6-J/M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
<DDR266A/B, DDR200>
DDR266A
DDR266B
Min Max
DDR200
Parameter
Symbol
Unit
Note
Min
Max
Min
70
80
50
20
20
15
1
Max
Row Cycle Time
tRC
tRFC
tRAS
tRAP
tRCD
tRRD
tCCD
tRP
65
75
45
20
20
15
1
-
65
75
45
20
20
15
1
-
-
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
Auto Refresh Row Cycle Time
Row Active Time
-
-
-
120K
120K
120k
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
20
15
1
20
15
1
20
15
1
Write Recovery Time
tWR
tWTR
Write to Read Command Delay
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Auto Precharge Write Recovery + Precharge
Time
tDAL
tCK
-
-
-
CK
15
CL = 2.5
System Clock Cycle Time
CL = 2
7.5
7.5
12
7.5
10
12
8.0
10
12
12
ns
ns
12
12
Clock High Level Width
tCH
tCL
0.45
0.45
-0.75
-0.75
-
0.55
0.55
0.75
0.75
0.5
0.45
0.45
-0.75
-0.75
-
0.55
0.55
0.75
0.75
0.5
0.45
0.45
-0.8
-0.8
-
0.55
0.55
0.8
CK
CK
ns
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tAC
tDQSCK
tDQSQ
0.8
ns
0.6
ns
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Data-Out hold time from DQS
Clock Half Period
tQH
tHP
-
-
-
ns
ns
1, 10
min
(tCL,tCH
)
min
(tCL,tCH
)
min
(tCL,tCH
)
-
-
-
1,9
10
Data Hold Skew Factor
tQHS
tDV
tHZ
tLZ
-
0.75
-
0.75
-
0.75
ns
ns
ns
ns
ns
ns
ns
ns
ns
Valid Data Output Window
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Input Pulse Width
-0.75
-0.75
0.9
0.75
-0.75
-0.75
0.9
0.75
-0.8
-0.8
1.1
1.1
1.1
1.1
2.5
0.8
17
17
0.75
0.75
0.8
tIS
-
-
-
-
-
-
-
-
-
-
-
-
-
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
6
tIH
0.9
0.9
tIS
1.0
1.0
tIH
1.0
1.0
tIPW
2.2
2.2
Rev. 0.3/Oct. 02
11
HYMD216M726A(L)6-J/M/K/H/L
- continued -
DDR266A
DDR266B
DDR200
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Min
Max
Write DQS High Level Width
tDQSH
tDQSL
tDQSS
tDS
0.35
0.35
0.75
0.45
0.45
1.75
0.9
0.4
0
-
0.35
0.35
0.75
0.45
0.45
1.75
0.9
0.4
0
-
0.35
0.35
0.72
0.5
0.5
1.75
0.9
0.4
0
-
CK
CK
CK
ns
Write DQS Low Level Width
-
-
-
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
1.25
1.25
1.28
-
-
-
6,7,
11~13
tDH
-
-
-
ns
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
-
1.1
0.6
-
-
1.1
0.6
-
-
1.1
0.6
-
ns
Read DQS Preamble Time
CK
CK
CK
CK
CK
CK
CK
us
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
0.25
0.4
2
-
0.25
0.4
2
-
0.25
0.4
2
-
0.6
-
0.6
-
0.6
-
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
tXSC
200
-
-
200
-
-
200
-
-
8
tREFI
15.6
15.6
15.6
Rev. 0.3/Oct. 02
12
HYMD216M726A(L)6-J/M/K/H/L
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
ps
Delta tIH
V/ns
0.5
ps
0
0
0.4
+50
0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
7.
8.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
0.5
ps
0
ps
0
0.4
+75
+150
+75
+150
0.3
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.
I/O Input Level
mV
Delta tDS
ps
Delta tDH
ps
+280
+50
+50
13.
I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
0
ps
0
ps
0
+/-0.25
+/- 0.5
+50
+100
+50
+100
Rev. 0.3/Oct. 02
13
HYMD216M726A(L)6-J/M/K/H/L
14.
15.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transi tions through the DC region must be monotonic.
tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock
16.
17.
For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Rev. 0.3/Oct. 02
14
HYMD216M726A(L)6-J/M/K/H/L
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
ADDR
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
BA
Note
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
H
H
X
X
L
L
H
L
L
L
L
L
L
L
L
OP code
OP code
1,2
1,2
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active
RA
V
V
1
1
Read
L
H
L
L
L
L
H
H
L
L
L
H
L
L
CA
CA
X
Read with Autoprecharge
Write
1,3
1
H
H
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
H
H
L
1,4
1,5
1
X
V
H
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
L
L
L
1
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry
Precharge
Power Down
H
L
Mode
Exit
H
H
L
Active Power
Down Mode
(Clock Suspend)
Entry
Exit
H
L
L
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.3/Oct. 02
15
HYMD216M726A(L)6-J/M/K/H/L
PACKAGE DIMENSIONS
Front
67.60 mm
2.00 mm
Component
Keepout
Area
2.00 mm
31.75 mm
20.00 mm
1
39
41
199
Side
Back
3.8mm
2.0 mm
2.0 mm
MAX.
2
40
42
200
(Front)
1.1mm
MAX.
Rev. 0.3/Oct. 02
16
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(16Mx72 Unbuffered DDR SO-DIMM)
Rev. 0.3/Oct. 02
17
HYMD216M726A(L)6-J/M/K/H/L
SERIAL PRESENCE DETECT
Bin Sort :J(DDR333),M(DDR266(2-2-2)),K(DDR266A@CL=2)
H(DDR266B@CL=2.5),L(DDR200@CL=2)
Function Supported
Hexa Value
K
Byte#
Function Description
Note
J
M
K
H
L
J
M
H
L
0
Number of Bytes written into serial memory at module
manufacturer
128 Bytes
80h
1
2
Total number of Bytes in SPD device
Fundamental memory type
256 Bytes
08h
07h
0Dh
09h
01h
48h
00h
04h
DDR SDRAM
3
Number of row address on this assembly
Number of column address on this assembly
Number of physical banks on DIMM
Module data width
13
9
1
1
4
5
1Bank
72 Bits
-
6
7
Module data width (continued)
8
Module voltage Interface levels(VDDQ)
DDR SDRAM cycle time at CAS Latency=2.5(tCK)
SSTL 2.5V
9
6.0ns
7.5ns 7.5ns 7.5ns
8.0ns
60h
75h 75h 75h
80h
80h
2
2
10
11
12
13
14
15
DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.7ns
Module configuration type
+/-0.75ns
+/-0.8ns 70h
75h 75h 75h
ECC
02h
82h
10h
08h
Refresh rate and type
7.8us & Self refresh
Primary DDR SDRAM width
x16
x8
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random col-
umn address(tCCD)
1 CLK
01h
16
17
18
19
20
21
Burst lengths supported
Number of banks on each DDR SDRAM
CAS latency supported
CS latency
2,4,8
0Eh
04h
0Ch
01h
02h
20h
4 Banks
2, 2.5
0
WE latency
1
DDR SDRAM module attributes
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
22
DDR SDRAM device attributes : General
C0h
23
24
25
26
27
28
29
30
31
32
33
34
35
DDR SDRAM cycle time at CL=2.0(tCK)
7.5ns
7.5ns 7.5ns 10ns
+/-0.75ns
10ns
75h
75h 75h A0h A0h
2
2
2
2
DDR SDRAM access time from clock at CL=2.0(tAC) +/-0.7ns
DDR SDRAM cycle time at CL=1.5(tCK)
+/-0.8ns 70h
75h 75h 75h
80h
-
00h
00h
DDR SDRAM access time from clock at CL=1.5(tAC)
-
Minimum row precharge time(tRP)
18ns
12ns
18ns
42ns
15ns 20ns 20ns
15ns 15ns 15ns
15ns 20ns 20ns
45ns 45ns 45ns
128MB
20ns
15ns
20ns
50ns
48h 3Ch 50h 50h
50h
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
30h 3Ch 3Ch 3Ch 3Ch
48h 3Ch 50h 50h 50h
2Ah 2Dh 2Dh 2Dh 32h
20h
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
0.75ns 0.9ns 0.9ns 0.9ns
0.75ns 0.9ns 0.9ns 0.9ns
0.45ns 0.5ns 0.5ns 0.5ns
0.45ns 0.5ns 0.5ns 0.5ns
Undefined
1.1ns
1.1ns
0.6ns
0.6ns
75h
75h
45h
45h
90h 90h 90h B0h
90h 90h 90h B0h
50h 50h 50h
50h 50h 50h
00h
60h
60h
Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41
Minimum active / auto-refresh time ( tRC)
60ns
72ns
12ns
60ns 65ns 65ns
75ns 75ns 75ns
12ns 12ns 12ns
70ns
80ns
3Ch 3Ch 41h 41h
46h
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
42
48h 4Bh 4Bh 4Bh 50h
43
44
45
Maximum cycle time (tCK max)
12ns
30h
30h 30h 30h
30h
Maximim DQS-DQ skew time(tDQSQ)
Maximum read data hold skew factor(tQHS)
0.45ns 0.5ns 0.5ns 0.5ns
0.6ns
2Dh 32h 32h 32h 3Ch
0.55ns 0.75ns 0.75ns 0.75ns 0.75ns
55h
75h 75h 75h
75h
46~61 Superset information(may be used in future)
Undefined
Initial release
-
00h
00h
62
63
SPD Revision code
Checksum for Bytes 0~62
F9h 83h B0h DBh 75h
Rev. 0.3/Oct. 02
18
HYMD216M726A(L)6-J/M/K/H/L
SERIAL PRESENCE DETECT
- continued -
Function Supported
Hexa Value
K
Byte #
Function Description
Manufacturer JEDEC ID Code
Note
J
M
K
H
L
J
M
H
L
64
Hynix JEDEC ID
-
ADh
00h
65~71 --------- Manufacturer JEDEC ID Code
Hynix(Korea Area)
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
0*h
1*h
2*h
3*h
4*h
5*h
72
Manufacturing location
6
Asia Area
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
Manufacture part number (DDR SDRAM)
H
48h
59h
4Dh
44h
32h
31h
36h
4Dh
37h
32h
36h
41h
36h
2Dh
Y
M
D
Manufacture part number(Memory density)
Manufacture part number(Module Depth)
2
1
------- Manufacture part number(Module Depth)
Manufacture part number(Module type)
6
M
Manufacture part number(Data width)
7
-------Manufacture part number(Data width)
Manufacture part number(Refresh, # of Bank.)
Manufacture part number(Component Generation)
Manufacture part number(Component configuration)
Manufacture part number(Hyphen)
2
6(8K refresh,4Bank)
A
6
‘-’
Manufacture part number(Minimum cycle time)
J
M
K
H
L
4Ah 4Dh 4Bh 48h 4Ch
88~90 Manufacture part number(T.B.D)
Blank
20h
91
92
93
94
Manufacture revision code(for Component)
Manufacture revision code (for PCB)
Manufacturing date(Year)
-
-
-
-
-
-
-
3
3
4
5
5
Manufacturing date(Week)
-
95~98 Module serial number
-
-
99~127 Manufacturer specific data (may be used in future)
128~255 Open for customer use
Undefined
Undefined
00h
00h
Note :
1. The bank address is excluded
2. These value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number system
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix web site
Byte 85~86, Low power part
Function Supported
Hexa Value
Byte #
Function Description
Note
J
M
K
H
L
J
M
K
H
L
85
86
Manufacture part number(Low power part)
Manufacture part number(Component configuration)
L
6
4Ch
36h
Rev. 0.3/Oct. 02
19
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