HYMD532M646L6-H [HYNIX]
DDR DRAM Module, 32MX64, 0.75ns, CMOS, 67.60 X 31.75 X 3.80 MM, SODIMM-200;
| 型号： | HYMD532M646L6-H |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM Module, 32MX64, 0.75ns, CMOS, 67.60 X 31.75 X 3.80 MM, SODIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总16页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32Mx64 bits
Unbuffered DDR SO-DIMM
HYMD532M646(L)6-K/H/L
DESCRIPTION
Preliminary
Hynix HYMD532M646(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline
Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memoryarrays. Hynix
HYMD532M646(L)6-K/H/L series consists of four 32Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin
glass-epoxy substrate. Hynix HYMD532M646(L)6-K/H/L series provide a high performance 8-byte interface in
67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD532M646(L)6-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper-
ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD532M646(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
256MB (32M x 64) Unbuffered DDR SO-DIMM
based on 32Mx16 DDR SDRAM
•
•
Data inputs on DQS centers when write (centered
DQ)
•
JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
Data strobes synchronized with output data for read
and input data for write
•
•
2.5V +/- 0.2V VDD and VDDQ Power supply
•
•
Programmable CAS Latency 1.5 / 2 / 2.5 supported
All inputs and outputs are compatible with SSTL_2
interface
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
•
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
•
•
•
•
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency
Interface
Form Pactor
HYMD532M646(L)6-K
HYMD532M646(L)6-H
HYMD532M646(L)6-L
133MHz(*DDR266A)
133MHz(*DDR266B)
125MHz(*DDR200)
VDD=2.5V
VDDQ=2.5V
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 3.8mm
SSTL_2
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/May. 02
1
HYMD532M646(L)6-K/H/L
PIN DESCRIPTION
Pin
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Pin
Pin Description
DQs Power Supply
Ground
CK0, /CK0, CK1, /CK1
CS0
VDDQ
VSS
CKE0
VREF
Reference Power Supply
Power Supply for SPD
/RAS, /CAS, /WE
A0 ~ A12
VDDSPD
SA0~SA2
2
E PROM Address Inputs
2
BA0, BA1
Bank Address
SCL
SDA
E PROM Clock
2
DQ0~DQ63
Data Inputs/Outputs
E PROM Data I/O
DQS0~DQS7
DM0~DM7
VDD
Data Strobe Inputs/Outputs
Data-in Mask
VDDID
DU
VDD Identification Flag
Do not Use
Power Supply
NC
No Connection
PIN ASSIGNMENT
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
A9
VREF
2
VREF
51
VSS
52
VSS
101
102
A8
151
DQ42
152
DQ46
3
5
7
9
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
4
6
8
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
NC
NC
VSS
NC
NC
VDD
NC
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
NC
NC
VSS
NC
NC
VDD
NC
103
105
107
109
111
113
VSS
A7
A5
A3
A1
104
106
108
110
112
114
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
NC
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
DQ47
VDD
/CK1
CK1
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VSS
VDD
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
115 A10/AP 116
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
BA0
/WE
/CS0
DU
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
DU
VSS
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ14
DQ15
VDD
VDD
VSS
DU
VSS
NC
NC
VDD
NC
DU
/CK0
VSS
VSS
VSS
VDD
VDD
CKE0
DU
DQ58
DQ59
VDD
SDA
SCL
VSS
DQ16
DQ17
VDD
DQS2
DQ18
DQ20
DQ21
VDD
DM2
DQ22
NC
A12
197 VDDSPD 198
199 VDDID 200
A11
DU
Rev. 0.1/May. 02
2
HYMD532M646(L)6-K/H/L
FUNCTIONAL BLOCK DIAGRAM
/CS0
/CS
/CS
DQS1
DM1
LDQS
LDM
DQS5
DM5
LDQS
LDM
DQ8
D0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D2
I/O 6
I/O 6
DQ9
I/O 4
I/O 4
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 1
I/O 1
I/O 3
I/O 3
I/O 2
I/O 2
I/O 0
I/O 0
I/O 5
I/O 5
I/O 7
I/O 7
DQS0
DM0
UDQS
UDM
I/O 8
DQS4
DM4
UDQS
UDM
I/O 8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
/CS
/CS
DQS3
DM3
LDQS
LDM
DQS7
DM7
LDQS
LDM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
I/O 6
I/O 6
I/O 4
I/O 4
I/O 1
I/O 1
I/O 3
I/O 3
I/O 2
I/O 2
I/O 0
I/O 0
I/O 5
I/O 5
I/O 7
I/O 7
DQS2
DM2
UDQS
UDM
I/O 8
DQS6
DM6
UDQS
UDM
I/O 8
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
Serial PD
.
SPD
VDDSPD
VDD/VDDQ
VREF
.
D0 - D3
D0 - D3
SCL
WP
= =
SDA
.
A0
SA0
A1
A2
=
. . . .
VSS
D0 - D3
..
SA1
SA2
VDDID
Strap:see Note 4
BA0-BA1
A0 - A12
/RAS
/CAS
CKE0
BA0-BA1 : SDRAMs D0 - D3
A0 - A12 : SDRAMs D0 - D3
/RAS : SDRAMs D0 - D3
/CAS : SDRAMs D0 - D3
CKE : SDRAMs D0 - D3
/WE : SDRAMs D0 - D3
Notes:
DQ wiring may differ from that described in this drawing ;
however DQ/DM/DQS relationship are maintained as shown.
VDDID strap connections;
(for memory device VDD, VDDQ) :
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD= VDDQ
/WE
Rev. 0.1/May. 02
3
HYMD532M646(L)6-K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
oC
Ambient Temperature
TA
0 ~ 70
oC
V
Storage Temperature
TSTG
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
VIN, VOUT
VDD
V
VDDQ
IOS
V
mA
W
PD
8
oC / Sec
Soldering Temperature Þ Time
TSOLDER
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDD
2.3
2.3
2.5
2.5
-
2.7
2.7
V
V
V
V
V
V
VDDQ
VIH
1
2
3
VREF + 0.15
-0.3
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
1.35
VIL
-
Termination Voltage
Reference Voltage
VTT
VREF - 0.04
1.15
VREF
1.25
VREF
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
VREF - 0.31
VDDQ + 0.6
0.7
1
2
Input Crossing Point Voltage, CK and /CK inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.1/May. 02
4
HYMD532M646(L)6-K/H/L
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
Termination Voltage
VDDQ x 0.5
V
V
VDDQ x 0.5
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
VREF + 0.31
V
VREF - 0.31
V
VREF
VTT
1.5
1
V
V
V
Input minimum Signal Slew Rate
V/ns
W
W
pF
Termination Resistor (RT)
50
Series Resistor (RS)
25
Output Load Capacitance for Access Time Measurement (CL)
30
Rev. 0.1/May. 02
5
HYMD532M646(L)6-K/H/L
CAPACITANCE (TA=25oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Capacitance
A0 ~ A12, BA0, BA1
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
pF
pF
pF
pF
pF
pF
Input Capacitance
/RAS, /CAS, /WE
CKE0, CKE1
Input Capacitance
Input Capacitance
/CS0, /CS1
Input Capacitance
CK0, /CK0, CK1, /CK1
DM0 ~ DM7
Input Capacitance
Data Input / Output Capacitance
DQ0 ~ DQ63, DQS0 ~ DQS7
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
Ω
RT=50
Output
Ω
Zo=50
VREF
CL=30pF
Rev. 0.1/May. 02
6
HYMD532M646(L)6-K/H/L
DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Add, CMD, /CS, /CKE
Symbol
Min.
Max
Unit
Note
-8
8
Input Leakage
Current
CK0, /CK0, CK1, /CK1
CK2, /CK2
ILI
-8
8
uA
1
0
0
Output Leakage Current
Output High Voltage
Output Low Voltage
ILO
VOH
VOL
-5
5
uA
V
2
VTT + 0.76
-
-
IOH = -15.2mA
IOL = +15.2mA
VTT - 0.76
V
Note :
1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 2.7V
Rev. 0.1/May. 02
7
HYMD532M646(L)6-K/H/L
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
-H
Parameter
Operating Current
Operating Current
Symbol
IDD0
Test Condition
Unit Note
-K
-L
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle ; address and control inputs
changing once per clock cycle
440
440
520
400
mA
mA
One bank; Active - Read - Precharge; Burst Length =2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
IDD1
520
28
480
24
Precharge Power
Down Standby Current
All banks idle; Power down mode; CKE=Low, tCK=
tCK(min)
IDD2P
IDD2N
28
mA
mA
Idle Standby Current
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
140
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
Idle Standby Current
IDD2F
140
mA
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref for
DQ, DQS and DM
Idle Quiet Standby
Current
IDD2Q
IDD3P
128
40
mA
mA
Active Power Down
Standby Current
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Active Standby Current
Operating Current
Operating Current
IDD3N
IDD4R
IDD4W
IDD5
160
800
mA
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
800
880
680
800
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM, and DQS inputs
changing twice per clock cycle
880
mA
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
Auto Refresh Current
Self Refresh Current
1200
1200
1040
Normal
20
10
mA
mA
CKE=<0.2V; External clock on; tCK
=tCK(min)
IDD6
IDD7
Low Power
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
1560
1560
1560
1400
1400
mA
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
mA, 100% DQ, DM and DQS inputs changing twice
per clock cycle; 100% addresses changing once per
clock cycle
Random Read Current
IDD7A
1560
mA
Rev. 0.1/May. 02
8
HYMD532M646(L)6-K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-K(DDR266A)
-H(DDR266B)
-L(DDR200)
Parameter
Symbol
Unit
Note
Min
65
Max
Min
65
Max
Min
70
Max
Row Cycle Time
tRC
tRFC
tRAS
-
-
-
-
-
-
ns
ns
ns
Auto Refresh Row Cycle Time
Row Active Time
75
75
80
45
120K
45
120K
50
120K
tRCD or
tRP min
tRCD or
tRP min
tRCD or
tRP min
Active to Read with Auto Precharge Delay
tRAP
-
-
-
ns
16
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
tRCD
tRRD
tCCD
tRP
20
15
1
-
-
-
-
-
-
20
15
1
-
-
-
-
-
-
20
15
1
-
-
-
-
-
-
ns
ns
CK
ns
20
15
1
20
15
1
20
15
1
Write Recovery Time
tWR
tWTR
ns
Write to Read Command Delay
CK
Auto Precharge Write Recovery+Precharge
Time
tDAL
tCK
5
-
5
-
4
-
CK
15
CL = 2.5
System Clock Cycle Time
CL = 2
7.5
7.5
12
12
7.5
10
12
12
8
12
12
ns
ns
10
Clock High Level Width
tCH
tCL
tAC
0.45
0.45
-0.75
0.55
0.55
0.75
0.75
0.5
0.45
0.45
-0.75
-0.75
-
0.55
0.55
0.75
0.75
0.5
0.45
0.45
-0.8
-0.8
-
0.55
0.55
0.8
CK
CK
ns
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tDQSCK -0.75
0.8
ns
tDQSQ
tQH
-
0.6
ns
tHPmin
-tQHS
tHPmin
-tQHS
tHPmin
-tQHS
Data-Out hold time from DQS
Clock Half Period
-
-
-
ns
ns
1, 10
tCH/L
min
tCH/L
min
tCH/L
min
tHP
-
-
-
1,9
10
Data Hold Skew Factor
tQHS
tDV
tHZ
tLZ
-
0.75
-
0.75
-
0.75
ns
ns
ns
ns
ns
ns
ns
ns
ns
Valid Data Output Window
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Input Pulse Width
-0.75
-0.75
0.9
0.75
-0.75
-0.75
0.9
0.75
-0.8
-0.8
1.1
1.1
1.1
1.1
-
0.8
0.75
0.75
0.8
tIS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
6
tIH
0.9
0.9
tIS
1.0
1.0
tIH
1.0
1.0
tIPW
2.2
2.2
Rev. 0.1/May. 02
9
HYMD532M646(L)6-K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
-K(DDR266A)
-H(DDR266B)
-L(DDR200)
Parameter
Symbol
Unit
Note
Min
0.35
0.35
0.75
Max
Min
0.35
0.35
0.75
Max
Min
0.35
0.35
0.75
Max
Write DQS High Level Width
Write DQS Low Level Width
tDQSH
tDQSL
tDQSS
-
-
-
-
-
-
CK
CK
CK
Clock to First Rising edge of DQS-In
1.25
1.25
1.25
6,7,
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
tDS
tDH
0.5
0.5
-
-
0.5
0.5
-
-
0.6
0.6
-
-
ns
ns
11~13
6,7,
11~13
DQ & DM Input Pulse Width
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
1.75
0.9
0.4
0
-
1.1
0.6
-
1.75
0.9
0.4
0
-
1.1
0.6
-
2
0.9
0.4
0
-
1.1
0.6
-
ns
CK
CK
CK
CK
CK
CK
CK
us
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
0.25
0.4
2
-
0.25
0.4
2
-
0.25
0.4
2
-
0.6
-
0.6
-
0.6
-
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
tXSC
200
-
-
200
-
-
200
-
-
8
tREFI
7.8
7.8
7.8
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
ps
Delta tIH
V/ns
0.5
ps
0
0
0.4
+50
0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to
n-channel variation of the output drivers.
Rev. 0.1/May. 02
10
HYMD532M646(L)6-K/H/L
11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
0.5
ps
0
ps
0
0.4
+75
+150
+75
+150
0.3
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS
slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns
and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
0
ps
0
ps
0
+/-0.25
+/- 0.5
+50
+100
+50
+100
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK
is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
Rev. 0.1/May. 02
11
HYMD532M646(L)6-K/H/L
SIMPLIFIED COMMAND TRUTH TABLE
A10/
ADDR
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
BA
Note
AP
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
H
H
X
X
L
L
H
L
L
L
L
L
L
L
L
OP code
OP code
1,2
1,2
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active
RA
V
V
1
1
Read
L
H
L
L
L
L
H
H
L
L
L
H
L
L
CA
CA
X
Read with Autoprecharge
Write
1,3
1
H
H
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
H
H
L
1,4
1,5
1
X
V
H
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
L
L
L
1
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry
Precharge
Power Down
H
L
Mode
Exit
H
H
L
Active Power
Down Mode
(Clock Suspend)
Entry
Exit
H
L
L
H
X
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.1/May. 02
12
HYMD532M646(L)6-K/H/L
MODULE DIMENSIONS
Front
67.60 mm
Side
3.8mm
MAX.
(Front)
31.75 mm
20.00 mm
1
39
41
199
Voltage
Key
2.7 mm
4.0 mm
1.0 mm
1.8 mm
0.66mm
Left key position:
2.5V
Right key position:
Reserved
V
DD = VDDQ=
Rev. 0.1/May. 02
13
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(32Mx64 Unbuffered DDR SO-DIMM)
Rev. 0.1/May. 02
14
HYMD532M646(L)6-K/H/L
SERIAL PRESENCE DETECT
Bin Sort : K(DDR266A@CL=2), H(DDR266B@CL=2.5), L(DDR200@CL=2)
Function Supported
H
Hexa Value
H
Byte#
Function Description
Note
K
L
K
L
Number of Bytes written into serial memory at module
manufacturer
0
128 Bytes
80h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of physical banks on DIMM
Module data width
256 Bytes
DDR SDRAM
08h
07h
0Dh
0Ah
01h
40h
00h
04h
75h
75h
00h
82h
10h
00h
13
10
1Bank
64 Bits
-
1
1
Module data width (continued)
Module voltage Interface levels(VDDQ)
DDR SDRAM cycle time at CAS Latency=2.5(tCK)
DDR SDRAM access time from clock at CL=2.5 (tAC)
Module configuration type
Refresh rate and type
Primary DDR SDRAM width
SSTL 2.5V
7.5ns
+/-0.75ns +/-0.75ns +/-0.8ns
7.5ns
8ns
75h
75h
80h
80h
2
2
Non-ECC
7.8us & Self refresh
x16
N/A
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
15
1 CLK
01h
address(tCCD)
16
17
18
19
20
21
Burst lengths supported
Number of banks on each DDR SDRAM
CAS latency supported
CS latency
WE latency
DDR SDRAM module attributes
2,4,8
4 Banks
2, 2.5
0
0Eh
04h
0Ch
01h
02h
20h
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
22
DDR SDRAM device attributes : General
C0h
23
24
25
26
27
28
29
30
31
32
33
34
35
DDR SDRAM cycle time at CL=2.0(tCK)
DDR SDRAM access time from clock at CL=2.0(tAC)
DDR SDRAM cycle time at CL=1.5(tCK)
DDR SDRAM access time from clock at CL=1.5(tAC)
Minimum row precharge time(tRP)
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
7.5ns
10ns
10ns
75h
75h
A0h
75h
00h
00h
50h
3Ch
50h
2Dh
40h
90h
90h
50h
50h
00h
41h
A0h
80h
+/-0.75ns +/-0.75ns +/-0.8ns
-
-
20ns
15ns
20ns
45ns
20ns
15ns
20ns
20ns
15ns
20ns
50ns
50h
3Ch
50h
2Dh
50h
3Ch
50h
32h
45ns
256MB
0.9ns
0.9ns
0.5ns
0.5ns
Undefined
65ns
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
0.9ns
0.9ns
0.5ns
0.5ns
1.1ns
1.1ns
0.6ns
0.6ns
90h
90h
50h
50h
B0h
B0h
60h
60h
Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41
Minimum active / auto-refresh Time (tRC)
65ns
75ns
70ns
80ns
41h
4Bh
46h
50h
Minimum auto-refresh to active / auto-refresh
42
75ns
4Bh
command period (tRFC)
43
Maximum cycle time (tCK max)
12ns
12ns
12ns
30h
30h
32h
30h
44
45
Maximum DQS-DQ skew time (tDQSQ)
0.5ns
0.5ns
0.6ns
32h
75h
3Ch
75h
Maximum read data hold skew factor (tQHS)
0.75ns
0.75ns
Undefined
Initial release
-
0.75ns
75h
00h
00h
02h
46~61 Superset Information(may be used in future)
62
63
SPD Revision code
Checksum for Bytes 0~62
D7h
9Ch
Rev. 0.1/May. 02
15
HYMD532M646(L)6-K/H/L
SERIAL PRESENCE DETECT(continued)
Function Supported
Hexa Value
H
Byte #
Function Description
Manufacturer JEDEC ID Code
Note
K
H
L
K
L
64
65~71
Hynix JEDEC ID
ADh
00h
--------- Manufacturer JEDEC ID Code
-
Hynix(Korea Area)
0*h
1*h
2*h
3*h
4*h
5*h
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
72
Manufacturing location
6
Asia Area
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87~90
91
Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
Manufacture part number (DDR SDRAM)
Manufacture part number(Memory density)
Manufacture part number(Module Depth)
------- Manufacture part number(Module Depth)
Manufacture part number(Module type)
Manufacture part number(Data width)
-------Manufacture part number(Data width)
Manufacture part number(Refresh, # of Bank.)
Manufacture part number(Component configuration)
Manufacture part number(Hyphen)
H
Y
M
D
5
3
2
M
48h
59h
4Dh
44h
35h
33h
32h
4Dh
36h
34h
36h
36h
2Dh
48h
20h
20h
-
6
4
6(8K refresh,4Bank)
6
‘-’
H
-
Blank
-
Manufacture part number(Minimum cycle time)
Manufacture part number(T.B.D)
Manufacture revision code(for Component)
Manufacture revision code (for PCB)
K
L
4Bh
4Ch
92
93
94
95~98
99~127
Manufacturing date(Year)
Manufacturing date(Week)
Module serial number
Manufacturer specific data (may be used in future)
-
-
-
-
-
-
3
3
4
5
5
Undefined
Undefined
00h
00h
128~255 Open for customer use
Note :
1. The bank address is excluded
2. This value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number System
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix Web Site
Byte 84~85, Low power part
Function Supported
Hexa Value
H
Byte#
Function Description
Note
K
H
L
K
L
84
85
Manufacture part number(Low power part)
Manufacture part number(Component Configuration)
L
6
4Ch
36h
Rev. 0.1/May. 02
16
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