HYMP112S64P8-Y5 [HYNIX]
DDR DRAM Module, 128MX64, 0.45ns, CMOS, ROHS COMPLIANT, SODIMM-200;
| 型号： | HYMP112S64P8-Y5 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM Module, 128MX64, 0.45ns, CMOS, ROHS COMPLIANT, SODIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总20页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb 1st ver.
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 1Gb 1st ver. DDR2 SDRAMs
in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb 1st ver. based Unbuffered
DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard.
It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
•
•
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both
sequential and interleave mode
•
All inputs and outputs are compatible with SSTL_1.8
interface
•
•
•
•
•
•
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
•
•
Posted CAS
Serial presence detect with EEPROM
DDR2 SDRAM Package: 68 ball FBGA
67.60 x 30.00 mm form factor
Programmable CAS Latency 3 ,4 ,5
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
Lead-free Products are RoHS compliant
ORDERING INFORMATION
# of
DRAMs
# of
ranks
Part Name
Density
Organization
Materials
HYMP112S648-E3/C4/Y5
HYMP325S64M*8-E3/C4/Y5
HYMP112S64P8-E3/C4/Y5
HYMP325S64M*P8-E3/C4/Y5
1GB
2GB
1GB
2GB
128Mx64
256Mx64
128Mx64
256Mx64
8
16
8
1
2
1
2
Leaded
Leaded
Lead free
Lead free
16
Notes:
* : ‘M’ stands for Hynix Dual Die Package(DDP) based module.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2 / Sep. 2005
1
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400)
C4 (DDR2-533)
Y5 (DDR2-667)
Unit
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
400
-
400
533
-
400
533
Mbps
Mbps
Mbps
tCK
667
3-3-3
4-4-4
5-5-5
ADDRESS TABLE
# of
DRAMs
Refresh
Method
Density Organization Ranks
SDRAMs
# of row/bank/column Address
1GB
2GB
128M x 64
256M x 64
2
2
128Mb x 8
128Mb x 8
8
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
8K / 64ms
16
Rev. 1.2 / Sep. 2005
2
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PIN DESCRIPTION
Symbol
Type
Polarity
Pin Description
The system clock inputs. All adress an commands lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to
the input clock.
Cross
Point
CK[1:0], CK[1:0]
Input
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Active
High
CKE[1:0]
S[1:0]
Input
Input
Enables the associated DDR2 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1
Active
Low
Active
Low
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,
RAS and WE define the operation to be excecuted by the SDRAM.
RAS, CAS, WE
BA[2:0]
Input
Input
Input
Selects which DDR2 SDRAM internal bank of four or eight is activated.
Active
High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
ODT[1:0]
During a Bank Activate command cycle, difines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-
mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is
high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP
is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in
conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn
are used to define which bank to precharge.
A[9:0], A10/AP,
A[15:11]
Input
DQ[63:0]
DM[7:0]
In/Out
Input
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.
Active
High
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading
edge of the data window. DQS signals are complements, and timing is relative to the
crosspoint of respective DQS and DQS. If the module is to be operated in single ended
strobe mode, all DQS signals must be tied on the system board to VSS and DDR2
SDRAM mode registers programmed approriately.
Cross
point
DQS[7:0], DQS[7:0] In/Out
VDD, VDDSPD,VSS
SDA
Supply
In/Out
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to VDD to act as a pull up.
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to VDD to act as a pull up.
SCL
Input
Input
In/Out
SA[1:0]
TEST
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).
Rev. 1.2 / Sep. 2005
3
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PIN ASSIGNMENT
Pin Front Pin Back Pin Front
Pin
NO.
Back
Side
Pin
NO.
Front
Side
Pin
NO.
Back
Side
Pin
NO.
Front
Side
Pin
NO.
Back
Side
NO. Side NO. Side NO.
Side
DQS2
VSS
1
VREF
VSS
2
VSS
DQ4
DQ5
VSS
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
52
54
56
58
60
62
64
66
68
70
72
74
76
78
DM2
VSS
101
103
A1
102
104
106
108
110
112
114
116
118
A0
VDD
BA1
151
153
155
157
159
161
DQ42
DQ43
VSS
152 DQ46
154 DQ47
3
4
VDD
5
DQ0
DQ1
VSS
6
DQ18
DQ19
VSS
DQ22
DQ23
VSS
105 A10/AP
156
VSS
7
8
107
109
111
113
115
117
BA0
WE
RAS
DQ48
DQ49
VSS
158 DQ52
160 DQ53
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
DM0
VSS
S0
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS0
DQS0
VSS
DQ24
DQ25
VSS
DQ28
DQ29
VSS
VDD
CAS
VDD
ODT0
A13
162
VSS
CK1
CK1
VSS
DM6
VSS
DQ6
DQ7
VSS
163 NC,TEST 164
NC/S1
VDD
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
VSS
DQS6
DQS6
VSS
166
168
170
172
DQ2
DQ3
VSS
DM3
NC
DQS3
DQS3
VSS
VDD
NC
DQ12
DQ13
VSS
119 NC/ODT1 120
VSS
121
123
125
127
VSS
DQ32
DQ33
VSS
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
VSS
DQ8
DQ9
VSS
DQ26
DQ27
VSS
DQ30
DQ31
VSS
DQ36
DQ37
VSS
DQ50
DQ51
VSS
174 DQ54
176 DQ55
DM1
VSS
178
VSS
DQS1
DQS1
VSS
CK0
CKE0
VDD
NC
80 NC/CKE1 129
DQS4
DQS4
VSS
DM4
VSS
DQ56
DQ57
VSS
180 DQ60
182 DQ61
CK0
82
84
86
88
90
92
94
96
98
100
VDD
131
VSS
NC/A15 133
NC/A14 135
DQ38
DQ39
VSS
184
VSS
DQ10
DQ11
VSS
DQ14
DQ15
VSS
BA2
VDD
A12
DQ34
DQ35
VSS
DM7
VSS
186 DQS7
188 DQS7
VDD
A11
A7
137
139
141
143
145
147
149
DQ44
DQ45
VSS
DQ58
DQ59
VSS
190
VSS
VSS
VSS
A9
DQ40
DQ41
VSS
192 DQ62
194 DQ63
DQ16
DQ17
VSS
DQ20
DQ21
VSS
A8
A6
VDD
A5
VDD
A4
DQS5
DQS5
VSS
SDA
196
198
VSS
SA0
SA1
DM5
VSS
SCL
DQS2
NC
A3
A2
199 VDDSPD 200
Pin Location
200
42
2
40
Back
Front
1
199
39
41
Rev. 1.2 / Sep. 2005
4
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx64) : HYMP112S648-E3/C4
N .C .
N .C .
N .C .
/S 1
O D T 1
C K E 1
3 Ω + /− 5%
C K E 0
O D T 0
D Q S 0
D Q S 0
/D Q S 0
D M 0
D Q S 4
/D Q S 4
D M 4
D Q S
/D Q S
D M
D Q S
/D Q S
D M
/C S
O D T C K E
/C S
O D T C K E
I/O
I/O
I/O
I/O
I/O
I/O
0
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
D Q 0
D Q 1
D Q 2
D Q 3
D Q 4
D Q 5
D Q 6
D Q 7
D Q 32
D Q 33
D Q 34
D Q 35
D Q 36
D 0
D 4
1
2
3
4
5
D Q 37
D Q 38
D Q 39
I/O
I/O
6
7
I/O
I/O
6
7
D Q S 1
/D Q S 1
D M 1
D Q S 5
/D Q S 5
D M 5
D Q S
/D Q S
D M
D Q S
/D Q S
D M
/C S
O D T C K E
O D T C K E
O D T C K E
/C S
O D T C K E
O D T C K E
O D T C K E
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
0
D Q 8
D Q 8
D Q 40
D Q 41
D Q 42
D Q 43
D Q 44
D Q 45
D Q 46
D Q 47
D 1
D 5
1
2
3
4
5
D Q 10
D Q 11
D Q 12
D Q 13
D Q 14
D Q 1 5
I/O
I/O
6
7
I/O
I/O
6
7
D Q S 2
/D Q S 2
D M 2
D Q S 6
/D Q S 6
D M 6
D Q S
/D Q S
D M
D Q S
/D Q S
D M
/C S
/C S
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
0
D Q 16
D Q 17
D Q 18
D Q 19
D Q 48
D Q 49
D Q 50
D Q 51
D 2
D 6
1
2
3
4
5
D Q 20
D Q 21
D Q 22
D Q 2 3
D Q 52
D Q 53
D Q 54
D Q 55
I/O
I/O
6
7
I/O
I/O
6
7
D Q S 3
/D Q S 3
D M 3
D Q S 0
/D Q S 0
D M 0
D Q S
/D Q S
D M
D Q S
/D Q S
D M
/C S
/C S
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
0
D Q 24
D Q 25
D Q 26
D Q 27
D Q 56
D Q 57
D Q 58
D Q 59
D 3
D 7
1
2
3
4
5
D Q 28
D Q 29
D Q 30
D Q 3 1
D Q 60
D Q 61
D Q 62
D Q 63
I/O
I/O
6
7
I/O
I/O
6
7
S C L
S C L
A 0
A 1
3 Ω + /- 5%
S D A
S D A
S A 0
S A 1
S eria l P D
W P
B A 0 -B A 2
A 0 -A N
/R A S
/C A S
/W E
S D R A M S D 0-7
S D R A M S D 0-7
S D R A M S D 0-7
S D R A M S D 0-7
S D R A M S D 0-7
A 2
VD D S P D
V R E F
S erial P D
S D R A M S D O -D 7
C K 0
4
4
lo ad s
lo ad s
VD D
S D R A M S D O -D 7, V D D and V D D Q
S D R A M S D O -D 7 , S P D
/C K 0
VS S
C K 1
N otes :
1. R e sistor values are 22 O hm + /- 5% .
/C K 1
Rev. 1.2 / Sep. 2005
5
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx64) : HYMP351S64M8-E3/C4
3 Ω+/− 5%
CKE 1
ODT 1
/S1
CKE 0
ODT 0
/S 0
DQS 0
/ DQS 0
DM 0
DQS 4
/ DQS 4
DM 4
DQS
/ DQS
DM
DQS
/ DQS
DM
/CS
0
ODT
0
CKE0
/CS
1
ODT
1
CKE1
/CS
/CS
/CS
/CS
0
0
0
0
ODT
0
CKE0
/CS
1
ODT
1
1
1
1
CKE1
CKE1
CKE1
CKE1
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ 0
DQ 1
DQ 2
DQ 3
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
D0,D8( DDP)
D4,D 12( DDP)
DQ 4
DQ 5
DQ 6
DQ 7
DQ 37
DQ 38
DQ 39
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQS 1
/ DQS 1
DM 1
/CS
0
ODT
0
CKE0
/CS
1
ODT
1
CKE1
DQS 5
/ DQS 5
DM 5
ODT
0
CKE0
/CS 1 ODT
DQS
/ DQS
DM
DQS
/ DQS
DM
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 0
I/ O 1
I/ O 2
I/ O 3
DQ 8
DQ 8
DQ 40
DQ 41
DQ 42
DQ 43
D1,D9( DDP)
D5,D 13( DDP)
DQ 10
DQ 11
I/ O 4
I/ O 5
I/ O 4
I/ O 5
DQ 12
DQ 13
DQ 14
DQ 15
DQ 44
DQ 45
DQ 46
DQ 47
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQS 2
/ DQS 2
DM 2
DQS 6
/ DQS 6
DM 6
ODT
0
CKE0
/CS 1 ODT
DQS
/ DQS
DM
DQS
/ DQS
DM
/CS
0
ODT
0
CKE0
/CS 1 ODT 1 CKE1
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 0
I/ O 1
I/ O 2
I/ O 3
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
D2,D 10( DDP)
D6,D 14( DDP)
I/ O 4
I/ O 5
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQS 3
/ DQS 3
DM 3
DQS 7
/ DQS 7
DM 7
ODT
0
CKE0
/CS 1 ODT
DQS
/ DQS
DM
DQS
/ DQS
DM
/CS
0
ODT
0
CKE0
/CS 1 ODT 1 CKE1
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ 24
DQ 25
DQ 26
DQ 27
DQ 56
DQ 57
DQ 58
DQ 59
D3,D 11( DDP)
D7,D 15( DDP)
DQ 28
DQ 29
DQ 30
DQ 31
DQ 60
DQ 61
DQ 62
DQ 63
I/ O 6
I/ O 7
I/ O 6
I/ O 7
SCL
SCL
SDA
SDA
10Ω+/-5 %
SA0
SA1
A0
A1
A2
Serial PD
WP
BA0 ? BA2
SDRAMS D 0-15
SDRAMS D 0-15
SDRAMS D 0-15
SDRAMS D 0-15
SDRAMS D 0-15
A0- AN
/ RAS
/ CAS
/ WE
:
VDD SPD
Serial PD
SDRAMS DO -D 15
CK0
8 loads
8 loads
8 loads
8 loads
9.1 pF
VREF
VDD
/CK0
CK1
Notes :
1. Resistor values are 22 Ohm +/- 5%
SDRAMS DO -D 15 , VDD and VDD
SDRAMS DO -D 15 , SPD
Q
9.1 pF
/CK1
VSS
Rev. 1.2 / Sep. 2005
6
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VDD
Value
Unit
Note
- 1.0 V ~ 2.3 V
-0.5V ~ 2.3 V
V
V
V
V
1
1
Voltage on VDD pin relative to Vss
VDDL
Voltage on VDDL pin relative to Vss
Voltage on VDDQ pin relative to Vss
VDDQ
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-50 ~ +100
5 to 95
1
1
1
1
V
IN, VOUT
TSTG
Voltage on any pin relative to Vss
Storage Temperature
oC
HSTG
Storage Humidity(without condensation)
%
Notes:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
OPERATING CONDITIONS
Parameter
Symbol
Rating
Units
Notes
oC
TOPR
0 ~ +55
DIMM Operating temperature(ambient)
PBAR
DIMM Barometric Pressure(operating & storage)
105 to 69
0 ~+95
K Pascal
1
2
DRAM Component Case Temperature Range
oC
TCASE
Notes:
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Symbol
VDD
Min
1.7
Max
1.9
Unit
V
Note
VDDL
1.7
1.9
V
Power Supply Voltage
VDDQ
VREF
1.7
1.9
V
1
2
Input Reference Voltage
EEPROM Supply Voltage
0.49 x VDDQ
1.7
0.51 x VDDQ
3.6
V
VDDSPD
VTT
V
V
REF+0.04
V
3
VREF-0.04
Termination Voltage
Notes:
1. VDDQ must be less than or equal to VDD
.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Rev. 1.2 / Sep. 2005
7
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
INPUT DC LOGIC LEVEL
Parameter
Input High Voltage
Input Low Voltage
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.30
Max
Unit
V
Note
VDDQ + 0.3
VREF - 0.125
V
INPUT AC LOGIC LEVEL
DDR2 400/533
DDR2 667
Parameter
Symbol
Unit
Min
Max
Min
Max
AC Input logic High VIH(AC)
AC Input logic Low VIL(AC)
V
V
V
REF + 0.250
-
-
VREF + 0.200
-
-
V
REF - 0.250
VREF - 0.200
AC INPUT TEST CONDITIONS
Symbol
VREF
Condition
Input reference voltage
Value
Units
Notes
0.5 * VDDQ
V
V
1
1
VSWING(MAX)
SLEW
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
V
SWING(MAX)
max
max
IL(dc)
IL(ac)
SS
delta TF
delta TR
Rising Slew =
V
min - V
REF
V
-
V
max
IL(ac)
IH(ac)
REF
Falling Slew =
delta TF
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 1.2 / Sep. 2005
8
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VID (ac)
0.5
VDDQ + 0.6
V
1
ac differential input voltage
ac differential cross point voltage
VIX (ac)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level.
The minimum value is equal to VIH(DC) - VIL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
Parameter
Min.
Max.
Units
Note
VOX (ac)
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 1.2 / Sep. 2005
9
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
Parameter
SSTL_18
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Notes:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18
Units
Notes
- 13.4
13.4
mA
mA
1, 3, 4
2, 3, 4
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
DDQ - 280 mV.
V
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver.
The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define
a convenient driver current for measurement.
Rev. 1.2 / Sep. 2005
10
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
1GB : HYMP112S64[P]8
Pin
Symbol
Min
Max
Unit
CK, CK
CCK
CI1
CI2
CIO
13
24
23
5
21
38
40
8
pF
pF
pF
pF
CKE, ODT,CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
2GB : HYMP351S64M[P]8
Pin
Symbol
Min
Max
Unit
CK, CK
CCK
CI1
CI2
CIO
25
32
47
16
49
58
96
20
pF
pF
pF
pF
CKE, ODT,CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
Notes:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 1.2 / Sep. 2005
11
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
IDD SPECIFICATIONS (TCASE : 0 to 95oC)
1GB, 128M x 64 SO- DIMM : HYMP112S64[P]8
Symbol
IDD0
E3(DDR2 400@CL3)
C4(DDR2 533@CL 4)
Y5(DDR2 667@CL 5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
800
880
48
880
960
48
960
1040
56
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
320
360
200
56
400
440
240
64
480
520
280
72
480
1040
1120
2160
64
560
1360
1440
2160
64
640
1840
1920
2160
64
1
1
IDD6(L)
IDD7
40
40
40
1920
2400
2720
2GB, 256M x 64 SO - DIMM : HYMP325S64M[P]8
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Y5(DDR2 667@CL 5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
1280
1360
96
1440
1520
96
1600
1680
112
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
640
720
400
112
960
1520
1760
2640
128
80
800
960
880
1040
560
480
128
144
1120
1920
2080
2720
128
1280
2480
2560
2800
128
1
1
IDD6(L)
IDD7
80
80
2720
3120
3360
Notes:
1. IDD6 current values are guaranted up to Tcase of 85℃ max.
Rev. 1.2 / Sep. 2005
12
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
IDD Meauarement Conditions
Symbol
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
IDD0
IDD1
mA
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
t
t
CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and address
IDD2P
IDD2Q
IDD2N
mA
mA
mA
bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD); CKE is LOW;
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
IDD4R
Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-
ING
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
mA
mA
t
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK =
t
t
t
t
t
CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
t
t
t
t
t
t
= 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD5B
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 ℃ max.
IDD6
mA
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
t
t
t
t
AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; - Refer to the following page for detailed timing conditions
IDD7
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations
of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Rev. 1.2 / Sep. 2005
13
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
DDR2-667 (Y5)
DDR2-533 (C4)
DDR2-400 (E3)
Unit
5-5-5
min
5
4-4-4
min
4
3-3-3
min
3
tCK
ns
15
15
15
tRP
15
15
15
ns
tRAS
45
45
40
ns
tRC
60
60
55
ns
AC Timing Parameters by Speed Grade
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
-600
-500
0.45
0.45
Max
Min
-500
-450
0.45
0.45
Max
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
Clock High Level Width
tAC
tDQSCK
tCH
600
500
500
450
ps
ns
0.55
0.55
0.55
0.55
CK
CK
Clock Low Level Width
tCL
min
(tCL,tCH)
min
(tCL,tCH)
Clock Half Period
tHP
-
-
ns
ps
System Clock Cycle Time
tCK
tDS
5000
150
275
25
8000
3750
100
225
-25
8000
DQ and DM input setup time
-
-
-
-
-
-
-
-
-
-
ps
ps
1
1
1
1
DQ and DM input hold time
tDH
DQ and DM input setup time(single-ended strobe)
DQ and DM input hold time(single-ended strobe)
Control & Address input Pulse Width for each input
tDS1
tDH1
tIPW
ps
25
-25
ps
0.6
0.6
tCK
DQ and DM input pulse witdth for each input pulse
width for each input
tDIPW
tHZ
0.35
-
0.35
-
tCK
Data-out high-impedance window from CK, /CK
-
tAC max
-
tAC max
ps
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
2*tAC min
tAC max
tAC max
350
450
tAC min
2*tAC min
tAC max
tAC max
300
400
ps
ps
ps
-
-
-
-
ps
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock edge tDQSS
tQH
tHP - tQHS
-0.25
0.35
0.35
0.2
-
tHP - tQHS
-0.25
0.35
0.35
0.2
-
ps
+0.25
-
-
-
-
-
0.6
-
+0.25
-
-
-
-
-
0.6
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
tDSH
0.2
2
0.4
0.35
-600
0.2
2
0.4
0.35
-500
tMRD
tWPST
tWPRE
tAC
Write preamble
Data-Out edge to Clock edge Skew
600
500
Address and control input setup time
tIS
350
-
250
-
ps
Rev. 1.2 / Sep. 2005
14
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
- Continued -
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Address and control input hold time
Read preamble
Read postamble
tIH
tRPRE
tRPST
475
0.9
0.4
-
1.1
0.6
375
0.9
0.4
-
1.1
0.6
ps
tCK
tCK
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
127.5
-
127.5
-
ns
Row Active to Row Active Delay for 1KB page size
tRRD
tFAW
tFAW
7.5
37.5
50
-
-
-
7.5
37.5
50
-
-
-
ns
ns
ns
Four Activate Window for 1KB page size
Four Activate Window for 2KB page size
CAS to CAS command delay
Write recovery time
Auto Precharge Write Recovery + Precharge Time
tCCD
tWR
tDAL
2
15
tWR+tRP
2
15
tWR+tRP
tCK
ns
tCK
-
-
-
-
Write to Read Command Delay
tWTR
10
-
ns
7.5
7.5
tRFC + 10
200
-
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
tRTP
tXSNR
tXSRD
7.5
tRFC + 10
200
ns
ns
tCK
-
-
-
-
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
Exit active power down to read command
tXARD
tXARDS
6 - AL
6 - AL
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
tCKE
tAOND
tAON
3
2
3
2
tCK
tCK
ns
ODT turn-on delay
2
2
tAC(max)
+1
tAC(max)
+1
ODT turn-on
tAC(min)
tAC(min)
2tCK+tAC
(max)+1
2.5
tAC(max)+
0.6
2tCK+tAC
(max)+1
2.5
tAC(max)+
0.6
tAONPD
tAOFD
tAOF
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
ODT turn-off
tAC(min)
tAC(min)
2.5tCK+tAC
(max)+1
2.5tCK+tAC
(max)+1
tAOFPD
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
ns
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Notes:
1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS1G831(L)F).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 1.2 / Sep. 2005
15
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
DDR2-667
Symbol
Unit
Note
Parameter
min
-450
-400
0.45
0.45
max
+450
+400
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
tDQSCK
tCH
ps
ps
tCK
tCK
CK low-level width
tCL
0.55
min(tCL,
tCH)
CK half period
tHP
tCK
tDS
-
8000
-
ps
ps
ps
Clock cycle time, CL=x
3000
DQ and DM input setup time
(differential strobe)
100
1
1
DQ and DM input hold time
(differential strobe)
tDH
175
-
ps
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tIPW
tDIPW
tHZ
0.6
0.35
-
-
tCK
tCK
ps
-
tAC max
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
2*tAC min
-
tAC max
ps
tAC max
ps
240
ps
-
340
ps
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock edge
DQS input high pulse width
tQH
tHP - tQHS
- 0.25
0.35
0.35
0.2
-
ps
tDQSS
tDQSH
tDQSL
tDSS
+ 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
DQS input low pulse width
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
-
tDSH
0.2
-
tMRD
tWPST
tWPRE
tIS
2
-
0.6
-
0.4
Write preamble
0.35
200
Address and control input setup time
Address and control input hold time
Read preamble
-
tIH
275
-
ps
tRPRE
tRPST
tRAS
0.9
1.1
0.6
70000
tCK
tCK
ns
Read postamble
0.4
Activate to precharge command
45
Active to active command period for 1KB page size
products
tRRD
tFAW
7.5
-
-
ns
ns
Four Active Window for 1KB page size products
37.5
Rev. 1.2 / Sep. 2005
16
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
- continued -
DDR2-667
Symbol
Unit
Note
Parameter
CAS to CAS command delay
min
max
tCCD
tWR
2
tCK
ns
Write recovery time
15
-
-
-
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
tWTR
tRTP
WR+tRP
tCK
ns
7.5
7.5
ns
tXSNR
tXSRD
tXP
tRFC + 10
ns
200
2
-
-
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
tXARD
2
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
7 - AL
tCK
CKE minimum pulse width
(high and low pulse width)
tCKE
tAOND
tAON
3
2
tCK
tCK
ns
ODT turn-on delay
2
tAC(max)
+0.7
ODT turn-on
tAC(min)
2tCK+
tAC(max)+1
tAONPD
ODT turn-on(Power-Down mode)
tAC(min)+2
ns
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
tCK
ns
tAC(min)
tAC(max)+ 0.6
tAC(min)
+2
2.5tCK+
tAC(max)+1
tAOFPD
ODT turn-off (Power-Down mode)
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
tCK
tCK
ns
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tIH
ns
tREFI
tREFI
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G831(L)F).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 1.2 / Sep. 2005
17
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PACKAGE OUTLINE
128Mx64 - HYMP112S64[P]8
Front
67.60
2.00 Min
Side
3.8 max
4.00 +/-0.10
30.00
20.00
Detail-B
Detail-A
PIN 1
PIN 39
PIN 41
PIN 199
11.40
47.40
2.70
4.20
Back
1.00 ± 0.10
Detail-B
47.40
2.45
11.40
2.40
PIN 200
PIN 2
PIN 40 PIN 42
Detail of Contacts A
Detail of Contacts B (Front)
Detail of Contacts B (Back)
4.20
2.70±0.10
1.50
0.45±0.03
0.60
2.40±0.10
1.80
1.0±0.05
4.20
note:
1. all dimension Units are millimeters.
2. all outline dimensions and tolerances match up to the JEDEC standard.
Rev. 1.2 / Sep. 2005
18
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PACKAGE OUTLINE
256Mx64 - HYMP325S64M[P]8
Front
67.60
2.00 Min
Side
3.8 max
4.00 +/-0.10
30.00
20.00
Detail-B
Detail-A
PIN 1
PIN 39
PIN 41
PIN 199
11.40
47.40
2.70
4.20
1.00 ± 0.10
Back
Detail-B
47.40
2.45
11.40
2.40
PIN 200
PIN 2
PIN 40 PIN 42
Detail of Contacts A
Detail of Contacts B (Front)
Detail of Contacts B (Back)
4.20
2.70±0.10
1.50
0.45±0.03
0.60
2.40±0.10
1.80
1.0±0.05
4.20
note:
1. all dimension Units are millimeters.
2. all outline dimensions and tolerances match up to the JEDEC standard.
Rev. 1.2 / Sep. 2005
19
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
REVISION HISTORY
Revision
History
Date
First Version Release - Data sheet coverage is changed from an individual module
part to a component based module family.
1.0
Feb. 2005
Corrected module outline.
Mar. 2005
Apr. 2005
Sep. 2005
1.1
1.2
Added VDDL spec, corrected tDS & tDH spec values.
Added DDR2 667 Speed bin part
Rev. 1.2 / Sep. 2005
20
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