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HYMP125P72CP4-S5 [HYNIX]

240pin Registered DDR2 SDRAM DIMMs; 注册240PIN DDR2 SDRAM DIMM内存模块
HYMP125P72CP4-S5
型号： HYMP125P72CP4-S5
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

240pin Registered DDR2 SDRAM DIMMs
注册240PIN DDR2 SDRAM DIMM内存模块

动态存储器 双倍数据速率
文件： 总32页 (文件大小：509K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C  
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2  
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb  
version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width  
form factor of industry standard. It is suitable for easy interchange and addition.  
FEATURES  
•
JEDEC standard Double Data Rate2 Synchro-  
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-  
0.1V Power Supply  
•
•
Fully differential clock operations (CK & CK)  
Programmable Burst Length 4 / 8 with both  
sequential and interleave mode  
•
All inputs and outputs are compatible with  
SSTL_1.8 interface  
•
•
•
•
•
•
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
•
•
•
•
•
8 Bank architecture  
Serial presence detect with EEPROM  
DDR2 SDRAM Package: 60 ball(x4/x8)  
133.35 x 30.00 mm form factor  
RoHS compliant  
Posted CAS  
Programmable CAS Latency 3, 4, 5, 6  
OCD (Off-Chip Driver Impedance Adjustment)  
ODT (On-Die Termination)  
ORDERING INFORMATION  
# of  
DRAMs  
# of  
ranks  
Parity  
Support  
Part Name  
Density  
Organization  
HYMP112P72CP8-C4/Y5/S6/S5  
HYMP125P72CP8-C4/Y5/S6/S5  
HYMP125P72CP4-C4/Y5/S6/S5  
HYMP151P72CP8-C4/Y5/S6/S5  
HYMP151P72CP4-C4/Y5/S6/S5  
HYMP31GP72CMP4-C4/Y5  
HYMP112R72CP8-E3/C4  
1GB  
2GB  
2GB  
4GB  
4GB  
8GB  
1GB  
2GB  
4GB  
128Mx72  
256Mx72  
256Mx72  
512Mx72  
512Mx72  
512Mx72  
128Mx72  
256Mx72  
512Mx72  
9
1
2
1
4
2
4
1
1
2
O
O
O
O
O
O
X
18  
18  
36  
36  
72  
9
HYMP125R72CP4-E3/C4  
18  
36  
X
HYMP151R72CP4-E3/C4  
X
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.7 / Jun. 2009  
1
1240pin Registered DDR2 SDRAM DIMMs  
SPEED GRADE & KEY PARAMETERS  
E3  
C4  
Y5  
S6  
S5  
Unit  
(DDR2-400)  
(DDR2-533)  
(DDR2-667)  
(DDR2-800)  
(DDR2-800)  
Speed@CL3  
Speed@CL4  
Speed@CL5  
Speed@CL6  
CL-tRCD-tRP  
400  
400  
533  
-
400  
533  
667  
-
-
400  
533  
800  
-
Mbps  
Mbps  
Mbps  
Mbps  
tCK  
-
533  
667  
800  
6-6-6  
-
-
-
3-3-3  
4-4-4  
5-5-5  
5-5-5  
ADDRESS TABLE  
# of  
DRAMs  
Refresh  
Method  
Density Organization Ranks  
SDRAMs  
# of row/bank/column Address  
1GB  
2GB  
2GB  
4GB  
4GB  
8GB  
128M x 72  
256M x 72  
256M x 72  
512M x 72  
512M x 72  
1G x 72  
1
2
1
4
2
4
128Mb x 8  
128Mb x 8  
256Mb x 4  
128Mb x 8  
256Mb x 4  
256Mb x 4  
9
14(A0~A13)/3(BA0~BA2)/10(A0~A9)  
14(A0~A13)/3(BA0~BA2)/10(A0~A9)  
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)  
14(A0~A13)/3(BA0~BA2)/10(A0~A9)  
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)  
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)  
8K / 64ms  
8K / 64ms  
8K / 64ms  
8K / 64ms  
8K / 64ms  
8K / 64ms  
18  
18  
36  
36  
72  
Rev. 0.7 / Jun. 2009  
2
1240pin Registered DDR2 SDRAM DIMMs  
Input/Output Functional Description  
Symbol  
Type  
Polarity  
Pin Description  
Positive  
Edge  
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.  
CK0  
IN  
Negative  
Edge  
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.  
CK0  
IN  
IN  
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-  
ing the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.  
CKE[1:0]  
Active High  
Enables the associated DDR2 SDRAM command decoder when low and disables the command  
S[1:0]  
IN  
Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous  
operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1  
ODT[1:0]  
RAS, CAS, WE  
Vref  
IN  
IN  
Active High On-Die Termination signals.  
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the  
command being entered.  
Active Low  
Supply  
Supply  
IN  
Reference voltage for SSTL18 inputs  
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current  
DDR2 unbuffered DIMM designs, V  
V
DDQ  
shares the same power plane as V pins.  
DDQ  
DD  
BA[2:0]  
-
-
Selects which DDR2 SDRAM internal bank of Eight is activated.  
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)  
During a Read or Write command cycle, Address input defines the column address when sampled at the  
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used  
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autopre-  
charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is dis-  
abled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which  
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn  
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.  
A[9:0],A10/AP  
A[13:11]  
IN  
DQ[63:0],  
CB[7:0]  
Data and Check Bit Input/Output pins.  
IN  
IN  
-
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with  
Active High that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input  
only, the DM loading matches the DQ and DQS loading.  
DM[8:0]  
Power and ground for the DDR2 SDRAM input buffers, and core logic. V and V  
pins are tied to  
DDQ  
DD  
V
,V  
Supply  
DD SS  
V
/V  
planes on these modules.  
DD DDQ  
Positive  
Edge  
Positive line of the differential data strobe for input and output data  
Negative line of the differential data strobe for input and output data  
DQS[17:0]  
DQS[17:0]  
SA[2:0]  
I/O  
I/O  
IN  
Negative  
Edge  
These signals are tied at the system planar to either V or V  
SS  
to configure the serial SPD  
DDSPD  
-
-
-
EEPROM address range.  
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be con-  
nected from the SDA bus line to V on the system planar to act as a pull up.  
SDA  
I/O  
IN  
DDSPD  
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from  
SCL to V to act as a pull up on the system board.  
SCL  
DDSPD  
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM  
supply is operable from 1.7V to 3.6V.  
VDDSPD  
Supply  
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all  
register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low  
level (the PLL will remain synchronized with the input clock)  
RESET  
IN  
Par_In  
Err_Out  
TEST  
IN  
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)  
Parity error found in the Address and Control bus  
OUT  
Used by memory bus analysis tools (unused on memory DIMMs)  
Rev. 0.7 / Jun. 2009  
3
1240pin Registered DDR2 SDRAM DIMMs  
PIN DESCRIPTION  
Pin  
Pin Description  
Pin  
Pin Description  
CK0  
CK0  
Clock Input, positive line  
Clock input, negative line  
ODT[1:0]  
VDDQ  
On Die Termination Inputs  
DQs Power Supply  
Data Input/Output  
CKE0~CKE1  
RAS  
Clock Enable Input  
Row Address Strobe  
Column Address Strobe  
Write Enable  
DQ0~DQ63  
CB0~CB7  
DQS(0~8)  
DQS(0~8)  
Data check bits Input/Output  
Data strobes  
CAS  
WE  
Data strobes, negative line  
S0,S1  
Chip Select Input  
DM(0~8),DQS(9~17) Data Maskes/Data strobes  
A0~A9,A11~A13  
A10/AP  
Address input  
DQS(9~17)  
RFU  
Data strobes, negative line  
Reserved for Future Use  
No Connect  
Address input/Autoprecharge  
SDRAM Bank Address  
BA0, BA1, BA2  
NC  
Memory bus test tool (Not Connected and Not  
Usable on DIMMs)  
SCL  
Serial Presence Detect (SPD) Clock Input  
SPD Data Input/Output  
TEST  
SDA  
VDD  
VDDQ  
VSS  
Core Power  
2
SA0~SA2  
Par_In  
I/O Power Supply  
Ground  
E PROM Address Inputs  
Parity bit for the Address and Control bus  
Parity error found on the Addre  
Reset Enable  
Err_Out  
RESET  
CB0~CB7  
VREF  
Reference Power Supply  
Power Supply for SPD  
VDDSPD  
Data Strobe Inputs/Outputs  
PIN LOCATION  
Front Side  
Back Side  
pin #1  
Pin #64 Pin #65  
Pin #120  
pin #240  
Pin #185  
Pin #184  
Pin #121  
Rev. 0.7 / Jun. 2009  
4
1240pin Registered DDR2 SDRAM DIMMs  
PIN ASSIGNMENT  
Pin  
1
Name  
VREF  
VSS  
Pin  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
Name  
VSS  
Pin  
81  
Name  
DQ33  
VSS  
Pin  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
Name  
VSS  
Pin  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
Name  
CB4  
Pin  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
Name  
VSS  
2
CB0  
82  
DQ4  
CB5  
DM4/DQS13  
DQS13  
VSS  
3
DQ0  
CB1  
83  
DQS4  
DQS4  
VSS  
DQ5  
VSS  
4
DQ1  
VSS  
84  
VSS  
DM8,DQS17  
DQS17  
VSS  
5
VSS  
DQS8  
DQS8  
VSS  
85  
DM0/DQS9  
DQS9  
VSS  
DQ38  
6
DQS0  
DQS0  
VSS  
86  
DQ34  
DQ35  
VSS  
DQ39  
7
87  
CB6  
VSS  
8
CB2  
88  
DQ6  
CB7  
DQ44  
9
DQ2  
CB3  
89  
DQ40  
DQ41  
VSS  
DQ7  
VSS  
DQ45  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
DQ3  
VSS  
90  
VSS  
VDDQ  
NC,CKE1  
VDD  
VSS  
VSS  
VDDQ  
CKE0  
VDD  
91  
DQ12  
DQ13  
VSS  
DM5/DQS14  
DQS14  
VSS  
DQ8  
92  
DQS5  
DQS5  
VSS  
DQ9  
93  
A15,NC  
A14,NC  
VDDQ  
A12  
VSS  
BA2,NC  
NC, Err_Out  
VDDQ  
A11  
94  
DM1/DQS10  
DQS10  
VSS  
DQ46  
DQS1  
DQS1  
VSS  
95  
DQ42  
DQ43  
VSS  
DQ47  
96  
VSS  
97  
RFU  
A9  
DQ52  
RESET  
NC  
A7  
98  
DQ48  
DQ49  
VSS  
RFU  
VDD  
DQ53  
VDD  
99  
VSS  
A8  
VSS  
VSS  
A5  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
DQ14  
DQ15  
VSS  
A6  
RFU  
DQ10  
DQ11  
VSS  
A4  
SA2  
VDDQ  
A3  
RFU  
VDDQ  
A2  
NC(TEST)  
VSS  
VSS  
DQ20  
DQ21  
VSS  
A1  
DM6/DQS15  
NC,DQS15  
VSS  
DQ16  
DQ17  
VSS  
VDD  
DQS6  
DQS6  
VSS  
VDD  
Key  
Key  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
VSS  
VSS  
DM2/DQS11  
DQS11  
VSS  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
CK0  
CK0  
DQ54  
DQS2  
DQS2  
VSS  
DQ50  
DQ51  
VSS  
DQ55  
VDD  
VDD  
A0  
VSS  
NC, Err_Out  
VDD  
DQ22  
DQ23  
VSS  
DQ60  
DQ18  
DQ19  
VSS  
DQ56  
DQ57  
VSS  
VDD  
BA1  
DQ61  
A10/AP  
BA0  
VSS  
DQ28  
DQ29  
VSS  
VDDQ  
RAS  
DM7/DQS16  
NC,DQS16  
VSS  
DQ24  
DQ25  
VSS  
VDDQ  
WE  
DQS7  
DQS7  
VSS  
S0  
CAS  
DM3/DQS12  
DQS12  
VSS  
VDDQ  
ODT0  
A13,NC  
VDD  
VSS  
DQ62  
DQS3  
DQS3  
VSS  
VDDQ  
NC, S1  
NC, ODT1  
VDDQ  
VSS  
DQ58  
DQ59  
VSS  
DQ63  
VSS  
DQ30  
DQ31  
VSS  
VDDSPD  
SA0  
DQ26  
DQ27  
SDA  
SCL  
DQ36  
DQ37  
SA1  
DQ32  
NC= No Connect, RFU= Reserved for Future Use.  
Note:  
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.  
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.  
3. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)  
Rev. 0.7 / Jun. 2009  
5
1240pin Registered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
1GB(128Mbx72) : HYMP112[R,P]72CP8  
RS0  
DQS0  
DQS4  
DQS0  
DQS4  
DM0/DQS9  
DM4/DQS13  
DQS9  
DQS13  
DM/ NU/  
CS DQS DQS  
DM/ NU/  
CS DQS DQS  
RDQS RDQS  
RDQS RDQS  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ32  
DQ33  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
D0  
D4  
Serial PD  
SCL  
SDA  
DQS1  
DQS5  
DQS1  
DM1/DQS10  
DQS10  
DQS5  
DM5/DQS14  
DQS14  
WP A0 A1 A2  
SA0 SA1 SA2  
DM/ NU/  
CS DQS DQS  
DM/ NU/  
CS DQS DQS  
RDQS RDQS  
RDQS RDQS  
VDDSPD  
VDD/VDDQ  
VREF  
SPD  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ8  
DQ9  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
D0–D8  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
D1  
D5  
D0–D8  
VSS  
D0–D8  
Note:  
1. DQ-to-I/O wiring may be changed within a nibble.  
DQS2  
DQS6  
2. Unless otherwise noted, resistor values are 22 Ohms ± 5%.  
DQS2  
DQS6  
DM2/DQS11  
DM6/DQS15  
DQS11  
DQS15  
DM/ NU/  
CS DQS DQS  
DM/ NU/  
CS DQS DQS  
RDQS RDQS  
RDQS RDQS  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
D2  
D6  
DQS3  
DQS7  
DQS3  
DQS7  
DM3DQS12  
DM7/DQS16  
DQS12  
DQS16  
DM/ NU/  
CS DQS DQS  
DM/ NU/  
CS DQS DQS  
RDQS RDQS  
RDQS RDQS  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
D3  
D7  
DQS8  
DQS8  
DM8/DQS17  
DQS17  
DM/ NU/  
CS DQS DQS  
RDQS RDQS  
The resistors on Par_In,A13,A14,A15,BA2 and the  
signal line of Err_Out refer to the section:  
“Register Options for Unused Address inputs”  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
Signals for Address and Command Parity Function  
Register  
D8  
Vss  
C0  
VSS  
C1  
PAR_IN  
100KΩ  
PPO  
PAR_IN  
QERR  
Err_Out  
S0*  
RS0 -> CS: SDRAMs D0-D8  
1:2  
R
E
G
I
S
T
R
E
BA0-BA2**  
A0-A15**  
RAS  
RBA-RBA2 -> BA0-BA2: SDRAMs D0-D8  
RA0-RA15 -> A0-A15: SDRAMs D0-D8  
RRAS -> RAS: SDRAMs D0-D8  
RCAS -> CAS: SDRAMs D0-D8  
RWE -> WE: SDRAMs D0-D8  
CK0  
CK0  
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D8  
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D8  
PCK7 -> CK: Register  
CAS  
WE  
OE  
CKE0  
ODT1  
RCKE0 -> CKE0: SDRAMs D0-D8  
RODT0 -> ODT0: SDRAMs D0-D8  
RESET  
PCK7 -> CK: Register  
RST  
RESET  
PCK7  
* S0 connects to DCS of VDD connects to CSR on the register. S1, CKE1 and ODT1 are NC.  
** A13-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.  
PCK7  
Rev. 0.7 / Jun. 2009  
6
1240pin Registered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
2GB(256Mbx72): HYMP125P72CP8  
RS1  
RS0  
DQS0  
DQS0  
DM0/DQS9  
DQS9  
DQS4  
DQS4  
DM4/DQS13  
DQS13  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
D0  
D9  
D4  
D13  
DQS1  
DQS1  
DM1/DQS10  
DQS10  
DQS5  
DQS5  
DM5/DQS14  
DQS14  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ8  
DQ9  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ40  
DQ41  
DQ42  
DQ43  
DQ40  
DQ41  
DQ42  
DQ43  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
D1  
D10  
D5  
D14  
DQS2  
DQS2  
DM2/DQS11  
DQS11  
DQS6  
DQS6  
DM6/DQS15  
DQS15  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
I/O 0  
I/O 0  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D2  
D11  
D6  
D15  
DQS3  
DQS3  
DM3/DQS12  
DQS12  
DQS7  
DQS7  
DM7/DQS16  
DQS16  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
I/O 0  
I/O 0  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 0  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D3  
D12  
D7  
D16  
DQS8  
DQS8  
Serial PD  
VDDSPD  
SPD  
DM8DQS17  
DQS17  
D0–D17  
SCL  
SDA  
VDD/VDDQ  
VREF  
WP A0 A1 A2  
SA0 SA1 SA2  
D0–D17  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
DM/ NU/  
RDQS RDQS  
CS DQS DQS  
V
SS  
D0–D17  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
CK0  
CK0  
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D17  
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D17  
PCK7 -> CK: Register  
D8  
D17  
OE  
RESET  
PCK7 -> CK: Register  
Signals for Address and Command Parity Function  
Register A Register B  
S0*  
S1*  
RS0 -> CS: SDRAMs D0-D8  
RS1 -> CS: SDRAMs D9-D17  
1:2  
R
E
G
I
Vss  
VDD  
C0  
VDD  
C0  
C1  
VDD  
C1  
BA0-BA2***  
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D17  
RA0-RA15 -> A0-A15: SDRAMs D0-D17  
RRAS -> RAS: SDRAMs D0-D17  
RCAS -> CAS: SDRAMs D0-D17  
RWE -> WE: SDRAMs D0-D17  
PAR_IN  
PPO  
PPO  
PAR_IN  
PAR_IN  
A0-A15***  
RAS  
100KΩ  
QERR  
QERR  
Err_Out  
CAS  
S
T
The resistors on Par_In,A13,A14,A15,BA2 and the signal line of Err_Out refer to  
the section: “Register Options for Unused Address inputs”  
WE  
R
E
CKE0  
CKE1  
ODT0  
ODT1  
RCKE0 -> CKE0: SDRAMs D0-D8  
RCKE1 -> CKE0: SDRAMs D9-D17  
RODT0 -> ODT0: SDRAMs D0-D8  
RODT1 -> ODT0: SDRAMs D9-D17  
Note:  
1. DQ-to-I/O wiring may be changed within a byte.  
R
2. Unless otherwise noted, resistor values are 22 Ohms ± 5%.  
3. RS0 and RS1 alternate between the back and front sides of the DIMM.  
RST  
RESET**  
PCK7**  
* S0 connects to DCS and S1 connects to CSR on Registers. S1 connects to DCS and S0 connects to CSR on another Register.  
** RESET, PCK7 and PCK7 connect to both Registers. Other signals connect to one of two Registers.  
*** A13-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.  
PCK7**  
Rev. 0.7 / Jun. 2009  
7
1240pin Registered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
2GB(256Mbx72): HYMP125[R,P]72CP4  
VSS  
RS0  
DQS0  
DQS0  
DQS9  
DQS9  
Serial PD  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
SCL  
SDA  
DQ0  
DQ1  
DQ2  
DQ4  
DQ5  
DQ6  
WP A0 A1 A2  
SA0 SA1 SA2  
D0  
D9  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
DQ3  
DQS1  
DQ7  
DQS9  
DQS1  
DQS9  
VDDSPD  
SPD  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
D0–D17  
VDD/VDDQ  
VREF  
DQ8  
DQ12  
DQ13  
DQ14  
DQ15  
DQS11  
D0–D17  
D1  
D10  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
DQ9  
DQ10  
DQ11  
DQS2  
V
SS  
D0–D17  
I/O 3  
I/O 3  
DQS2  
DQS11  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
CK0  
CK0  
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D17  
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D17  
PCK7 -> CK: Register  
DQ16  
DQ20  
DQ21  
DQ22  
DQ23  
DQS12  
D2  
D11  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
DQ17  
DQ18  
DQ19  
DQS3  
I/O 3  
I/O 3  
OE  
RESET  
PCK7 -> CK: Register  
DQS3  
DQS12  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ24  
DQ28  
DQ29  
DQ30  
DQ31  
DQS13  
Note:  
D3  
D12  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
DQ25  
DQ26  
DQ27  
DQS4  
1. DQ-to-I/O wiring may be changed within a nibble.  
I/O 3  
I/O 3  
2. Unless otherwise noted, resistor values are 22 Ohms ± 5%.  
DQS4  
DQS13  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ32  
DQ36  
D4  
D13  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
DQ33  
DQ34  
DQ35  
DQS5  
DQ37  
DQ38  
DQ39  
* S0 connects to DCS of Register A and CSR of Register B.  
CSR of Register A and DCS of Register B connects to VDD.  
DQS14  
DQS5  
DQS14  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect  
to one of two Registers.  
DQ40  
DQ44  
DQ45  
DQ46  
DQ47  
DQS15  
D5  
D14  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
DQ41  
DQ42  
DQ43  
DQS6  
*** A13-15, BA2 have the optional pull down resistors (100K ohms), which is  
not indicated here.  
I/O 3  
I/O 3  
DQS6  
DQS15  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ52  
D6  
D15  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
DQ49  
DQ50  
DQ51  
DQS7  
DQ53  
DQ54  
DQ55  
DQS16  
DQS7  
DQS16  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ60  
D7  
D16  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
DQ57  
DQ58  
DQ59  
DQS8  
DQ61  
DQ62  
DQ63  
DQS17  
DQS8  
DQS17  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
D8  
D17  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
The resistors on Par_In,A13,A14,A15,BA2 and the signal line of Err_Out refer to  
the section:  
“Register Options for Unused Address inputs”  
S0*  
RS0 -> CS: SDRAMs D0-D17  
1:2  
R
E
G
I
S
T
R
E
BA0-BA2***  
A0-A15***  
RAS  
RBA-RBA2 -> BA0-BA2: SDRAMs D0-D17  
RA0-RA15 -> A0-A15: SDRAMs D0-D17  
RRAS -> RAS: SDRAMs D0-D17  
RCAS -> CAS: SDRAMs D0-D17  
RWE -> WE: SDRAMs D0-D17  
Signals for Address and Command Parity Function  
CAS  
Register A  
Register B  
Vss  
VDD  
C0  
C1  
VDD  
VDD  
C0  
C1  
WE  
CKE0  
RCKE0 -> CKE0: SDRAMs D0-D17  
RODT0 -> ODT0: SDRAMs D0-D17  
PAR_IN  
PPO  
PPO  
PAR_IN  
PAR_IN  
ODT1  
100KΩ  
QERR  
QERR  
Err_Out  
RST  
RESET**  
PCK7**  
PCK7**  
Rev. 0.7 / Jun. 2009  
8
1240pin Registered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
4GB(512Mbx72): HYMP151P72CP8  
RDOT0  
RCKE0  
RDOT1  
RCKE1  
RS0  
RS2  
RS1  
RS3  
Serial PD  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS0  
DQS0  
DQ7-0  
DM0  
SCL  
SDA  
WP A0 A1 A2  
SA0 SA1 SA2  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D18  
D19  
D20  
D21  
D22  
D23  
D24  
D25  
D26  
D9  
D27  
D28  
D29  
D30  
D31  
D32  
D33  
D34  
D35  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS1  
DQS1  
DQ15-8  
DM1  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
VDDSPD  
VDD/VDDQ  
VREF  
SPD  
D0–D35  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS2  
DQS2  
DQ23-16  
DM2  
D0–D35  
VSS  
D0–D35  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS3  
DQS3  
DQ31-24  
DM3  
CK0  
CK0  
PCK0-PCK6, PCK8,PCK9  
-> CK: SDRAMs D0-D35  
P
L
L
PCK0-PCK6, PCK8, PCK9  
-> CK: SDRAMs D0-D35  
PCK7 -> CK: Register  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS4  
DQS4  
CB7-0  
DM8  
PCK7 -> CK: Register  
OE  
RESET  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS4  
DQS4  
DQ39-32  
DM4  
Signals for Address and Command  
Parity Function  
Register A1  
Vss  
VDD  
C0  
C1  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS5  
DQS5  
DQ47-40  
DM5  
PPO  
PAR_IN  
QERR  
Register B1  
VDD  
VDD  
C0  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS6  
DQS6  
DQ55-48  
DM6  
C1  
PPO  
PAR_IN  
QERR  
Err_Out  
Register A2  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS  
DQS  
DQ7-0  
DM  
DQS7  
DQS7  
DQ63-56  
DM7  
Vss  
VDD  
C0  
C1  
PPO  
PAR_IN  
QERR  
Register B2  
S0,S2*  
RS0 -> CS: SDRAMs D0-D8, RS2 -> CS: SDRAMs D18-D26  
VDD  
VDD  
C0  
C1  
S1,S3*  
RS1 -> CS: SDRAMs D9-D17,RS3 -> CS: SDRAMs D27-D35  
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35****  
RA0-RA15 -> A0-A15: SDRAMs D0-D35****  
1:2  
BA0-BA2***  
A0-A15***  
PPO  
R
E
PAR_IN  
QERR  
RAS  
CAS  
RRAS -> RAS: SDRAMs D0-D35  
RCAS -> CAS: SDRAMs D0-D35  
G
I
Register A1 and A2 share the a part of  
Addr/Cmd input signal set.  
Register B1 and B2 chare the rest part of  
Addr/Cmd input signal set.  
WE  
RWE -> WE: SDRAMs D0-D35  
S
T
CKE0  
CKE1  
ODT0  
ODT1  
RCKE0 -> CKE: SDRAMs D0-D17  
RCKE1 -> CKE: SDRAMs D18-D35  
RODT0 -> ODT0: SDRAMs D0-D8  
RODT1 -> ODT1: SDRAMs D18-D26  
The resistors on Par_In, A13, A14. A15,BA2 and  
the signal line of Err_Out refer to the section:  
The register Options for Unused Address inputs?  
E
R
RST  
RESET**  
PCK7**  
PCK7**  
* S0 (S2) connects to DCS0, S1 (S3) to DCS1 on a Register A. S1 (S3) connects to DCS and S0 (S2) connects to CSR on another pair of Register.  
* S2 and S3 have required pull up resistors (100k ohms), not indicated here.  
** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to two of four Registers.  
*** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here.  
**** For Raw Card N2, DQ stub resistor value is TBD.  
And for Raw Card N2, post register A14 and A15 are not connected to the SDRAMs.  
Rev. 0.7 / Jun. 2009  
9
1240pin Registered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
4GB(512Mbx72): HYMP151[R,P]72CP4  
VSS  
RS0  
RS1  
DQS0  
DQS0  
DQS9  
DQS9  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
D0  
D18  
D9  
D27  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
Serial PD  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
SCL  
SDA  
DQS1  
DQS1  
DQS10  
DQS10  
WP A0 A1 A2  
SA0 SA1 SA2  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ8  
DQ9  
DQ10  
DQ12  
DQ13  
DQ14  
DQ15  
D1  
D19  
D10  
D28  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
DQ11  
DQS2  
DQS2  
DQS11  
DQS11  
VDDSPD  
VDD/VDDQ  
VREF  
SPD  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
D0–D35  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
D2  
D20  
D11  
D29  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
D0–D35  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
V
SS  
D0–D35  
DQS3  
DQS3  
DQS12  
DQS12  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ30  
D3  
D21  
D12  
D30  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
DQS8  
DQS8  
DQS17  
DQS17  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
Signals for Address and Command  
Parity Function  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
D8  
D26  
D17  
D35  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
Register  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
PARIN  
PTYERR  
0Ω  
Par_In  
RS0  
RS1  
DQS4  
Register  
Err_Out  
PARIN  
PTYERR  
DQS13  
DQS13  
100KΩ  
DQS4  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
o ohm resistor on Err_Out is not populated  
for non-parity card.  
D4  
D22  
D13  
D31  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
DQS5  
DQS5  
DQS14  
DQS14  
The resistors on Par_In,A13,A14,A15,BA2  
and the signal line of Err_Out refer to the  
section:  
“Register Options for Unused Address  
input”  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
D5  
D23  
D14  
D32  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
DQS6  
DQS6  
DQS15  
DQS15  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
D6  
D24  
D15  
D33  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
DQS7  
DQS7  
DQS16  
DQS16  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
D7  
D25  
D16  
D34  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
S0*  
RS0 -> CS: SDRAMs D0-D17  
RS1 -> CS: SDRAMs D18-D35  
S1*  
CK0  
CK0  
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35  
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35  
PCK7 -> CK: Register  
1:2  
R
BA0-BA2***  
A0-A15***  
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35  
RA0-RA15 -> A0-A15: SDRAMs D0-D35  
E
RAS  
CAS  
RRAS -> RAS: SDRAMs D0-D35  
RCAS -> CAS: SDRAMs D0-D35  
OE  
RESET  
PCK7 -> CK: Register  
G
I
WE  
RWE -> WE: SDRAMs D0-D35  
Note:  
S
T
CKE0  
CKE1  
ODT0  
ODT1  
RCKE0 -> CKE0-1: SDRAMs D0-D17  
RCKE1 -> CKE0-1: SDRAMs D18-D35  
RODT0 -> ODT1: SDRAMs D0-D17  
RODT1 -> ODT1: SDRAMs D18-D35  
1. DQ-to-I/O wiring may be changed within a nibble.  
2. Unless otherwise noted, resistor values are 22 Ohms ± 5%.  
3. RS0 and RS1 alternate between the bottom and surface sides of the DIMM.  
E
R
*S0 connects to DCS and S1 command to CRS on a pair of Register, S2 connects to DCS and S0 connect to CRS on another pair of Register.  
** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to one pair of four Registers.  
RST  
RESET**  
PCK7**  
PCK7**  
*** A14-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.  
Rev. 0.7 / Jun. 2009  
10  
1240pin Registered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
8GB(1Gbx72): HYMP31GP72CMP4  
RODT0  
RCKE0  
RODT1  
RCKE1  
RODT0  
RCKE0  
RODT1  
RCKE1  
RS1  
RS0  
RS3  
RS2  
RS1  
RS0  
RS3  
RS2  
22Ω  
DQS0  
DQS  
DQS  
DQS9  
DQS  
DQS  
DQS0  
DQ3~0  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS9  
DQ7~4  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
D0  
D1  
D2  
D3  
D8  
D18  
D19  
D20  
D21  
D26  
D9  
D27  
D28  
D29  
D30  
D35  
DQS1  
DQS  
DQS  
DQS10  
DQS  
DQS  
DQS1  
DQ11~8  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS10  
DQ15~12  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
D10  
D11  
D12  
D17  
DQS2  
DQS  
DQS  
DQS11  
DQS  
DQS  
DQS2  
DQ19~26  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS11  
DQ23~20  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS3  
DQS  
DQS  
DQS12  
DQS  
DQS  
DQS3  
DQ27~24  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS12  
DQ31~28  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS8  
DQS  
DQS  
DQS17  
DQS  
DQS  
DQS8  
CB3~0  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS17  
CB7~4  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
RODT0  
RCKE0  
RODT1  
RCKE1  
RODT0  
RCKE0  
RODT1  
RCKE1  
RS1  
RS0  
RS3  
RS2  
RS1  
RS0  
RS3  
RS2  
DQS4  
DQS  
DQS  
DQS13  
DQS  
DQS  
DQS4  
DQ35~32  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS13  
DQ39~36  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
D4  
D5  
D6  
D7  
D22  
D23  
D24  
D25  
D13  
D14  
D15  
D16  
D31  
D32  
D33  
D34  
22Ω  
DQS5  
DQS  
DQS  
DQS14  
DQS  
DQS  
DQS5  
DQ43~40  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS14  
DQ47~44  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS  
DQS  
DQS  
DQS15  
DQS  
DQS  
DQS6  
DQ51~48  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS15  
DQ55~52  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS7  
DQS  
DQS  
DQS16  
DQS  
DQS  
DQS7  
DQ59~56  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
DQS16  
DQ63~60  
DQS  
DQ3~0  
DM  
DQS  
DQ3~0  
DM  
22Ω  
Register  
S0,2*  
S1,3**  
RS0 -> CS0: SDRAMs D0-D17, RS2 -> CS0: SDRAMs D18-D35  
PARIN  
PTYERR  
0Ω  
0Ω  
RS1 -> CS1: SDRAMs D0-D17, RS3 -> CS1: SDRAMs D18-D35  
RBA-RBA2 -> BA0-BA1: SDRAMs D0-D35  
PAR_IN  
ERR_OUT  
Serial PD  
Register  
PARIN  
1:2  
BA0-BA2***  
A0-A15***  
PTYERR  
100KΩ  
R
E
RA0-RA13 -> A0-A13: SDRAMs D0-D35  
SCL  
SDA  
RAS  
CAS  
RRAS -> RAS: SDRAMs D0-D35  
RCAS -> CAS: SDRAMs D0-D35  
G
I
WP A0 A1 A2  
SA0 SA1 SA2  
WE  
RWE -> WE: SDRAMs D0-D35  
CK0  
CK0  
P
PCK7 -> CK: Register  
PCK7 -> CK: Register  
S
T
CKE0  
CKE1  
ODT1  
ODT0  
RCKE0 -> CKE0-1: SDRAMs D0-D17  
RCKE1 -> CKE0-1: SDRAMs D18-D35  
RODT0 -> ODT1: SDRAMs D0-D17  
RODT1 -> ODT1: SDRAMs D18-D35  
L
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35  
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35  
L
E
R
OE  
RESET  
*S0 connects to DCS0, S1 to DCS1 on the first register, S2 connects to DCS0, S3 to DCS1 on the second register.  
RST  
RESET  
PCK7  
** S2 and S3 have required pull up resistors (100K ohms), not indicated here.  
*** A13-15, BA2 have optional pull down resistors (100K ohms), not indicated here.  
PCK7  
Rev. 0.7 / Jun. 2009  
11  
1240pin Registered DDR2 SDRAM DIMMs  
ABSOLUTE MAXIMUM DC RATINGS  
Parameter  
Symbol  
Value  
Unit  
V
Note  
V
- 1.0 ~ 2.3  
- 0.5 ~ 2.3  
- 0.5 ~ 2.3  
- 0.5 ~ 2.3  
1
1
1
1
Voltage on V pin relative to Vss  
DD  
DD  
V
V
Voltage on V  
Voltage on V  
pin relative to Vss  
pin relative to Vss  
DDQ  
DDQ  
DDL  
V
V
DDL  
V
V
V
IN, OUT  
Voltage on any pin relative to Vss  
Operating Conditions and Environmental Parameters  
Parameter  
DIMM Operating temperature (ambient)  
Storage Temperature  
Symbol  
Rating  
Units  
Notes  
o
T
0 ~ +55  
C
OPR  
o
T
-50 ~ +100  
5 to 95  
1
1
2
3
C
STG  
H
Storage Humidity (without condensation)  
%
STG  
BAR  
DIMM Barometric Pressure (operating & storage)  
DRAM Component Case Temperature Range  
105 to 69  
0 ~+95  
K Pascal  
P
o
T
C
CASE  
Note:  
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device  
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con  
ditions for extended periods may affect reliablility.  
2. Up to 9850 ft.  
3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to  
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.  
DC OPERATING CONDITIONS (SSTL_1.8)  
Rating  
Symbol  
Parameter  
Supply Voltage  
Units  
Notes  
Min.  
Typ.  
Max.  
VDD  
VDDL  
VDDQ  
VREF  
1.7  
1.8  
1.9  
V
V
1
1.7  
1.7  
1.8  
1.9  
1.9  
1,2  
1,2  
3,4  
5
Supply Voltage for DLL  
Supply Voltage for Output  
Input Reference Voltage  
Termination Voltage  
1.8  
0.50*VDDQ  
VREF  
V
0.49*VDDQ  
VREF-0.04  
1.7  
0.51*VDDQ  
VREF+0.04  
3.6  
mV  
V
VTT  
VDDSPD  
-
V
EEPROM Supply Voltage  
Note:  
1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.  
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.  
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is  
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.  
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).  
5. VTT of transmitting device must track VREF of receiving device.  
Rev. 0.7 / Jun. 2009  
12  
1240pin Registered DDR2 SDRAM DIMMs  
INPUT DC LOGIC LEVEL  
Parameter  
dc Input logic HIGH  
dc Input logic LOW  
Symbol  
VIH(DC)  
VIL(DC)  
Min  
VREF + 0.125  
-0.30  
Max  
Unit  
V
Note  
VDDQ + 0.3  
VREF - 0.125  
V
INPUT AC LOGIC LEVEL  
DDR2 400/533  
DDR2 667/800  
Parameter  
Symbol  
Unit Notes  
Min  
Max  
Min  
Max  
ac Input logic HIGH VIH(AC)  
ac Input logic LOW VIL(AC)  
V
V
VREF + 0.250  
-
-
VREF + 0.200  
-
-
VREF - 0.250  
VREF - 0.200  
AC INPUT TEST CONDITIONS  
Symbol  
VREF  
Condition  
Input reference voltage  
Value  
Units  
Notes  
0.5 * VDDQ  
V
1
VSWING(MAX)  
SLEW  
Input signal maximum peak to peak swing  
Input signal minimum slew rate  
1.0  
1.0  
V
1
V/ns  
2, 3  
Note:  
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.  
2. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the  
range from VREF min to VIL(ac) max for falling edges as shown in the below figure.  
3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions and VIH (ac) to  
VIL (ac) on the negative transitions.  
Start of Rising Edge Input Timing  
Start of Falling Edge Input Timing  
V
V
V
V
V
V
V
DDQ  
IH(ac)  
IH(dc)  
REF  
min  
min  
V
SWING(MAX)  
max  
max  
IL(dc)  
IL(ac)  
SS  
∆TR  
∆TF  
V
min - V  
REF  
V
-
V
max  
IL(ac)  
IH(ac)  
REF  
Falling Slew =  
Rising Slew =  
∆
TR  
∆
TF  
< Figure: AC Input Test Signal Waveform >  
Rev. 0.7 / Jun. 2009  
13  
1240pin Registered DDR2 SDRAM DIMMs  
Differential Input AC logic Level  
Note  
Symbol  
Parameter  
Min.  
Max.  
Units  
1
VID (ac)  
0.5  
VDDQ + 0.6  
V
ac differential input voltage  
ac differential cross point voltage  
2
VIX (ac)  
0.5 * VDDQ - 0.175  
0.5 * VDDQ + 0.175  
V
Note:  
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,  
LDQS, UDQS and UDQS.  
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS  
or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to  
V
IH(DC) - VIL(DC).  
V
DDQ  
V
TR  
Crossing point  
V
ID  
V
V
IX or OX  
V
CP  
V
SSQ  
< Differential signal levels >  
Note:  
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal  
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).  
The minimum value is equal to V IH(AC) - VIL(AC).  
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in  
VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.  
DIFFERENTIAL AC OUTPUT PARAMETERS  
Symbol  
Parameter  
Min.  
Max.  
Units  
Note  
VOX (ac)  
0.5 * VDDQ - 0.125  
0.5 * VDDQ + 0.125  
V
1
ac differential crosspoint voltage  
Note:  
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations  
in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.  
Rev. 0.7 / Jun. 2009  
14  
1240pin Registered DDR2 SDRAM DIMMs  
OUTPUT BUFFER LEVELS  
OUTPUT AC TEST CONDITIONS  
Symbol  
Parameter  
SSTL_18  
Units  
Notes  
VOTR  
Output Timing Measurement Reference Level  
0.5 * VDDQ  
V
1
Note:  
1. The VDDQ of the device under test is referenced.  
OUTPUT DC CURRENT DRIVE  
Symbol  
IOH(dc)  
IOL(dc)  
Parameter  
Output Minimum Source DC Current  
Output Minimum Sink DC Current  
SSTl_18  
- 13.4  
13.4  
Units  
mA  
Notes  
1, 3, 4  
2, 3, 4  
mA  
Note:  
1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV.  
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.  
3. The dc value of VREF applied to the receiving device is set to VTT  
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capa-  
bility to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual cur-  
rent values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for  
measurement.  
Rev. 0.7 / Jun. 2009  
15  
1240pin Registered DDR2 SDRAM DIMMs  
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°C)  
1GB: HYMP112[R,P]72CP8  
Pin  
Symbol  
Min  
Max  
Unit  
CK0, /CK0  
CCK  
CI1  
7
8
8
8
6
11  
12  
12  
12  
9
pF  
pF  
pF  
pF  
pF  
CKE, ODT  
/CS  
CI2  
Address, /RAS, /CAS, /WE  
DQ, DM, DQS, /DQS  
CI3  
CIO  
2GB: HYMP125P72CP8  
Pin  
Symbol  
Min  
Max  
Unit  
CK0, /CK0  
CCK  
CI1  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
pF  
pF  
pF  
pF  
pF  
CKE, ODT  
/CS  
CI2  
CI3  
CIO  
Address, /RAS, /CAS, /WE  
DQ, DM, DQS, /DQS  
2GB: HYMP125[R,P]72CP4  
Pin  
Symbol  
Min  
Max  
Unit  
CK0, /CK0  
CCK  
CI1  
7
8
11  
12  
15  
12  
9
pF  
pF  
pF  
pF  
pF  
CKE, ODT  
/CS  
CI2  
CI3  
10  
8
Address, /RAS, /CAS, /WE  
DQ, DM, DQS, /DQS  
CIO  
6
4GB: HYMP151P72CP8  
Pin  
Symbol  
Min  
Max  
Unit  
CK0, /CK0  
CCK  
CI1  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
pF  
pF  
pF  
pF  
pF  
CKE, ODT  
/CS  
CI2  
CI3  
CIO  
Address, /RAS, /CAS, /WE  
DQ, DM, DQS, /DQS  
Rev. 0.7 / Jun. 2009  
16  
1240pin Registered DDR2 SDRAM DIMMs  
4GB: HYMP151[R,P]72CP4  
Pin  
Symbol  
Min  
Max  
Unit  
CK0, /CK0  
CCK  
CI1  
7
11  
15  
15  
15  
15  
pF  
pF  
pF  
pF  
pF  
CKE, ODT  
10  
10  
10  
9
/CS  
CI2  
CI3  
CIO  
Address, /RAS, /CAS, /WE  
DQ, DM, DQS, /DQS  
8GB: HYMP31G[R,P]72CMP4  
Pin  
Symbol  
Min  
Max  
Unit  
CK0, /CK0  
CCK  
CI1  
7
8
11  
12  
12  
15  
22  
pF  
pF  
pF  
pF  
pF  
CKE, ODT  
/CS  
CI2  
8
Address, /RAS, /CAS, /WE  
DQ, DM, DQS, /DQS  
CI3  
CIO  
10  
18  
Note:  
1. Pins not under test are tied to GND.  
2. These value are guaranteed by design and tested on a sample basis only.  
Rev. 0.7 / Jun. 2009  
17  
1240pin Registered DDR2 SDRAM DIMMs  
IDD SPECIFICATIONS (TCASE: 0 to 95oC)  
1GB, 128M x 72 Registered DIMM: HYMP112[R,P]72CP8  
E3  
C4  
Y5  
S5 /S6  
Symbol  
Unit Note  
(DDR2 400@CL3)  
(DDR2 533@CL4)  
(DDR2 667@CL5) (DDR2 800@CL5&6)  
IDD0  
IDD1  
1190  
1280  
740  
1235  
1325  
740  
1280  
1370  
740  
1325  
1415  
740  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P(F)  
IDD3P(S)  
IDD3N  
IDD4R  
IDD4W  
IDD5B  
IDD6  
848  
893  
920  
938  
920  
965  
1010  
875  
1055  
875  
830  
830  
758  
758  
758  
758  
965  
1055  
1775  
1775  
2135  
540  
1100  
2045  
2000  
2225  
540  
1145  
2270  
2180  
2270  
540  
1550  
1550  
2135  
540  
mA  
mA  
1
IDD7  
2135  
2225  
2450  
2765  
2GB, 256M x 72 Registered DIMM: HYMP125P72CP8  
E3  
C4  
Y5  
S5 /S6  
Symbol  
Unit Note  
(DDR2 400@CL3)  
(DDR2 533@CL4)  
(DDR2 667@CL5) (DDR2 800@CL5&6)  
IDD0  
IDD1  
1460  
1550  
830  
1550  
1640  
830  
1640  
1730  
830  
1730  
1820  
830  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P(F)  
IDD3P(S)  
IDD3N  
IDD4R  
IDD4W  
IDD5B  
IDD6  
1046  
1190  
1010  
866  
1136  
1280  
1010  
866  
1190  
1370  
1100  
866  
1226  
1460  
1100  
866  
1280  
1820  
1820  
2405  
630  
1460  
2090  
2090  
2450  
630  
1550  
2405  
2360  
2585  
630  
1640  
2675  
2585  
2675  
630  
mA  
mA  
1
IDD7  
2405  
2540  
2810  
3170  
Note: 1. IDD6 current values are guaranteed up to Tcase of 85°C max.  
Rev. 0.7 / Jun. 2009  
18  
1240pin Registered DDR2 SDRAM DIMMs  
2GB, 256M x 72 Registered DIMM: HYMP125[R,P]72CP4  
E3  
C4  
Y5  
S5 /S6  
Symbol  
Unit Note  
(DDR2 400@CL3)  
(DDR2 533@CL4)  
(DDR2 667@CL5) (DDR2 800@CL5&6)  
IDD0  
IDD1  
1730  
1910  
830  
1820  
2000  
830  
1910  
2090  
830  
2000  
2180  
830  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P(F)  
IDD3P(S)  
IDD3N  
IDD4R  
IDD4W  
IDD5B  
IDD6  
1046  
1190  
1010  
866  
1136  
1280  
1010  
866  
1190  
1370  
1100  
866  
1226  
1460  
1100  
866  
1280  
2450  
2450  
3620  
630  
1460  
2900  
2900  
3620  
630  
1550  
3440  
3600  
3800  
630  
1640  
3890  
3710  
3690  
630  
mA  
mA  
1
IDD7  
3620  
3800  
4250  
4880  
4GB, 512M x 72 Registered DIMM: HYMP151P72CP8  
E3  
C4  
Y5  
S5 /S6  
Symbol  
Unit Note  
(DDR2 400@CL3)  
(DDR2 533@CL4)  
(DDR2 667@CL5) (DDR2 800@CL5&6)  
IDD0  
IDD1  
2000  
2090  
1010  
1442  
1730  
1370  
1082  
1910  
2360  
2360  
2945  
810  
2180  
2270  
1010  
1622  
1910  
1370  
1082  
2270  
2720  
2720  
3080  
810  
2360  
2450  
1010  
1730  
1090  
1550  
1082  
2450  
3125  
3080  
3305  
810  
2540  
2630  
1010  
1802  
2270  
1550  
1082  
2630  
3485  
3395  
3485  
810  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P(F)  
IDD3P(S)  
IDD3N  
IDD4R  
IDD4W  
IDD5B  
IDD6  
mA  
mA  
1
IDD7  
2945  
3170  
3530  
3980  
Note: 1. IDD6 current values are guaranteed up to Tcase of 85°C max.  
Rev. 0.7 / Jun. 2009  
19  
1240pin Registered DDR2 SDRAM DIMMs  
4GB, 512M x 72 Registered DIMM: HYMP151[R,P]72CP4  
E3  
C4  
Y5  
S5 /S6  
Symbol  
Unit Note  
(DDR2 400@CL3)  
(DDR2 533@CL4)  
(DDR2 667@CL5) (DDR2 800@CL5&6)  
IDD0  
IDD1  
2270  
2450  
1010  
1442  
1730  
1370  
1082  
1910  
2990  
2990  
4160  
810  
2450  
2630  
1010  
1622  
1910  
1370  
1082  
2270  
3530  
3530  
4250  
810  
2630  
2810  
1010  
1730  
2090  
1550  
1082  
2450  
4160  
4070  
4520  
810  
2810  
2990  
1010  
1802  
2270  
1550  
1082  
2630  
4700  
1520  
4700  
810  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P(F)  
IDD3P(S)  
IDD3N  
IDD4R  
IDD4W  
IDD5B  
IDD6  
mA  
mA  
1
IDD7  
4160  
4430  
4970  
5690  
8GB, 1G x 72 Registered DIMM: HYMP31G[R,P]72CMP4  
C4  
Y5  
Symbol  
Unit  
Note  
(DDR2 533@CL4)  
(DDR2 667@CL5)  
IDD0  
IDD1  
3710  
3890  
1370  
2594  
3170  
2090  
1514  
3890  
4790  
4790  
5510  
1170  
5690  
4070  
4250  
1370  
2810  
3530  
2450  
1514  
4250  
5600  
5510  
5960  
1170  
6410  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P(F)  
IDD3P(S)  
IDD3N  
IDD4R  
IDD4W  
IDD5B  
IDD6  
1
IDD7  
Note: 1. IDD6 current values are guaranteed up to Tcase of 85°C max.  
Rev. 0.7 / Jun. 2009  
20  
1240pin Registered DDR2 SDRAM DIMMs  
IDD Measurement Conditions  
Symbol  
Conditions  
Units  
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RASmin (IDD);  
CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs  
are SWITCHING  
mA  
IDD0  
IDD1  
Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;  
t
t
t
t
t
t
t
t
CK = CK(IDD), RC = RC (IDD), RAS = RASmin (IDD), RCD = RCD(IDD); CKE is HIGH, CS is HIGH  
between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W  
mA  
t
t
Precharge power-down current; All banks idle; CK = CK(IDD); CKE is LOW; Other control and address  
IDD2P  
IDD2Q  
IDD2N  
mA  
mA  
mA  
bus inputs are STABLE; Data bus inputs are FLOATING  
t
t
Precharge quiet standby current; All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control  
and address bus inputs are STABLE; Data bus inputs are FLOATING  
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and  
address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
t
t
mA  
mA  
Active power-down current; All banks open; CK = CK(IDD); CKE is LOW;  
Other control and address bus inputs are STABLE; Data bus inputs are  
FLOATING  
Fast PDN Exit MRS(12) = 0  
Slow PDN Exit MRS(12) = 1  
IDD3P  
IDD3N  
IDD4W  
IDD4R  
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax (IDD), RP = RP(IDD); CKE is  
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data  
bus inputs are SWITCHING  
mA  
mA  
mA  
t
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK =  
t
t
t
t
t
CK(IDD), RAS = RASmax (IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands;  
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),  
t
t
t
t
t
t
AL = 0; CK = CK(IDD), RAS = RASmax (IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid  
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W  
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is  
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are  
SWITCHING  
IDD5B  
IDD6  
mA  
mA  
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃max.  
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL  
t
t
t
t
t
t
t
t
t
t
= RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is  
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-  
tern is same as IDD4R; - Refer to the following page for detailed timing conditions  
IDD7  
mA  
Note:  
1. IDD specifications are tested after the device is properly initialized  
2. Input slew rate is specified by AC Parametric Test Condition  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations  
of EMRS bits 10 and 11.  
5. Definitions for IDD  
LOW is defined as Vin ≤ VILAC (max)  
HIGH is defined as Vin ≥ VIHAC (min)  
STABLE is defined as inputs stable at a HIGH or LOW level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and con-  
trol signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including  
masks or strobes  
Rev. 0.7 / Jun. 2009  
22  
1240pin Registered DDR2 SDRAM DIMMs  
Electrical Characteristics & AC Timings  
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin  
Speed  
Bin (CL-tRCD-tRP)  
Parameter  
CAS Latency  
tRCD  
DDR2-800 (S5)  
DDR2-667 (Y5)  
DDR2-533 (C4)  
DDR2-400 (E3)  
Unit  
4-4-4  
min  
4
3-3-3  
min  
3
5-5-5  
min  
5
5-5-5  
min  
5
ns  
ns  
ns  
ns  
ns  
15  
15  
12.5  
12.5  
57.5  
45  
15  
tRP  
15  
15  
15  
tRC  
60  
55  
60  
tRAS  
45  
40  
45  
AC Timing Parameters by Speed Grade (DDR2-400 & DDR2-533)  
DDR2-400  
DDR2-533  
Parameter  
Symbol  
Unit Note  
Min  
-600  
-500  
0.45  
0.45  
Max  
600  
Min  
Max  
500  
Data-Out edge to Clock edge Skew  
DQS-Out edge to Clock edge Skew  
Clock High Level Width  
tAC  
tDQSCK  
tCH  
-500  
-500  
0.45  
0.45  
ps  
ns  
500  
450  
0.55  
0.55  
0.55  
0.55  
CK  
CK  
Clock Low Level Width  
tCL  
min  
(tCL, tCH)  
min  
(tCL, tCH)  
Clock Half Period  
tHP  
-
-
ns  
ps  
System Clock Cycle Time  
tCK  
tDS  
5000  
150  
275  
0.6  
8000  
3750  
100  
225  
0.6  
8000  
DQ and DM input setup time  
-
-
-
-
-
-
ps  
ps  
1
1
DQ and DM input hold time  
tDH  
tIPW  
Control & Address input Pulse Width for each input  
tCK  
DQ and DM input pulse width for each input pulse width for  
each input  
tDIPW  
tHZ  
0.35  
-
-
0.35  
-
-
tCK  
ps  
tAC max  
tAC max  
Data-out high-impedance window from CK, /CK  
DQS low-impedance time from CK/CK  
DQ low-impedance time from CK/CK  
DQS-DQ skew for DQS and associated DQ signals  
DQ hold skew factor  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tQHS  
tAC min  
tAC max  
tAC min  
tAC max  
ps  
ps  
2*tAC min  
tAC max  
2*tAC min  
tAC max  
-
350  
-
300  
ps  
-
tHP - tQHS  
WL - 0.25  
0.35  
450  
-
tHP - tQHS  
WL - 0.25  
0.35  
400  
ps  
DQ/DQS output hold time from DQS  
Write command to first DQS latching transition  
DQS input high pulse width  
tQH  
-
-
ps  
tDQSS  
tDQSH  
tDQSL  
tDSS  
WL + 0.25  
WL + 0.25  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
-
-
-
-
-
-
-
-
-
-
-
-
DQS input low pulse width  
0.35  
0.35  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
Write preamble  
0.2  
0.2  
tDSH  
0.2  
0.2  
tMRD  
2
2
tWPRE  
0.35  
0.35  
Rev. 0.7 / Jun. 2009  
23  
1240pin Registered DDR2 SDRAM DIMMs  
DDR2-400  
DDR2-533  
Parameter  
Symbol  
Unit Note  
Min  
Max  
Min  
Max  
Write postamble  
tWPST  
tIS  
0.4  
350  
475  
0.9  
0.6  
0.4  
250  
375  
0.9  
0.6  
tCK  
ps  
Address and control input setup time  
Address and control input hold time  
Read preamble  
-
-
-
-
tIH  
ps  
tRPRE  
tRPST  
tRFC  
tRRD  
1.1  
0.6  
-
1.1  
0.6  
-
tCK  
tCK  
ns  
Read postamble  
0.4  
0.4  
Auto-Refresh to Active/Auto-Refresh command period  
127.5  
7.5  
127.5  
7.5  
-
-
ns  
Row Active to Row Active Delay for 1KB page size  
Row Active to Row Active Delay for 2KB page size  
Four Activate Window for 1KB page size  
tRRD  
tFAW  
tFAW  
10  
37.5  
50  
-
-
-
10  
37.5  
50  
-
-
-
ns  
ns  
ns  
Four Activate Window for 2KB page size  
CAS to CAS command delay  
tCCD  
tWR  
2
15  
2
15  
tCK  
ns  
Write recovery time  
-
-
-
-
Auto Precharge Write Recovery + Precharge Time  
tDAL  
tWR + tRP  
tWR + tRP  
tCK  
Write to Read Command Delay  
tWTR  
10  
-
ns  
7.5  
-
Internal read to precharge command delay  
Exit self refresh to a non-read command  
Exit self refresh to a read command  
tRTP  
tXSNR  
tXSRD  
tXP  
7.5  
7.5  
ns  
ns  
tRFC + 10  
tRFC + 10  
200  
2
-
-
200  
2
-
-
tCK  
tCK  
tCK  
Exit precharge power down to any non-read command  
Exit active power down to read command  
tXARD  
2
2
Exit active power down to read command  
(Slow exit, Lower power)  
tXARDS  
tCKE  
6 - AL  
3
6 - AL  
3
tCK  
tCK  
CKE minimum pulse width  
(high and low pulse width)  
ODT turn-on delay  
ODT turn-on  
tAOND  
tAON  
2
2
2
2
tCK  
ns  
tAC (min)  
tAC(max)+1  
tAC (min)  
tAC(max)+1  
2tCK+tAC(m  
ax)+1  
2tCK+tAC(m  
ax)+1  
ODT turn-on (Power-Down mode)  
ODT turn-off delay  
tAONPD  
tAOFD  
tAOF  
tAC(min)+2  
2.5  
tAC(min)+2  
2.5  
ns  
tCK  
ns  
2.5  
2.5  
tAC (max)+  
0.6  
tAC (max)+  
0.6  
ODT turn-off  
tAC (min)  
tAC (min)  
2.5tCK+tAC(  
max)+1  
2.5tCK+tAC(  
max)+1  
ODT turn-off (Power-Down mode)  
tAOFPD  
tAC(min)+2  
tAC(min)+2  
ns  
ODT to power down entry latency  
ODT power down exit latency  
OCD drive mode output delay  
tANPD  
tAXPD  
tOIT  
3
8
0
3
8
0
tCK  
tCK  
ns  
12  
12  
Minimum time clocks remains ON after CKE  
asynchronously drops LOW  
tDelay  
tIS + tCK + tIH  
tIS + tCK + tIH  
ns  
tREFI  
tREFI  
-
-
7.8  
3.9  
-
-
7.8  
3.9  
us  
us  
2
3
Average periodic Refresh Interval  
Note:  
1. For details and notes, please refer to the relevant HYNIX component datasheet HY5PS1G[4,8]31CFP.  
2. 0°C ≤ TCASE ≤ 85°C  
3. 85°C ＜ TCASE ≤ 95°C  
Rev. 0.7 / Jun. 2009  
24  
1240pin Registered DDR2 SDRAM DIMMs  
(DDR2-667 & DDR2-800)  
DDR2-667  
DDR2-800  
Symbol  
Unit  
Note  
Parameter  
min  
-450  
-400  
0.45  
0.45  
max  
+450  
+400  
0.55  
min  
-400  
-350  
0.45  
0.45  
max  
+400  
+350  
0.55  
DQ output access time from CK/CK  
DQS output access time from CK/CK  
CK high-level width  
tAC  
tDQSCK  
tCH  
ps  
ps  
tCK  
tCK  
CK low-level width  
tCL  
0.55  
0.55  
min(tCL,  
tCH)  
min(tCL,  
tCH)  
CK half period  
tHP  
tCK  
tDS  
-
8000  
-
-
ps  
ps  
ps  
Clock cycle time, CL=x  
3000  
2500  
DQ and DM input setup time  
(differential strobe)  
100  
50  
-
-
1
1
DQ and DM input hold time  
(differential strobe)  
tDH  
175  
-
125  
ps  
Control & Address input pulse width for each input  
DQ and DM input pulse width for each input  
Data-out high-impedance time from CK/CK  
DQS low-impedance time from CK/CK  
DQ low-impedance time from CK/CK  
DQS-DQ skew for DQS and associated DQ signals  
DQ hold skew factor  
tIPW  
tDIPW  
tHZ  
0.6  
-
-
0.6  
-
-
tCK  
tCK  
ps  
0.35  
0.35  
-
tAC max  
tAC max  
tAC max  
240  
-
tAC max  
tAC max  
tAC max  
200  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tQHS  
tAC min  
tAC min  
ps  
2*tAC min  
2*tAC min  
ps  
-
-
ps  
-
340  
-
300  
ps  
DQ/DQS output hold time from DQS  
tQH  
tHP - tQHS  
-
tHP - tQHS  
-
ps  
First DQS latching transition to associated clock  
edge  
tDQSS  
- 0.25  
+ 0.25  
- 0.25  
+ 0.25  
tCK  
DQS input high pulse width  
DQS input low pulse width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
Write preamble  
tDQSH  
tDQSL  
tDSS  
0.35  
0.35  
0.2  
0.2  
2
-
-
0.35  
0.35  
0.2  
0.2  
2
-
-
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
-
-
tDSH  
-
-
tMRD  
tWPRE  
tWPST  
-
-
0.35  
0.4  
-
0.35  
0.4  
-
Write postamble  
0.6  
0.6  
Auto-Refresh to Active/Auto-Refresh command  
period  
tRFC  
tRRD  
127.5  
7.5  
-
-
127.5  
7.5  
-
-
ns  
ns  
Row Active to Row Active Delay for 1KB page size  
Address and control input setup time  
Address and control input hold time  
Read preamble  
tIS  
tIH  
200  
275  
0.9  
0.4  
45  
-
-
175  
250  
0.9  
0.4  
45  
-
-
ps  
ps  
tRPRE  
tRPST  
tRAS  
1.1  
0.6  
70000  
1.1  
0.6  
70000  
tCK  
tCK  
ns  
Read postamble  
Activate to precharge command  
Active to active command period for 1KB page size  
products  
tRRD  
7.5  
-
7.5  
-
ns  
tRRD  
10  
-
10  
-
ns  
Row Active to Row Active Delay for 2KB page size  
Four Active Window for 1KB page size products  
tFAW  
37.5  
-
35  
-
ns  
Four Activate Window for 2KB page size  
tFAW  
50  
-
50  
-
ns  
CAS to CAS command delay  
tCCD  
tWR  
2
15  
2
15  
tCK  
ns  
Write recovery time  
-
-
-
-
-
-
Auto precharge write recovery + precharge time  
Internal write to read command delay  
Internal read to precharge command delay  
tDAL  
tWTR  
tRTP  
WR+tRP  
7.5  
WR+tRP  
7.5  
tCK  
ns  
7.5  
7.5  
ns  
Rev. 0.7 / Jun. 2009  
25  
1240pin Registered DDR2 SDRAM DIMMs  
DDR2-667  
DDR2-800  
Symbol  
Unit Note  
Parameter  
min  
max  
min  
max  
Exit self refresh to a non-read command  
Exit self refresh to a read command  
tXSNR  
tXSRD  
tRFC + 10  
200  
tRFC + 10  
200  
ns  
-
-
-
-
tCK  
Exit precharge power down to any non-read  
command  
tXP  
2
2
2
2
tCK  
tCK  
tCK  
Exit active power down to read command  
tXARD  
tXARDS  
Exit active power down to read command  
(Slow exit, Lower power)  
7 - AL  
8 - AL  
CKE minimum pulse width  
(high and low pulse width)  
tCKE  
tAOND  
tAON  
3
2
3
2
tCK  
tCK  
ns  
ODT turn-on delay  
2
2
tAC (max)  
+0.7  
tAC (max)  
+0.7  
ODT turn-on  
tAC (min)  
tAC (min)  
2tCK+  
tAC (min)  
+2  
2tCK+  
ODT turn-on (Power-Down mode)  
ODT turn-off delay  
tAONPD  
tAOFD  
tAOF  
tAC(min)+2  
2.5  
ns  
tCK  
ns  
tAC(max)+1  
tAC(max)+1  
2.5  
2.5  
2.5  
tAC (max)  
+0.6  
ODT turn-off  
tAC (min)  
tAC (max)+ 0.6  
tAC (min)  
tAC (min)  
+2  
2.5tCK+  
tAC(max)+1  
tAC (min)  
+2  
2.5tCK+  
tAC(max)+1  
ODT turn-off (Power-Down mode)  
tAOFPD  
ns  
ODT to power down entry latency  
ODT power down exit latency  
OCD drive mode output delay  
tANPD  
tAXPD  
tOIT  
3
8
0
3
8
0
tCK  
tCK  
ns  
12  
12  
Minimum time clocks remains ON after CKE  
asynchronously drops LOW  
tIS + tCK  
+ tIH  
tDelay  
tIS + tCK + tIH  
ns  
tREFI  
tREFI  
-
-
7.8  
3.9  
-
-
7.8  
3.9  
us  
us  
2
3
Average periodic Refresh Interval  
Note:  
1. For details and notes, please refer to the relevant HYNIX component datasheet HY5PS1G[4,8]31CFP.  
2. 0°C ≤ TCASE ≤ 85°C  
3. 85°C ＜ TCASE ≤ 95°C  
Rev. 0.7 / Jun. 2009  
26  
1240pin Registered DDR2 SDRAM DIMMs  
DIMM OUTLINE  
128Mx72 (1 rank) - HYMP112[R,P]72CP8  
Front  
2X 3.00MIN  
4X FULL R  
17.80  
30.00  
10.00  
4X 4.0 ± 0.1  
PLL  
2X  
Ø
2.50 ±0.10  
2X 2.3 ± 0.1  
2X R1.00  
5.175  
63.0  
55.0  
5.0  
128.95  
DETAIL-A  
DETAIL-B  
133.35  
Back  
Detail of Contacts A  
Detail of Contacts B  
Side  
2.70max  
2.50  
1.0  
0.8 ± 0.05  
1.50 ± 0.10  
0.3 ± 0.7  
5.00  
1.27 ± 0.10  
Millimeters  
Inches  
Note) All dimensions are typical unless otherwise stated.  
Rev. 0.7 / Jun. 2009  
27  
1240pin Registered DDR2 SDRAM DIMMs  
DIMM OUTLINE  
256Mx72 (2 rank) - HYMP125P72CP8  
Front  
2X 3.00MIN  
4X FULL R  
17.80  
30.00  
10.00  
4X 4.0 ± 0.1  
PLL  
2X  
Ø 2.50 ±0.10  
2X 2.3 ± 0.1  
2X R1.00  
5.175  
63.0  
55.0  
5.0  
128.95  
DETAIL-A  
DETAIL-B  
133.35  
Back  
Detail of Contacts A  
Detail of Contacts B  
Side  
4.00max  
2.50  
1.0  
0.8 ± 0.05  
1.50 ± 0.10  
0.3 ± 0.7  
5.00  
1.27 ± 0.10  
Millimeters  
Inches  
Note) All dimensions are typical unless otherwise stated.  
Rev. 0.7 / Jun. 2009  
28  
1240pin Registered DDR2 SDRAM DIMMs  
DIMM OUTLINE  
256Mx72 (1 rank) - HYMP125[R,P]72CP4  
Front  
2X 3.00MIN  
4X FULL R  
17.80  
10.00  
4X 4.0 ± 0.1  
30.00  
PLL  
5.0  
2X  
Ø
2.50 ±0.10  
2X 2.3 ± 0.1  
2X R1.00  
5.175  
63.0  
55.0  
DETAIL-A  
DETAIL-B  
128.95  
133.35  
Back  
Detail of Contacts A  
Detail of Contacts B  
Side  
4.00max  
2.50  
1.0  
0.8 ± 0.05  
1.50 ± 0.10  
0.3 ± 0.7  
5.00  
1.27 ± 0.10  
Millimeters  
Inches  
Note) All dimensions are typical unless otherwise stated.  
Rev. 0.7 / Jun. 2009  
29  
1240pin Registered DDR2 SDRAM DIMMs  
DIMM OUTLINE  
512Mx72 (4 ranks) - HYMP151P72CP8  
Front  
2X 3.00MIN  
4X FULL R  
17.80  
30.00  
10.00  
4X 4.0 ± 0.1  
2X  
Ø 2.50 ±0.10  
2X 2.3 ± 0.1  
2X R1.00  
5.175  
63.0  
55.0  
5.0  
128.95  
DETAIL-A  
DETAIL-B  
133.35  
Back  
Side  
4.00max  
Detail of Contacts A  
Detail of Contacts B  
2.50  
1.0  
0.8 ± 0.05  
1.50 ± 0.10  
0.3 ± 0.7  
5.00  
1.27 ± 0.10  
Millimeters  
Inches  
Note) All dimensions are typical unless otherwise stated.  
Rev. 0.7 / Jun. 2009  
30  
1240pin Registered DDR2 SDRAM DIMMs  
DIMM OUTLINE  
512Mx72 (2 ranks) - HYMP151[R,P]72CP4  
Front  
2X 3.00MIN  
PLL  
4X FULL R  
17.80  
10.00  
4X 4.0 ± 0.1  
30.00  
2X  
Ø
2.50 ±0.10  
2X 2.3 ± 0.1  
2X R1.00  
5.175  
63.0  
55.0  
5.0  
128.95  
DETAIL-A  
DETAIL-B  
133.35  
Back  
Side  
4.00max  
Detail of Contacts A  
Detail of Contacts B  
2.50  
1.0  
0.8 ± 0.05  
1.50 ± 0.10  
0.3 ± 0.7  
5.00  
1.27 ± 0.10  
Millimeters  
Inches  
Note) All dimensions are typical unless otherwise stated.  
Rev. 0.7 / Jun. 2009  
31  
1240pin Registered DDR2 SDRAM DIMMs  
DIMM OUTLINE  
1Gx72 (4 ranks) - HYMP31GP72CMP4  
Front  
2X 3.00MIN  
4X FULL R  
17.80  
30.00  
10.00  
4X 4.0 ± 0.1  
2X  
Ø 2.50 ±0.10  
2X 2.3 ± 0.1  
2X R1.00  
5.175  
63.0  
55.0  
5.0  
128.95  
DETAIL-A  
DETAIL-B  
133.35  
Back  
Side  
7.55max  
Detail of Contacts A  
Detail of Contacts B  
2.50  
1.0  
0.8 ± 0.05  
1.50 ± 0.10  
0.3 ± 0.7  
5.00  
1.27 ± 0.10  
Millimeters  
Inches  
Note) All dimensions are typical unless otherwise stated.  
Rev. 0.7 / Jun. 2009  
32  
1240pin Registered DDR2 SDRAM DIMMs  
REVISION HISTORY  
Revision  
0.1  
History  
Initial data sheet released  
IDD updated  
Date  
May. 2007  
Jun. 2007  
Sep. 2007  
Nov. 2007  
Apr. 2008  
Mar. 2009  
Jun. 2009  
0.2  
0.3  
S6 items added and IDD adjusted  
Corrected Typos  
0.4  
0.5  
0.6  
0.7  
Added HYMP31GP72CMP4, HYMP151P72CP8, HYMP125P72CP8  
IDD Updated  
DIMM Outline Corrected  
Rev. 0.7 / Jun. 2009  
33  

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