HYMP351R72M4-E3 [HYNIX]
DDR DRAM Module, 512MX72, 0.6ns, CMOS, DIMM-240;
| 型号： | HYMP351R72M4-E3 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM Module, 512MX72, 0.6ns, CMOS, DIMM-240 动态存储器 双倍数据速率 |
| 文件： | 总24页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
240pin Registered DDR2 SDRAM DIMMs based on 1Gb 1st ver.
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb first version DDR2 SDRAMs in
Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1 Gb 1st ver. based Registered
DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard.
It is suitable for easy interchange and addition.
FEATURES
•
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
•
•
Fully differential clock operations (CK & /CK)
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
All inputs and outputs are compatible with SSTL_1.8
interface
•
•
•
•
•
•
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
•
•
•
•
8 Bank architecture
Serial presence detect with EEPROM
DDR2 SDRAM Package: 68ball FBGA
133.35 x 30.00 mm form factor
Posted CAS
Programmable CAS Latency 3 , 4 , 5
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Lead-free Products are RoHS compliant
ORDERING INFORMATION
# of
DRAMs
# of
ranks
Part Name
Density
Organization
Materials
HYMP112R728-E3/C4
HYMP125R728-E3/C4
HYMP125R724-E3/C4
HYMP351R72M4-E3/C4
HYMP112R72P8-E3/C4
HYMP125R72P8-E3/C4
HYMP125R7P24-E3/C4
HYMP351R72MP4-E3/C4
1GB
2GB
2GB
4GB
1GB
2GB
2GB
4GB
128Mx72
256Mx72
256Mx72
512Mx72
128Mx72
256Mx72
256Mx72
512Mx72
9
1
2
1
2
1
2
1
2
Leaded
Leaded
18
18
36
9
Leaded
Leaded
Lead free
Lead free
Lead free
Lead free
18
18
36
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Apr. 2005
1
1240pin Registered DDR2 SDRAM DIMMs
SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400)
C4 (DDR2-533)
Unit
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
400
400
533
Mbps
Mbps
Mbps
tCK
400
533
3-3-3
4-4-4
ADDRESS TABLE
# of
DRAMs
Refresh
Method
Organization Ranks
SDRAMs
# of row/bank/column Address
1GB
2GB
2GB
4GB
128M x 72
256M x 72
256M x 72
512M x 72
1
2
1
2
128Mb x 8
128Mb x 8
256Mb x 4
256Mb x 4
9
14(A0~A13)/2(BA0~BA2)/10(A0~A9)
14(A0~A13)/2(BA0~BA2)/10(A0~A9)
8K / 64ms
8K / 64ms
18
18
36
14(A0~A13)/2(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
14(A0~A13)/2(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
Rev. 1.0 / Apr. 2005
2
1240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol
Type Polarity
Pin Description
Positive
Edge
CK0
IN
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative
Edge
CK0
IN
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deac-
tivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations con-
tinue. Rank 0 is selected by S0; Rank 1 is selected by S1
CKE[1:0]
IN
Active
Low
S[1:0]
IN
Active
High
ODT[1:0]
IN
On-Die Termination signals.
RAS, CAS,
WE
Active
Low
When sampled at the positive rising edge of the clock. RAS,CAS and WE
(ALONG WITH S) define the command being entered.
IN
Vref
Supply
Supply
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
VDDQ
BA[2:0]
IN
IN
-
-
Selects which DDR2 SDRAM internal bank of Eight is activated.
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sampled
at the cross point of the rising edge of CK and
falling edge of CK.
In addition to the column address, AP is used to invoke autoprecharge operation at the end of the
burst read or write cycle.
If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged.
If AP is low, autoprecharge is disabled.
A[9:0],
A10/AP
A[13:11]
During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge.
If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs.
If AP is low, then BA0-BAn are used to define which bank to precharge.
DQ[63:0],
CB[7:0]
IN
IN
-
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coinci-
dent with that input data during a write access. DM is sampled on both edges of DQS. Although DM
pins are input only, the DM loading matches the DQ and DQS loading.
Activ
High
DM[8:0]
Power and ground for the DDR2 SDRAM input buffers, and core logic.
V
DD,VSS
Supply
I/O
V
DD and VDDQ pins are tied to VDD/VDDQ planes on these modules.
Positive
Edge
Negative
Edge
DQS[17:0]
DQS[17:0]
SA[2:0]
Positive line of the differential data strobe for input and output data
I/O
Negative line of the differential data strobe for input and output data
These signals are tied at the system planar to either VSS or VDDSPD to
configure the serial SPD EEPROM address range.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resister may be connected from the SDA bus line to VDDSPD on the
system planar to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM.
A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board.
IN
-
-
-
SDA
SCL
I/O
IN
Power supply for SPD EEPROM.
VDDSPD Supply
This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s)
will be set to low level (the PLL will remain
RESET
IN
synchronized with the input clock)
Par_In
Err_Out
TEST
IN
OUT
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 1.0 / Apr. 2005
3
1240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
Pin
Pin Description
Pin
Pin Description
On Die Termination Inputs
DQs Power Supply
CK0
CK0
Clock Input,positive line
Clock input,negative line
Clock Enable Input
Row Address Strobe
Column Address Strobe
Write Enable
ODT[1:0]
VDDQ
CKE0~CKE1
RAS
DQ0~DQ63
CB0~CB7
DQS(0~8)
DQS(0~8)
Data Input/Output
Data check bits Input/Output
Data strobes
CAS
WE
Data strobes,negative line
S0,S1
Chip Select Input
DM(0~8),DQS(9~17) Data Maskes/Data strobes
A0~A9,A11~A13 Address input
DQS(9~17)
RFU
Data strobes,negative line
Reserved for Future Use
No Connect
A10/AP
Address input/Autoprecharge
BA0, BA1, BA2 SDRAM Bank Address
NC
Memory bus test tool
(Not Connected and Not Usable on
DIMMs)
Serial Presence Detect(SPD)
Clock Input
SCL
TEST
SDA
SPD Data Input/Output
E2PROM Address Inputs
VDD
Core Power
I/O Power
SA0~SA2
VDDQ
Parity bit for the Address and
Control bus
Par_In
VSS
Ground
Err_Out
RESET
Parity error found on the Addre
Reset Enable
VREF
Input/Output Reference
SPD Power
VDDSPD
CB0~CB7
Data Check bit Inputs/Outputs
PIN LOCATION
Front Side
Back Side
1 pin
64 pin 65 pin
120 pin
184 pin
240 pin
185 pin
121 pin
Rev. 1.0 / Apr. 2005
4
1240pin Registered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
Pin
1
Name
VREF
VSS
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
VSS
Pin
81
Name
DQ33
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
Name
VSS
Pin
161
162
163
164
165
166
167
168
169
170
171
172
173
Name
CB4
Pin
201
202
203
Name
VSS
2
CB0
82
DQ4
CB5
DM4/DQS13
DQS13
VSS
3
DQ0
CB1
83
DQS4
DQS4
VSS
DQ5
VSS
4
DQ1
VSS
84
VSS
DM8,DQS17 204
5
VSS
DQS8
DQS8
VSS
85
DM0/DQS9
DQS9
VSS
DQS17
VSS
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
DQ38
DQ39
VSS
6
DQS0
DQS0
VSS
86
DQ34
DQ35
VSS
7
87
CB6
8
CB2
88
DQ6
CB7
DQ44
DQ45
VSS
9
DQ2
CB3
89
DQ40
DQ41
VSS
DQ7
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ3
VSS
90
VSS
VDDQ
NC,CKE1
VDD
A15,NC
A14,NC
VDDQ
A12
VSS
VDDQ
CKE0
VDD
BA2,NC
NC,Err_Out
VDDQ
A11
91
DQ12
DQ13
VSS
DM5/DQS14
DQS14
VSS
DQ8
92
DQS5
DQS5
VSS
DQ9
93
VSS
94
134 DM1/DQS10 174
DQ46
DQ47
VSS
DQS1
DQS1
VSS
95
DQ42
DQ43
VSS
135
136
137
138
139
140
141
142
143
144
145
DQS10
VSS
175
176
177
178
179
180
181
182
183
184
96
97
RFU
A9
DQ52
DQ53
VSS
RESET
NC
A7
98
DQ48
DQ49
VSS
RFU
VDD
A8
VDD
A5
99
VSS
VSS
100
101
102
103
104
105
106
107
108
DQ14
DQ15
VSS
A6
RFU
DQ10
DQ11
VSS
A4
SA2
VDDQ
A3
RFU
VDDQ
A2
NC(TEST)
VSS
VSS
DQ20
DQ21
VSS
A1
DM6/DQS15
NC,DQS15
VSS
DQ16
DQ17
VSS
VDD
Key
DQS6
DQS6
VSS
VDD
Key
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
146 DM2/DQS11 185
CK0
CK0
DQ54
DQ55
VSS
DQS2
DQS2
VSS
VSS
DQ50
DQ51
VSS
147
148
149
150
151
152
153
154
DQS11
VSS
186
187
188
189
190
191
192
193
VDD
VDD
A0
NC,Err_Out 109
DQ22
DQ23
VSS
DQ60
DQ61
VSS
DQ18
DQ19
VSS
VDD
A10/AP
BA0
110
111
112
113
114
115
116
117
118
119
120
DQ56
DQ57
VSS
VDD
BA1
DQ28
DQ29
VSS
VDDQ
RAS
DM7/DQS16
NC,DQS16
VSS
DQ24
DQ25
VSS
VDDQ
WE
DQS7
DQS7
VSS
S0
CAS
155 DM3/DQS12 194
VDDQ
ODT0
A13,NC
VDD
VSS
DQ62
DQ63
VSS
DQS3
DQS3
VSS
VDDQ
NC, S1
NC, ODT1
VDDQ
VSS
DQ58
DQ59
VSS
156
157
158
159
160
DQS12
VSS
195
196
197
198
199
200
DQ30
DQ31
VSS
VDDSPD
SA0
DQ26
DQ27
SDA
SCL
DQ36
DQ37
SA1
DQ32
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET(Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
Rev. 1.0 / Apr. 2005
5
1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) : HYMP112R72[P]8
/RS0
DQS4
/DQS4
DM4,DQS13
/DQS13
DQS0
/DQS0
DM0,DQS9
/DQS9
DM
RDQS /RDQS
I/O 0
NU
/CS
DQS /DQS
DQS /DQS
DQS /DQS
DM
RDQS /RDQS
I/O 0
NU
/CS
DQS /DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 1
I/O 2
D4
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS1
/DQS1
DM1,DQS10
/DQS10
/DQS5
DM5,DQS14
/DQS14
DM
RDQS /RDQS
I/O 0
NU
DM
RDQS /RDQS
I/O 0
NU
/CS
/CS
DQS /DQS
DQ40
DQ8
I/O 1
I/O 2
I/O 1
I/O 2
DQ41
DQ42
DQ9
DQ10
D5
D1
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DQS2
/DQS6
/DQS2
DM6,DQS15
/DQS15
DM2,DQS11
/DQS11
DM
RDQS /RDQS
I/O 0
NU
/CS
DM
RDQS /RDQS
I/O 0
NU
/CS
DQS /DQS
DQS /DQS
DQS /DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 2
I/O 1
I/O 2
D6
D2
I/O 3
I/O 4
I/O 5
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 6
I/O 7
DQS7
/DQS7
DM7,DQS16
/DQS16
DQS3
/DQS3
DM3,DQS12
/DQS12
DM
RDQS /RDQS
I/O 0
NU
DM
RDQS /RDQS
I/O 0
NU
/CS
/CS
DQS /DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 1
I/O 2
I/O 1
I/O 2
D3
D7
I/O 3
I/O 4
I/O 5
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 6
I/O 7
DQS8
/DQS8
DM8DQS17
/DQS17
Serial PD
U0
VDD SPD
Serial PD
DO-D8
SDA
SCL
SCL
SDA
DM
RDQS /RDQS
I/O 0
NU
/CS
VDD /
VDDQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
W
P
A0
A1
A2
I/O 1
I/O 2
VREF
VSS
DO-D8
DO-D8
SA0 SA1 SA2
D8
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
R
/CS0*
/RS0 to /CS ==> /CS: SDRAMs D0 to D8
E
G
I
PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD8
/PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD8
CK0
P
L
L
BA0 to BA2
A0 to A13
RBA0 to RBA2 ==> BA0 to BA2: SDRAMs D0 to D8
/RA0 to RA13 ==> A0 to A13: SDRAMs D0 to D8
/RRAS ==>/RAS: SDRAMs D0 to D8
/CK0
S
T
E
R
/RAS
PCK7 ==> CK: Register
/PCK7 ==> /CK: Register
/CAS
/RCAS ==>/CAS: SDRAMs D0 to D8
/RESET
OE
CKE0
RCKE0 ==> CKE: SDRAMs D0 to D8
/RWE ==> /WE: SDRAMs D0 to D8
/WE
ODT0
Notes :
1. Register values are 22 Ohms.
RODT0 ==> ODT0: SDRAMs D0 to D8
/RESET
PCK7
* : /S0 connects to D/CS and VDD connects to /CSR on register.
/RST
/PCK7
Rev. 1.0 / Apr. 2005
6
1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72) : HYMP125R72[P]8
/RS1
/RS0
DQS0
/ DQS0
DQS4
/ DQS4
DM0, DQS9
DM4, DQS13
/DQS9
/DQS13
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
NU
/ RDQS
DQS / DQS
NU
/ RDQS
DQS / DQS
DM
RDQS
I/ O 0
NU
/ RDQS
DM
RDQS
I/ O 0
NU
/ RDQS
/CS
/CS
DQS / DQS
DQS / DQS
DQS / DQS
DQS / DQS
DQS / DQS
DQS / DQS
DQS / DQS
DQS / DQS
/CS
/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
D0
D9
D4
D13
DQ36
DQ37
DQ38
DQ39
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQS1
/ DQS1
DQS5
/ DQS5
DM5, DQS14
/DQS14
DM1,DQS10
/DQS10
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DQS / DQS
NU
/ RDQS
DQS / DQS
NU
/ RDQS
/CS
/CS
NU /CS
/ RDQS
NU /CS
/ RDQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ10
DQ11
D1
D5
D14
D15
D16
D10
DQ12
DQ13
DQ14
DQ15
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQS6
/ DQS6
DM6, DQS15
DQS2
/ DQS2
DM2, DQS11
/DQS15
/DQS11
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DQS / DQS
NU
/ RDQS
DQS / DQS
NU /CS
/ RDQS
NU /CS
/ RDQS
/CS
/CS
NU
/ RDQS
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
D6
D2
D11
DQ20
DQ21
DQ22
DQ23
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQ54
DQ55
DQS7
/ DQS7
DM7, DQS16
DQS3
/ DQS3
DM3, DQS12
/DQS12
/DQS16
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
DQS / DQS
NU
/ RDQS
DQS / DQS
/CS
/CS
NU /CS
/ RDQS
NU /CS
/ RDQS
NU
/ RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
D3
D12
D7
DQ60
DQ61
DQ62
DQ63
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQS8
/ DQS8
DM8, DQS17
Serial
PD
VDD SPD
SDA
SCL
SCL
WP
/DQS17
Serial PD
VDD/VDDQ
DO-D17
DO-D17
DO-D17
DM
RDQS
I/ O 0
DM
RDQS
I/ O 0
NU
/ RDQS
DQS / DQS
NU
/ RDQS
DQS / DQS
/CS
/CS
A0
A1
A1
VREF
CB0
CB1
CB2
CB3
SA0
SA1
SA2
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
VSS
D8
D17
CB4
CB5
CB6
CB7
CK0
PCK0 to PCK6, PCK8,PCK9 => CK : SDRAMx D0-D17
P
L
L
/CK0
/PCK0 to /PCK6, /PCK8,/PCK9 => /CK : SDRAMx D0-D17
I/ O 6
I/ O 7
I/ O 6
I/ O 7
PCK7 => CK: Register
/PCK7 => /CK: Register
1:2
R
E
G
I
/S0
/S1
/RS0 to /CS : SDRAMs D0 - D8
/RS1 to /CS : SDRAMs D9 - D17
/RESET
OE
BA0 to BA2
/RBA0 to RBA2 => BA0 - BA2 : SDRAMs D0 - D17
/RA0 to RA12 => A0 - A12 : SDRAMs D0 - D17
/RRAS => /RAS: SDRAMs D0-D17
/RCAS => /CAS: SDRAMs D0-D17
/RWE => /WE: SDRAMs D0-D17
A0 to A13
/RAS
Notes:
1. Register values are 22 Ohms +/- 5%.
2. /RS0 and /RS1 alternate between the back and front sides of the DIMM
S
T
/CAS
/WE
E
R
CKE0
CKE1
ODT0
ODT1
RCKE0 => CKE0: SDRAMs D0-D8
RCKE1 => CKE1: SDRAMs D9-D17
RODT0 => ODT0: SDRAMs D0-D8
RODT1 => ODT1: SDRAMs D9-D17
/ RST
/RESET
PCK7
/PCK7
Rev. 1.0 / Apr. 2005
7
1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72): HYMP125R72[P]4
VSS
/RS0
/ DQS0
DQS0
/ DQS9
DQS9
Serial PD
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ0
DQ4
SDA
SCL
SCL
SDA
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
I/O1
D0
I/O2
I/O1
D9
I/O2
U0
W
P
A0
A1
A2
I/O3
I/O3
/ DQS1
/ DQS10
DQS10
SA0 SA1 SA2
DQS1
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ8
DQ12
Serial
PD
VDD SPD
VDD/VDDQ
VREF
DQ9
DQ13
DQ14
DQ15
I/O1
D1
I/O1
D10
I/O2
DQ10
DQ11
I/O2
DO-D17
I/O3
I/O3
/ DQS2
DQS2
/ DQS11
DO-D17
DO-D17
DQS11
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
VSS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
I/O1
D2
I/O1
D11
I/O2
I/O2
DQ22
I/O3
I/O3
DQ23
/ DQS3
DQS3
/ DQS12
DQS12
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O1
D3
I/O1
D12
I/O2
I/O2
I/O3
I/O3
/ DQS4
DQS4
/ DQS13
DQS13
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O1
D4
I/O1
D13
I/O2
I/O2
I/O3
I/O3
/ DQS5
DQS5
/ DQS14
DQS14
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
I/O1
D5
I/O1
D14
I/O2
I/O2
DQ46
I/O3
I/O3
DQ47
/ DQS6
DQS6
/ DQS15
DQS15
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
I/O1
D6
I/O1
D15
I/O2
I/O2
DQ50
I/O3
I/O3
DQ51
/ DQS7
DQS7
/ DQS16
DQS16
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O1
D7
I/O1
D16
I/O2
I/O2
I/O3
I/O3
/ DQS8
DQS8
/ DQS17
DQS17
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O1
D8
I/O1
D17
I/O2
I/O2
I/O3
I/O3
CK0
PCK0 to PCK6, PCK8,PCK9 =
>
CK : SDRAMx D0-D17
P
L
L
R
E
G
I
S
T
E
R
/CS0*
/RS0 to /CS ==> /CS: SDRAMs D0 to D17
/CK0
/PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D17
BA0 to BA2
A0 to A13
RBA0 to RBA2 ==> BA0 to BA2: SDRAMs D0 to D17
/RA0 to RA13 ==> A0 to A13: SDRAMs D0 to D17
/RRAS ==>/RAS: SDRAMs D0 to D17
PCK7
=
>
CK: Register
/RAS
/RESET
OE
/PCK7
= > /CK: Register
/CAS
/RCAS ==>/CAS: SDRAMs D0 to D17
CKE0
RCKE0 ==> CKE: SDRAMs D0 to D17
/RWE ==> /WE: SDRAMs D0 to D17
/WE
Notes:
1. Resistor values are 22 Ohms +/- 5%.
ODT0
RODT0 ==> ODT0: SDRAMs D0 to D17
/RESET
PCK7
/S0 connects to D/CS of Register1 and /CSR of Register2. /CSR of register and D/CS of register2 connects to VDD.
/RST
/PCK7
*
** /RESET,PCK7 connect to both Registers. Other signals connect to one of two Registers. /S1,CKE1 and ODT1 are NC.
Rev. 1.0 / Apr. 2005
8
1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72) : HYMP351R72M[P]4
VSS
/RS0
/RS1
Serial PD
U0
SDA
SCL
SCL
SDA
DQS9
/ DQS9
DQS0
/ DQS0
W
P
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
A0
A1
A2
I/O0
I/O1
I/O0
I/O1
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
D0,D18( DDP)
D9,D27( DDP)
I/O2
I/O3
I/O2
I/O3
SA0 SA1 SA2
DQS10
DQS1
/ DQS10
/ DQS1
DM /CS DQS / DQS
DM /CS DQS / DQS
Serial
PD
DM /CS DQS
DM /CS DQS
VDD SPD
VDD /VDDQ
VREF
I/O0
I/O1
I/O0
I/O1
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
D10,D28( DDP)
D1,D19( DDP)
I/O2
I/O3
I/O2
I/O3
DO to D35
DQ11
DO to D35
DO to D35
/RS0
/RS1
DQS11
/ DQS11
DQS2
VSS
/ DQS2
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
I/O0
I/O1
I/O0
I/O1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D11,D29( DDP)
D2,D20( DDP)
I/O2
I/O3
I/O2
I/O3
DQS12
DQS3
/ DQS12
/ DQS3
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
D12,D30( DDP)
D3,D21( DDP)
I/O2
I/O3
I/O2
I/O3
DQS17
DQS8
/ DQS17
/ DQS8
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
D17,D35( DDP)
D8,D26( DDP)
I/O2
I/O3
I/O2
I/O3
/RS0
/RS1
DQS13
DQS4
/ DQS13
/ DQS4
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
I/O0
I/O1
I/O0
I/O1
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
D13,D31( DDP)
D4,D2( DDP)
I/O2
I/O3
I/O2
I/O3
DQS14
DQS5
/ DQS14
/ DQS5
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
D14,D32( DDP)
D5,D23( DDP)
I/O2
I/O3
I/O2
I/O3
/RS0
/RS1
DQS15
DQS6
/ DQS15
/ DQS6
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
I/O0
I/O1
I/O0
I/O1
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
D15,D33( DDP)
D6,D24( DDP)
I/O2
I/O3
I/O2
I/O3
DQS9
DQS7
/ DQS9
/ DQS7
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
D9,D34( DDP)
D7,D25( DDP)
I/O2
I/O3
I/O2
I/O3
1:2
R
E
G
I
S
T
E
/S0*
/S1*
/RS0 to /CS : SDRAMs D0 ? D17
/RS1 to /CS : SDRAMs D18 ? D35
CK0
PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D35
P
L
L
BA0 ? BA2
A0?A13
/RAS
/RBA0 ? RBA2 = > BA0 -BA2 : SDRAMs D0-D35
/RA0 ? RA12 = > A0 -A12 : SDRAMs D0-D35
/RRAS = > /RAS: SDRAMs D0-D35
/RCAS = > /CAS: SDRAMs D0-D35
/RWE = > /WE: SDRAMs D0-D35
/CK0
/PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D35
PCK7 = > CK: Register
/PCK7 = > /CK: Register
/CAS
/WE
/RESET
OE
CKE0
RCKE0 = > CKE0: SDRAMs D0-D17
R
CKE1
RCKE1 = > CKE1: SDRAMs D18-D35
RODT0 = > ODT0: SDRAMs D0-D17
RODT1 = > ODT1: SDRAMs D18-D35
ODT0
ODT1
/RESET**
Notes:
1. Register values are 22 Ohms +/- 5%.
2. /RS0 and /RS1 alternate between the back and front sides of the DIMM
/ RST
PCK7**
/PCK7**
*
/S0 connects to D/CS0 and /S1 connects to D/CS1 on both Registers.
** /RESET,PCK7 and /PCK7 connect to both Registers. Other signals connect to two Registers.
Rev. 1.0 / Apr. 2005
9
1240pin Registered DDR2 SDRAM DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Note
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-50 ~ +100
V
V
V
V
1
1
1
1
1
1
Voltage on V pin relative to Vss
DD
DD
VDDL
Voltage on VDDL pin relative to Vss
V
Voltage on V
pin relative to Vss
DDQ
DDQ
V
V
IN, OUT
Voltage on any pin relative to Vss
Storage Temperature
o
T
C
STG
H
Storage Humidity(without condensation)
5 to 95
%
STG
Note :
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied.
Expousure to absolute maximum rating conditions for extended periods may affect reliablility.
OPERATING CONDITIONS
Parameter
Symbol
Rating
Units
Notes
o
T
0 ~ +55
C
OPR
DIMM Operating temperature(ambient)
BAR
DIMM Barometric Pressure(operating & storage)
105 to 69
0 ~+95
K Pascal
1
2
P
o
T
DRAM Component Case Temperature Range
C
CASE
Note :
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Symbol
VDD
Min
1.7
Max
1.9
Unit
V
Note
VDDL
1.7
1.9
V
Power Supply Voltage
VDDQ
VREF
1.7
1.9
V
1
2
Input Reference Voltage
EEPROM Supply Voltage
0.49 x VDDQ
1.7
0.51 x VDDQ
3.6
V
VDDSPD
VTT
V
VREF+0.04
V
3
VREF-0.04
Termination Voltage
Note :
1. VDDQ must be less than or equal to VDD
.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Rev. 1.0 / Apr. 2005
10
1240pin Registered DDR2 SDRAM DIMMs
INPUT DC LOGIC LEVEL
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.30
Max
Unit
V
Note
Input High Voltage
Input Low Voltage
VDDQ + 0.3
VREF - 0.125
V
INPUT AC LOGIC LEVEL
Parameter
Symbol
Min
Max
Unit
V
Note
AC Input logic High
AC Input logic Low
VIH(AC)
VIL(AC)
V
REF + 0.250
-
V
-
V
REF - 0.250
AC INPUT TEST CONDITIONS
Symbol
Condition
Input reference voltage
Value
Units
Notes
VREF
0.5 * VDDQ
V
1
1
VSWING(MAX) Input signal maximum peak to peak swing
SLEW Input signal minimum slew rate
1.0
1.0
V
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
V
SWING(MAX)
max
max
IL(dc)
IL(ac)
SS
delta TF
delta TR
Rising Slew =
V
min - V
REF
V
-
V
max
IL(ac)
IH(ac)
REF
Falling Slew =
delta TF
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 1.0 / Apr. 2005
11
1240pin Registered DDR2 SDRAM DIMMs
Differential Input AC logic Level
Note
Symbol
Parameter
Min.
Max.
Units
1
VID (ac)
0.5
VDDQ + 0.6
V
ac differential input voltage
ac differential cross point voltage
2
VIX (ac)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
Note:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS)
level. The minimum value is equal to VIH(DC) - VIL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
Parameter
Min.
Max.
Units
Note
VOX (ac)
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 1.0 / Apr. 2005
12
1240pin Registered DDR2 SDRAM DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
Parameter
SSTL_18
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Note:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18
Units
Notes
- 13.4
13.4
mA
mA
1, 3, 4
2, 3, 4
Note:
1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT.
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2.
They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise
margin are delivered to an SSTL_18 receiver.
The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define
a convenient driver current for measurement.
Rev. 1.0 / Apr. 2005
13
1240pin Registered DDR2 SDRAM DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25oC f=1MHz )
1GB : HYMP112R72[P]8
Pin
Symbol
Min
Max
Unit
CK0, CK0
CCK
CI1
CI2
CI3
CIO
7
8
8
8
6
11
12
12
12
9
pF
pF
pF
pF
pF
CKE, ODT
CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
2GB : HYMP125R72[P]8
Pin
Symbol
Min
Max
Unit
CK0, CK0
CCK
CI1
CI2
CI3
CIO
7
8
11
12
15
12
13
pF
pF
pF
pF
pF
CKE, ODT
CS
10
8
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
8
2GB : HYMP125R72[P]4
Pin
Symbol
Min
Max
Unit
CK0, CK0
CCK
CI1
CI2
CI3
CIO
7
8
11
12
15
12
9
pF
pF
pF
pF
pF
CKE, ODT
CS
10
8
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
6
4GB : HYMP351R72M[P]4
Pin
Symbol
Min
Max
Unit
CK0, CK0
CCK
CI1
CI2
CI3
CIO
9.5
10.5
10.5
10.5
17
14
16
16
16
21
pF
pF
pF
pF
pF
CKE, ODT
CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
Note :
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 1.0 / Apr. 2005
14
1240pin Registered DDR2 SDRAM DIMMs
o
IDD SPECIFICATIONS (T
: 0 to 95 C)
CASE
1GB, 128M x 72 Registered DIMM : HYMP112R72[P]8
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
1550
1640
704
1640
1730
704
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
1010
1055
875
1100
1145
920
713
722
1190
1820
1910
3080
522
1280
2180
2270
3080
522
1
IDD7
2810
3350
2GB, 256M x 72 Registered DIMM : HYMP125R72[P]8
Symbol
IDD0
E3(DDR2 400@CL3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
2090
2180
758
2270
2360
758
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
1370
1460
1100
776
1550
1640
1190
794
1730
2360
2450
3620
594
1910
2810
2900
3710
594
1
IDD7
3350
3980
Note:
1. IDD6 current alues are guaranted up to Tcase of 85oC max.
Rev. 1.0 / Apr. 2005
15
1240pin Registered DDR2 SDRAM DIMMs
2GB, 256M x 72 Registered DIMM : HYMP125R72[P]4
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
2450
2630
758
2630
2810
758
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
1370
1460
1100
776
1550
1640
1190
794
1730
2990
3170
5510
476
1910
3710
3890
5510
476
1
IDD7
4970
6050
4GB, 512M x 72 Registered DIMM : HYMP351R72M[P]4
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
3530
3710
866
3890
4070
866
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
2090
2270
1550
902
2450
2630
1730
938
2810
4070
4250
6590
738
3170
4970
5150
6770
738
1
IDD7
6050
7310
Note :
1. IDD6 current alues are guaranted up to Tcase of 85oC max.
Rev. 1.0 / Apr. 2005
16
1240pin Registered DDR2 SDRAM DIMMs
IDD Meauarement Conditions
Symbol
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are
SWITCHING;Data bus inputs are SWITCHING
IDD0
IDD1
mA
t
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; CK =
t
t
t
t
t
t
t
CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH between valid
commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and address
IDD2P
IDD2Q
IDD2N
mA
mA
mA
bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD); CKE is LOW;
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
IDD4R
Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-
ING
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP= RP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
mA
mA
t
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK
t
t
t
t
t
= CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85oC max.
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
t
t
t
t
AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; - Refer to the following page for detailed timing conditions
IDD7
mA
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations
of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Rev. 1.0 / Apr. 2005
17
1240pin Registered DDR2 SDRAM DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
DDR2-533 (C4)
DDR2-400 (E3)
Unit
4-4-4
min
4
3-3-3
min
3
tCK
ns
15
15
tRP
15
15
ns
tRC
60
55
ns
tRAS
45
40
ns
AC Timing Parameters by Speed Grade
DDR2-400
Min Max
DDR2-533
Parameter
Symbol
Unit Note
Min
-500
-450
0.45
0.45
Max
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
Clock High Level Width
tAC
tDQSCK
tCH
-600
-500
0.45
0.45
600
500
500
450
ps
ns
0.55
0.55
0.55
0.55
CK
CK
Clock Low Level Width
tCL
min
(tCL,tCH)
min
(tCL,tCH)
Clock Half Period
tHP
-
-
ns
ps
System Clock Cycle Time
tCK
tDS
5000
150
275
25
8000
3750
100
225
-25
8000
DQ and DM input setup time
-
-
-
-
-
-
-
-
ps
ps
ps
ps
1
1
1
1
DQ and DM input hold time
tDH
DQ and DM input setup time(single-ended strobe)
DQ and DM input hold time(single-ended strobe)
tDS1
tDH1
25
-25
Control & Address input Pulse Width
for each input
tIPW
0.6
-
-
0.6
-
-
tCK
DQ and DM input pulse witdth for each input pulse
width for each input
tDIPW
tHZ
0.35
0.35
tCK
ps
Data-out high-impedance window from CK, /CK
-
tAC max
tAC max
-
tAC max
tAC max
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC min
ps
ps
2*tAC min tAC max
2*tAC min tAC max
-
-
350
-
-
300
ps
450
400
ps
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock edge
DQS input high pulse width
tQH
tHP - tQHS
0.25
0.35
0.35
0.2
-
tHP - tQHS
0.25
0.35
0.35
0.2
-
ps
tDQSS
tDQSH
tDQSL
tDSS
+0.25
+0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
-
-
-
-
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
-
-
tDSH
0.2
-
0.2
-
tMRD
2
-
2
-
tWPST
tWPRE
0.4
0.6
-
0.4
0.6
-
Write preamble
0.35
0.35
Rev. 1.0 / Apr. 2005
18
1240pin Registered DDR2 SDRAM DIMMs
- Continued -
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Address and control input setup time
Address and control input hold time
Read preamble
tIS
tIH
350
475
0.9
0.4
-
250
375
0.9
0.4
-
ps
ps
-
-
tRPRE
tRPST
1.1
0.6
1.1
0.6
tCK
tCK
Read postamble
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
127.5
-
127.5
-
ns
Row Active to Row Active Delay for 1KB page size
tRRD
tRRD
tFAW
tFAW
7.5
10
-
-
-
-
7.5
10
-
-
-
-
ns
ns
ns
ns
Row Active to Row Active Delay for 2KB page size
Four Activate Window for 1KB page size
Four Activate Window for 2KB page size
37.5
50
37.5
50
CAS to CAS command delay
tCCD
tWR
2
15
2
15
tCK
ns
Write recovery time
-
-
-
-
Auto Precharge Write Recovery + Precharge Time
tDAL
tWR+tRP
tWR+tRP
tCK
Write to Read Command Delay
tWTR
10
-
ns
7.5
-
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
tRTP
tXSNR
tXSRD
7.5
tRFC + 10
200
7.5
tRFC + 10
200
ns
ns
-
-
-
-
tCK
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
Exit active power down to read command
tXARD
tXARDS
6 - AL
6 - AL
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
tCKE
3
2
3
2
tCK
tCK
tAOND
tAON
ODT turn-on delay
ODT turn-on
2
2
tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns
2tCK+tAC
(max)+1
tAC(min)
+2
2tCK+tAC
(max)+1
tAONPD
tAOFD
tAOF
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
ns
tCK
ns
2.5
2.5
2.5
tAC(max)+
0.6
tAC(max)+
0.6
ODT turn-off
tAC(min)
tAC(min)
2.5tCK+tAC(
max)+1
2.5tCK+tAC(
max)+1
tAOFPD
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tIS+tCK
+tIH
tIS+tCK
+tIH
tDelay
ns
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Note :
1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS1G[4/8]31(L)F).
2. 0°C
3. 85°C
TCASE
TCASE
85°C
95°C
Rev. 1.0 / Apr. 2005
19
1240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
128Mx72 (1 rank) - HYMP112R72[P]8
Front
133.35
Side
2. 7 max
R
E
G
I
S
T
E
R
(Front)
4.0±0.1
30.0
PLL
Detail-A
Detail-B
1. 27 ±0.10
5.175
63.0
55.0
5.175
5.0
Back
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
± 0.05
0.8
± 0.10
1.50
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
20
1240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
256Mx72 (2 ranks) - HYMP125R72[P]8
Front
Side
4.0 max
133.35
R
E
G
I
S
T
E
R
4.0±0.1
30.0
PLL
Detail-A
Detail-B
1.27 ± 0.10
5.175
63.0
55.0
5.175
5.0
Back
R
E
G
I
S
T
E
R
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
± 0.05
0.8
± 0.10
1.50
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
21
1240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
256Mx72 (1 rank) - HYMP125R72[P]4
Front
Side
4.0 max
133.35
R
E
G
I
S
T
E
R
4.0±0.1
30.0
PLL
Detail-A
Detail-B
1.27 ± 0.10
5.175
63.0
55.0
5.175
5.0
Back
R
E
G
I
S
T
E
R
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
± 0.05
0.8
± 0.10
1.50
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
22
1240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
512Mx72 (2 ranks) - HYMP351R72M[P]4
Front
Side
4. 0 max
133.35
R
E
G
I
S
T
E
R
4.0±0.1
30.0
PLL
Detail-A
Detail-B
1. 27 ±0.10
5.175
63.0
55.0
5.175
5.0
Back
R
E
G
I
S
T
E
R
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
± 0.05
0.8
± 0.10
1.50
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
23
1240pin Registered DDR2 SDRAM DIMMs
REVISION HISTORY
Revision
History
Date
Remark
First Version Release
Data sheet coverage changed from an individual module part to a component
based module family.
Added VDDL spec, corrected tDS & tDH spec values.
Dec. 2004
Apr. 2005
1.0
Rev. 1.0 / Apr. 2005
24
相关型号：
©2020 ICPDF网 联系我们和版权申明