UPA102B-E1_技术文档

GMS81508A

GMS81516A

USER’S MANUAL

Revision History

Rev 2.2 (Dec. 1998)

Add the package dimension for 64LQFP on page 3-1, 4-1.

Rev 2.1 (Nov. 1998)

Operating Temperature, -10~75°C is extended to -20~85°C.

Add the unused port guidance on page 55.

Correct errata for opcode of “EOR [dp+X], EOR [dp]+Y, EOR {X}” in “Instruction Set”.

Add the OTP device programming guidance, recommend using “Intelligent Mode”.

Add the chapter for OTP programming manual as an appendix.

Rev 2.0 (Sep. 1997)

- CONTENTS -

1. OVERVIEW...........................................................................................................................................1

1.1. FEATURES ..........................................................................................................................................1

1.2. BLOCK DIAGRAM..............................................................................................................................2

1.3. PIN ASSIGNMENT..............................................................................................................................3

1.4. PACKAGE DIMENSION .....................................................................................................................4

1.5. PIN DESCRIPTION..............................................................................................................................5

2. FUNCTIONS..........................................................................................................................................7

2.1. REGISTERS .........................................................................................................................................7

2.1.1. A - Register....................................................................................................................................8

2.1.2. X- Register.....................................................................................................................................8

2.1.3. Y- Register.....................................................................................................................................8

2.1.4. Stack Pointer .................................................................................................................................8

2.1.5. Program Counter.........................................................................................................................10

2.1.6. Program Status Word...................................................................................................................10

2.2. MEMORY SPACE..............................................................................................................................12

2.2.1. RAM area ....................................................................................................................................12

2.2.2. Peripheral Register area..............................................................................................................12

2.2.3. Program ROM area .....................................................................................................................12

2.2.4. Peripheral Register List ...............................................................................................................14

2.3. CLOCK GENERATION CIRCUIT .....................................................................................................16

2.3.1. Oscillation Circuit .......................................................................................................................16

2.3.2. Prescaler .....................................................................................................................................17

2.4. BASIC INTERVAL TIMER................................................................................................................18

2.4.1. Control of Basic Interval Timer....................................................................................................18

2.5. WATCH DOG TIMER........................................................................................................................19

2.5.1. Control of Watch Dog Timer ........................................................................................................19

2.5.2. The output of WDT signal.............................................................................................................20

2.6. TIMER................................................................................................................................................21

2.6.1. Control of Timer ..........................................................................................................................23

2.6.2. Interval Timer..............................................................................................................................24

2.6.3. Event Counter..............................................................................................................................24

2.6.4. Pulse Output ................................................................................................................................24

2.6.5. Input Capture...............................................................................................................................24

2.7. EXTERNAL INTERRUPT..................................................................................................................26

2.8. A/D CONVERTER .............................................................................................................................27

2.8.1. Control of A/D Converter.............................................................................................................27

2.9. SERIAL I/O........................................................................................................................................29

2.9.1. Data Transmission/Receiving Timing ...........................................................................................31

2.9.2. The Serial I/O operation by Srdy pin ............................................................................................31

2.9.3. The method of Serial I/O ..............................................................................................................32

2.9.4. The Method to Test Correct Transmission with S/W......................................................................32

2.10. PWM ................................................................................................................................................33

2.10.1. Controls of PWM .......................................................................................................................33

2.11. BUZZER DRIVER............................................................................................................................35

2.11.1. Buzzer Driver Operation ............................................................................................................36

2.12. INTERRUPTS...................................................................................................................................37

2.12.1. Interrupt Circuit Configuration and Kinds..................................................................................37

2.12.2. Interrupt Control........................................................................................................................38

2.12.3. Interrupt Priority .......................................................................................................................39

2.12.4. Interrupt Sequence..................................................................................................................... 40

2.12.5. Software Interrupt ..................................................................................................................... 41

2.12.6. Multiple Interrupt...................................................................................................................... 42

2.13. STANDBY FUNCTION................................................................................................................... 44

2.13.1. STOP Mode............................................................................................................................... 45

2.13.2. STOP Mode Release .................................................................................................................. 45

2.14. RESET FUNCTION ......................................................................................................................... 47

3. I/O PORTS........................................................................................................................................... 48

3.1. R0 PORT............................................................................................................................................ 48

3.2. R1 PORT............................................................................................................................................ 49

3.3. R2 PORT............................................................................................................................................ 50

3.4. R3 PORT............................................................................................................................................ 51

3.5. R4 PORT............................................................................................................................................ 52

3.6. R5 PORT............................................................................................................................................ 53

3.7. R6 PORT ............................................................................................................................................ 54

3.8. TERMINAL TYPES........................................................................................................................... 56

4. ELECTRICAL CHARACTERISTICS............................................................................................... 60

4.1. ABOULUTE MAXIMUM RATINGS................................................................................................. 60

4.2. RECOMMENDED OPERATING CONDITIONS............................................................................... 60

4.3. A/D CONVERTER CHARACTERISTICS ......................................................................................... 60

4.4. DC CHARACTERISTICS .................................................................................................................. 61

4.5. AC CHARACTERISTICS .................................................................................................................. 62

4.5.1. Input Conditions.......................................................................................................................... 62

4.5.2. Serial Transfer ............................................................................................................................ 63

4.5.3. Microprocessor Mode I/O Timing................................................................................................ 64

4.5.4. Bus Holding Timing..................................................................................................................... 65

5. INSTRUCTION SET........................................................................................................................... 66

GMS81508/16

1. OVERVIEW

GMS81508/16 is a single chip microcomputer designed CMOS technology. The use of CMOS

process enables extremely low power consumption.

This device using the G8MC Core includes several peripheral functions such as Timer, A/D

Converter, Programmable Buzzer Driver, Serial I/O, Pulse Width Modulation Function, etc.

ROM,RAM,I/O are placed on the same memory map in addition to simple instruction set.

1.1. FEATURES

GMS81508

GMS81516

ROM(Bytes)

RAM(Bytes)

Execution Time

Basic Interval Timer

Watch Dog Timer

Timer

8K

16K

448 bytes(includes stack area)

0.5us (@Xin=8MHz)

8bit ✕ 1ch.

6bit ✕ 1ch.

8bit✕4ch.(or 16bit ✕ 2ch.)

8bit ✕ 8ch.

ADC

PWM

8bit ✕ 2ch.

Serial I/O

8bit ✕ 1ch.

External Interrupt

Buzzer Driver

I/O Port

4ch.

Programmable Buzzer Driving Port

4 - Input only

52 - Input/Output

STOP Mode

4.5 5.5V ( @ Xin=8MHz )

Power Save Mode

Operating Voltage

Operating Frequency

Package

1

8MHz

64SDIP, 64QFP

GMS81516T

OTP

Application

Home Appliances, LED Applications

1

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1.2. BLOCK DIAGRAM

AVref

AVss

R60

:

R63

A/D

CONVERTER

R60~R67

(AN0~AN7)

R6

PORT

G8MC

CORE

R64

:

R67

R57/PWM1

R56/PWM0

PWM

R5

PORT

R50

:

R57

RAM

(448 BYTE)

R55/BUZ

BUZZER

W.D.T

R4

PORT

R40

:

R47

R54/WDTO

R3

PORT

R30

:

R37

ROM

(8/16K BYTE)

R53/Srdy

R52/Sclk

R51/Sout

R50/Sin

S.I.C

R2

PORT

R20

:

R27

R47/T3 O

R46/T1 O

TIMER

R45/EC2

R44/EC0

R1

PORT

R10

:

R17

R43/INT3

R42/INT2

R41/INT1

R40/INT0

INTERRUPT

PRESCALER

/

R0

PORT

R00

:

R07

CLOCK GEN.

/

SYSTEM

CONTROL

B.I.T

MP

RESET

Xin

Xout

Vdd

Vss

2

GMS81508/16

1.3. PIN ASSIGNMENT

MP MODE

R30/ RD

Vdd

MP

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

R31/ Wt

3

AVss

R32/ R/W

4

AVref

R33/

C

5

R67/AN7

R66/AN6

R65/AN5

R64/AN4

R63/AN3

R62/AN2

R61/AN1

R60/AN0

R34/ SYNC

R35/ BRK

R36/ BRQ

R37/ HALT

R00/ D0

R01/ D1

R02/ D2

R03/ D3

R04/ D4

R05/ D5

R06/ D6

R07/ D7

R10/ A0

R11/ A1

R12/ A2

R13/ A3

R14/ A4

R15/ A5

R16/ A6

R17/ A7

R20/ A8

R21/ A9

R22/ A10

R23/ A11

R24/ A12

R25/ A13

R26/ A14

R27/ A15

6

7

G

M

S

8

1

5

0

8

/

1

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

R57/PWM1

R56/PWM0

R55/BUZ

R54/WDTO

R53/Srdy

R52/Sclk

R51/Sout

R50/Sin

R47/T3O

R46/T1O

R45/EC2

R44/EC0

R43/INT3

R42/INT2

R41/INT1

R40/INT0

RESET

6

Xin

Xout

Vss

64 SDIP

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

52

53

54

55

56

57

32

31

30

29

28

27

R36 BRQ

R35 BAK

R34 SYNC

R33 C

R22/A10

R23/A11

R24/A12

R25/A13

R26/A14

R17/A15

R32 R/W

R31 Wt

R30 Rd 58

Vdd 59

26 Vss

GMS81508/16

25 Xout

24 Xin

MP 60

AVss 61

23 RESET

AVref

R67/AN7

R66/AN6

R40/INT0

62

63

64

22

21

20

R41/INT1

R42/INT2

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

64 QFP

3

GMS81508/16

1.5. PIN DESCRIPTION

Classification

No.

Symbol

I/O

Descriptions

Power

1

32

Vdd

Vss

I

Power Supply Input Pin(4.5~5.5V)

Ground(0V)

Controls Microprocess Mode of the Chip

At "H" input : Single Chip Mode

2

MP

At "L" input : Microprocess Mode

System Control

29

RESET

I

In the state of "L" level, system enter to the reset

state.

This chip has an internal clock generating circuit. To

control generating frequency, an external ceramic or

a quartz crystal oscillator is connected between Xin

and Xout pins.

If external clock is used, the clock source should be

connected to the Xin pin and the Xout pin should be

left open.

or

Clock

30

31

Xin

Xout

I

24

23

22

21

28

27

26

25

4

EC0

EC2

T1O

I

O

I

Event Counter Source Clock Input Pin

Timer

Timer Counter Overflow Output Pin

T3O

INT0

INT1

INT2

INT3

AVref

AVss

AN0

AN1

AN2

AN3

Ext. Interrupt

External Interrupt Request Signal Input Pin

Reference Voltage Input Pin for A/D Converter

Ground Level Input Pin for A/D Converter

3

12

11

10

9

A/D Converter

I

Analog Voltage Input Pin for A/D Converter

8

AN4

I

7

AN5

I

6

AN6

I

5

AN7

I

17

18

19

20

14

13

15

16

Srdy

Sclk

Sout

Sin

PWM0

PWM1

BUZ

WDTO

I/O

O

I

O

Receive Enable Output Pin

Serial Clock Output Pin

Serial Data Output Pin

Serial Data Input Pin

Serial I/O

P.W.M

PWM Pulse Output Pin

Buzzer

W.D.T

Buzzer Driving Frequency Output Pin

Watch dog Timer Overflow Output Pin

5

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Classification

No.

Symbol

I/O

Description

49

:

56

R00

:

R07

R0 Port

I/O

( Can be determined I/O by R0DD )

In MP mode, This port functions as 8-bit data bus for

the CPU. (D0~D7)

41

:

48

R10

:

R17

R1 Port

I/O

( Can be determined I/O by R1DD )

In MP mode, This functions as 8-bit lower address

output pins. (A0~A7)

33

:

40

R20

:

R27

R2 Port

( Can be determined I/O by R2DD )

In MP mode, This functions as 8-bit higher address

output pins.(A8~A15)

I/O Port

57

:

64

R30

:

R37

R3 Port

( Can be determined I/O by R3DD )

In MP mode, This port functions as 8-bit control bus

for the CPU.

28

:

21

20

:

R40

:

R47

R50

:

R4 Port

I/O

( Can be determined I/O by R4DD )

R5 Port

( Can be determined I/O by R5DD )

13

12

:

R57

R60

:

R6 Port

Input Only

I

9

8

:

R63

R64

:

I/O

R6 Port

( Can be determined I/O by R6DD )

5

R65

6

GMS81508/16

2. FUNCTIONS

2.1. REGISTERS

6 registers are built-in the CPU of G8MC. Accumulator(A), Index register X, Y, Stack Pointer (SP)

and Program Status Word(PSW) consists of 8-bit registers. Program Counter(PC) consists of 16-

bit registers. The contents of these registers are undefined after RESET.

15

8 7

0

PCH

PCL

A

Program Counter

A - Register

7

15

8

7

( YA 16bit Accumulator )

X - Register

Y

A

X

Y

Y - Register

Stack Pointer

Program Status Word

SP

PSW

I

N

V

G

B

H

Z

C

Carry Flag

Zero Flag

Interrupt Enable Flag

Half Carry Flag

Break Flag

G ( Direct Page ) Flag

Overflow Flag

Negative Flag

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2.1.1. A - Register

The accumulator is the 8-bit general purpose register. This is used register for data operation, data

transfer, temporary saves and conditional judgment.

Accumulator can be used as a 16-bit register with Y register and has a lower 8-bit data.

In case of multiplication instruction(MUL), it works as a multiplier. After execution of MUL

instruction, Accumulator has lower 8-bit data of the results(16-bit).

In case of division instruction(DIV), it has the lower 8-bit of dividend (16-bit)

2.1.2. X- Register

In index addressing mode, this register is executed as a 8-bit index register within direct page(RAM

area). also, In indirect addressing mode, it is destination address register.

This register can be used as a increment, decrement, comparison, and data transfer function.

In case of division instruction(DIV), it works as a divisor.

2.1.3. Y- Register

In index addressing mode, this register is executed as a index register.

In case of 16-bit operation instruction, this register has upper 8-bit of YA (16-bit accumulator).

In case of multiplication instruction(MUL), this register is executed as a multiplicand register. After

multiplication operation, it has the upper 8-bit of the result.

In case of division instruction, it is executed as a dividend(upper 8-bit). After division operation, it

has quotient.

This register can be used as a loop counter of conditional branch command. (e.g. DBNE Y, rel)

2.1.4. Stack Pointer

The stack pointer(SP) is an 8-bit register used during subroutine calling and interrupts.

When branching out from an on-going routine to subroutine or interrupt routine, it is necessary to

remember the return address. normally, internal RAM is used for storing the return address and

this area is called stack area. SP is pointer to show where the stack data are stored within the

stack area.

The stack area is located in 1-Page of internal RAM. SP must be initialized by S/W because the

contents of SP is undefined after RESET.

ex)

LDX

#0FEH

;0FEH -> X register

;X -> SP

TXSP

caution) You can't use !01FFH as stack. If you use this area, mal-function would be

occurred.

8

GMS81508/16

Stack Address ( 0100_H01FF_H)

15

8

7

0

SP

01_H

Hardware fixed

The bellows shows data store and restore sequence to/from stack area.

Interrupt

M (sp)

sp

( PCH )

M (sp)

sp

( PCL )

1

M (sp)

( PSW )

sp

1

sp

1

RETI

sp

1

sp

1

sp

1

( PCL )

M (sp)

( PCH)

M (sp)

( PSW )

M (sp)

Subroutine CALL

M (sp)

sp

( PCH )

M (sp)

sp

( PCL )

1

sp

1

sp

RET

sp

1

sp

1

( PCL )

M (sp)

( PCH)

M (sp)

PUSH A ( X, Y, PSW )

POP A ( X, Y, PSW )

M (sp)

A

sp

1

A

M (sp)

sp

1

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2.1.5. Program Counter

The program counter(PC) is a 16-bit counter which consists of 8-bit register PCH and PCL. The

addressing space is 64K bytes.

This counter indicates the address of the next instruction to be executed.

In reset state, the program counter (PC) has reset routine address in address FFFFH and FFFEH .

2.1.6. Program Status Word

PSW is an 8-bit register which is composed of flags to maintain the condition of the processor

immediately after an operation.

After RESET, The contents of PSW is set to "00H".

PSW

7

6

5

4

3

2

I

1

0

N

V

G

B

H

Z

C

Carry Flag ( C )

After an operation, it is set to "1" when there is a carry from bit7 of ALU or not a borrow.

SETC,CLRC instructions allow direct access for setting and resetting.

it can be used as a 1-bit accumulator.

It is a branch condition flag of BCS, BCC instructions.

Zero Flag ( Z )

After an operation including 16-bit operation, it is set to "1" when the result is “0”.

It is a branch condition flag of BEQ, BNE.

Interrupt Enable Flag ( I )

This flag is used to enable/disable all interrupts except interrupt caused by BRK instruction.

When this flag is "1", it means interrupt enable condition. When an interrupt is accept, this flag is

automatically set to "0" thereby preventing other interrupts. also it is set to "1" by RETI instruction.

This flag is set and cleared by EI, DI instructions.

Half Carry Flag ( H )

After an operation, it is set when there is a carry from bit3 of ALU or is not a borrow from bit4 of

ALU.

It can not be set by any instruction. it is cleared by CLRV instruction like V flag.

10

GMS81508/16

Break Flag ( B )

This flag is set by BRK (S/W interrupt) instruction to distinguish BRK and TCALL instruction having

the same vector address.

Direct Page Flag ( G )

This flag assign direct page (0-page, 1-page) for direct addressing mode. When G-flag is "0", the

direct addressing space is in 0-page(0000H~00FFH). When G-flag is "1", the direct addressing

space is in 1-page(0100H~01FFH).

It is set and cleared by SETG, CLRG instruction

Overflow Flag ( V )

This flag functions when one word is added or subtracted in binary with the sign. When results

exceeds +127 or -128, this flag is set.

When BIT instruction is executed, The bit6 of memory is input into V-flag.

This flag is cleared by CLRV instruction, but set instruction is not exist.

It is a branch condition flag of BVS, BVC.

Negative Flag ( N )

N-flag is set when the result of a data transfer or operation is negative (bit7 is “1”).

it means the bit-7 of memory is sign bit. thereby data is valid in the range of -128 ~ +127.

When BIT instruction is executed, The bit7 of memory is input into N-flag.

Set or clear instruction is not exist.

It is a branch condition flag of BPL, BMI instruction.

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2.2. MEMORY SPACE

All RAM ,ROM,I/O, Peripheral Register are placed in the same memory area. Therefore, same

instructions enable both data transfer and operation without the need to distinguish memory and

I/O. The program counter of GMS81508/16 consists of 16-bit and memory addressing space is 64K

byte.

2.2.1. RAM area

RAM(includes stack area) is 448 Bytes ( 0000_H01FF_H).

The internal RAM is used for data storage, subroutine calling or stack area when interrupts occur.

When RAM is used as the stack area, the depth of the subroutine "nesting" and the interrupt levels

should be kept in mind in order to avoid destruction of the RAM contents.

2.2.2. Peripheral Register area

Address 00C0_H00FF_Hare assigned for peripheral register.

2.2.3. Program ROM area

PCALL subroutines must be located in PCALL area ( FF00_HFFBF_H).

TCALL vector area ( FFC0_HFFDF_H) has the vector address corresponding to TCALL

instruction.

Interrupt Vector area ( FFE0_HFFFF_H) has the vector address of interrupts, inclusive RESET.

12

GMS81508/16

Absolute Address

!0000H

RAM

(192 byte)

0-Page

1-Page

!00C0H

Peripheral Registers

Direct Page(dp)

!0100H

RAM(STACK)

(256 byte)

!0200H

Not Used Area

!C000H

!E000H

G

M

S

8

Program ROM

G

M

S

8

1

5

!FF00H

!FFC0H

!FFE0H

1

PCALL Area

6

1

U-Page

TCALL Vector Area

Interrupt Vector Area

5

0

8

VECTOR TABLE

TCALL

INTERRUPT

Address

Vector

Address

Vector

FFC0H - FFC1H

FFC2H - FFC3H

FFC4H - FFC5H

FFC6H - FFC7H

FFC8H - FFC9H

FFCAH - FFCBH

FFCCH - FFCDH

FFCEH - FFCFH

FFD0H - FFD1H

FFD2H - FFD3H

FFD4H - FFD5H

FFD6H - FFD7H

FFD8H - FFD9H

FFDAH - FFDBH

FFDCH - FFDDH

FFDEH - FFDFH

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

TCALL 8

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0

FFE0H - FFE1H

FFE2H - FFE3H

FFE4H - FFE5H

FFE6H - FFE7H

FFE8H - FFE9H

FFEAH - FFEBH

FFECH - FFEDH

FFEEH - FFEFH

FFF0H - FFF1H

FFF2H - FFF3H

FFF4H - FFF5H

FFF6H - FFF7H

FFF8H - FFF9H

FFFAH - FFFBH

FFFCH - FFFDH

FFFEH - FFFFH

not used

Serial I/O

Basic Interval Timer

Watch Dog Timer

A/D Converter

Timer 3

Timer 2

Timer 1

Timer 0

Ext. Int. 3

Ext. Int. 2

Ext. Int. 1

Ext. Int. 0

not used

RESET

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2.2.4. Peripheral Register List

RESET VALUE

SYMBOL R/W

Address

Register Name

7 6 5 4 3 2 1 0

Undefined

00C0_H

00C1_H

00C2_H

00C3_H

00C4_H

00C5_H

00C6_H

00C7_H

00C8_H

00C9_H

00CA_H

00CB_H

00CC_H

00CD_H

00D0_H

00D1_H

00D2_H

R0 PORT DATA REGISTER

R0 PORT I/O DIRECTION REGISTER

R1 PORT DATA REGISTER

R1 PORT I/O DIRECTION REGISTER

R2 PORT DATA REGISTER

R2 PORT I/O DIRECTION REGISTER

R3 PORT DATA REGISTER

R3 PORT I/O DIRECTION REGISTER

R4 PORT DATA REGISTER

R4 PORT I/O DIRECTION REGISTER

R5 PORT DATA REGISTER

R5 PORT I/O DIRECTION REGISTER

R6 PORT DATA REGISTER

R6 PORT I/O DIRECTION REGISTER

PORT R4 MODE REGISTER

PORT R5 MODE REGISTER

TEST MODE REGISTER

R/W

W

R0

R0DD

R0

0 0 0 0 0 0 0 0

Undefined

R/W

W

0 0 0 0 0 0 0 0

Undefined

R0DD

R0

R/W

W

0 0 0 0 0 0 0 0

Undefined

R0DD

R0

R/W

W

0 0 0 0 0 0 0 0

Undefined

R0DD

R4

R/W

W

0 0 0 0 0 0 0 0

Undefined

R4DD

R5

R/W

W

0 0 0 0 0 0 0 0

Undefined

R5DD

R6

R/W

W

0 0 0 0 - - - -

0 0 0 0 0 0 0 0

R6DD

PMR4

PMR5

TMR

BITR

CKCTLR

WDTR

TM0

W

-

- 0 0 - - - -

- - - - 0 0 0

Undefined

W

BASIC INTERVAL REGISTER

CLOCK CONTROL REGISTER

WATCH DOG TIMER

R

00D3_H

W

-

- 0 1 0 1 1 1

W

- 0 1 1 1 1 1 1

00E0_H

00E2_H

TIMER MODE REGISTER 0

R/W 0 0 0 0 0 0 0 0

00E3_H

00E4_H

00E5_H

00E6_H

00E7_H

00E8_H

00E9_H

00EA_H

TIMER MODE REGISTER 2

TM2

TIMER0 DATA REGISTER

R/W

R

Undefined

TDR0

TDR1

TDR2

TDR3

ADCM

ADR

TIMER1 DATA REGISTER

TIMER2 DATA REGISTER

Undefined

TIMER3 DATA REGISTER

Undefined

A/D CONVERTER MODE REGISTER

A/D CONVERTER DATA REGISTER

SERIAL I/O MODE REGISTER

-

- 0 0 0 0 0 1

Undefined

R/W

- 0 0 0 0 0 0 1

SIOM

14

GMS81508/16

RESET VALUE

SYMBOL R/W

Address

Register Name

7 6 5 4 3 2 1 0

Undefined

00

00EB_H

00EC_H

00F0_H

00F1_H

00F2_H

00F3_H

00F4_H

00F5_H

00F6_H

00F7_H

00F8_H

SERIAL I/O REGISTER

R/W

W

SIOR

BUR

BUZZER DRIVER REGISTER

PWM0 DATA REGISTER

W

PWMR0

PWMR1

PWMCR

IMOD

IENL

PWM1 DATA REGISTER

W

PWM CONTROL REGISTER

W

INTERRUPT MODE REGISTER

R/W

- - 0 0 0 0 0 0

INTERRUPT ENABLE REGISTER LOW

INTERRUPT REQUEST FLAG REGISTER LOW

INTERRUPT ENABLE REGISTER HIGH

INTERRUPT REQUEST FLAG REGISTER HIGH

EXT. INTERRUPT EDGE SELECTION REGISTER

0 0 0 0 - - - -

IRQL

R/W 0 0 0 0 0 0 0 0

IENH

IRQH

W

0 0 0 0 0 0 0 0

IEDS

-: Not Used

Write Only Register can not be accessed by bit manipulation instruction.

15

HYUNDAI MicroElectronics

2.3. CLOCK GENERATION CIRCUIT

The clock generation circuit of GMS81508/16 consists of oscillation circuit, prescaler, Basic Interval

Timer.

The source clock of peripherals is provided by 11-bit prescaler.

OSC

Circuit

Clock Pulse Generator

Internal System Clock

IFBIT

Prescaler

ENPCK

MUX

B.I.T.(8)

W.D.T.(6)

6

WDTCL

8

BTCL

Comparator

6

IFWDT

To RESET

Circuit

WDTR

6

0

1

2

3

4

5

6

7

CKCTLR

Internal Data Bus

2.3.1. Oscillation Circuit

The clock signal incoming from crystal oscillator or ceramic resonator via Xin and Xout or from

external clock via Xin is supplied to Clock Pulse Generator and Prescaler.

The internal system clock for CPU is made by Clock Pulse Generator, and several peripheral clock

is divided by prescaler.

The clock generation circuit of crystal oscillator or ceramic resonator is shown in below.

Cout

Open

Xout

Xin

Xout

Xin

External

Clock

GND

Cin

Crystal Oscillator or Ceramic Resonator

External clock

In STOP Mode, The oscillation is stopped,

Xin pin goes to "L" level status, and Xout pin goes to "H" level state.

16

GMS81508/16

2.3.2. Prescaler

The prescaler consists of 11-bit binary counter, and input clock is supplied by oscillation circuit. The

frequency divided by prescaler is used as a source clock for peripherals.

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9 PS10 PS11

fex

ENPCK

B.I.T.

8

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

PS11

PS0

Internal Data Bus

Peripherals

Frequency-Divided Outputs of Prescaler

f_ex

(

)

PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11

4

2

1

500

2

250

4

125

8

62.5

16

31.25

32

15.36

64

7.18

128

3.59

256

Interval

Period

8

250

500

1

The peripheral clock supplied from prescaler can be stopped by ENPCK. (However, PS11 cannot

be stopped by ENPCK)

W

5

W

4

W

3

W

2

W

1

W

0

7

6

CKCTLR

<00D3_H>

ENPCK

WDTON

BTCL BTS2 BTS1 BTS0

Enable Peripheral Clock

0 : stop

1 : supply

17

HYUNDAI MicroElectronics

2.4. BASIC INTERVAL TIMER

The Basic Interval Timer(B.I.T.) has 8-bit binary counter. The operations is shown below.

. Generates reference time interval interrupt request as a timer.

. The counting value of B.I.T. can be read.

( Note; The writing at same address overwrites the CKCTLR.)

. The overflow of B.I.T be used the source clock of Watch Dog Timer.

Internal Data Bus

CKCTLR

WDTON ENPCK

BTCL BTS2 BTS1 BTS0

Same address

when read, it can be read as

counter value. When write, it can

be write as control register.

PS4

PS5

BITR

PS6

PS7

bit7

bit6

bit3

bit2

bit1

bit0

MUX

bit5

bit4

IFBIT

PS8

PS9

PS10

PS11

Internal Data Bus

2.4.1. Control of Basic Interval Timer

The Basic Interval Timer is free running timer. When the counting value is changed "0FFH" to

BTCL

"00H" , The interrupt request flag is generated. The counter can be cleared by setting

(Bit 3

of CKCTLR) and the BTCL is auto-cleared after 1 machine cycle. The initial state (after Reset) of

“ ”

BTCL is 0 .

The input clock of Basic Interval Timer is selected by BTS2~BTS0 (Bit2~0 of CKCTLR) among the

prescaler outputs (PS4~PS11).

The Basic Interval Timer Register (BITR) can be read.

The CKCTLR and the BITR have a same address (00D3H). So, If you write to this address, the

CKCTLR would be controlled. If you read this address, the counting value of BITR would be read.

CLOCK CONTROL REGISTER

W

5

W

4

W

3

W

2

W

1

W

0

7

6

CKCTLR

WDTON ENPCK

BTS2 BTS1 BTS0

BTCL

<00D3_H>

B.I.T. input clock selection

B.I.T. CLEAR ( When writing )

0 : B.I.T. Free-run

1 : B.I.T. Clear ( auto cleared after 1 machine cycle )

18

GMS81508/16

BASIC INTERVAL TIMER DATA REGISTER

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

BITR

<00D3_H>

B.I.T data

2.5. WATCH DOG TIMER

The Watch Dog Timer is a means of recovery from a system problem.

In this Device, the Watch Dog Timer consists of 6-bit binary counter, 6-bit comparator and watch

dog timer register(WDTR). The source clock of WDT is overflow of Basic Interval Timer. The

interrupt request of WDT is generated when the counting value of WDT equal to the contents of

WDTR( bit0~5). This can be used as s/w interrupt or MICOM RESET signal(Watch Dog Function).

2.5.1. Control of Watch Dog Timer

It can be used as 6-bit timer or WDT according to bit5(WDTON) of Clock Control Register

(CKCTLR). The counter can be cleared by setting WDTCL ( Bit 6 of WDTR) and the WDTCL is

auto-cleared after 1 machine cycle. The initial state (after Reset) of WDTCL is “0”.

CLOCK CONTROL REGISTER

W

5

W

4

W

3

W

2

W

1

W

0

7

6

CKCTLR

WDTON ENPCK

BTCL BTS2 BTS1 BTS0

<00D3_H>

WDT ON

0 : 6-bit Timer

1 : Watch Dog Timer

WATCH DOG TIMER REGISTER

W

4

W

3

W

2

W

1

W

0

W

7

W

6

W

5

WDTR

WDTR5

WDTR4 WDTR3 WDTR2 WDTR1 WDTR0

WDTCL

<00E0_H>

Watch Dog Timer Clear

Determines the interval of W.D.T Interrupt

0 : free run

1 : W.D.T counter clear

19

HYUNDAI MicroElectronics

The interval of WDT interrupt is decided by the interrupt interval of Basic Interval Timer and the

contents of WDTR.

The interval of WDT = The contents of WDTR

Caution) Do not use the contents of WDTR = "0"

The interval of B.I.T.

The relationship between the input clock of B.I.T and the output of W.D.T. (@8MHz)

BTS2 BTS1 BTS0

B.I.T. Input Clock

The cycle of B.I.T.

512

The cycle of W.D.T.(max)

32,256

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PS4 ( 2

PS5 ( 4

)

1,024

64,512

PS6 ( 8

2,048

129,024

PS7 ( 16

PS8 ( 32

PS9 ( 64

PS10 ( 128

PS11 ( 256

)

4,096

258,048

)

8,192

516,096

16,384

32,768

65,536

1,032,192

2,064,384

4,128,768

)

2.5.2. The output of WDT signal

The overflow of WDT can be output through R54/WDT O port by setting bit4 of PMR5(WDTS) to

"1".

PORT R5 MODE REGISTER

W

5

W

4

7

-

6

-

3

-

2

-

1

-

0

-

PMR5

BUZS WDTS

<00D1_H>

R54/WDT O Selection

0 : R54 ( Input / Output )

1 : WDTO ( Output )

20

GMS81508/16

2.6. TIMER

The GMS81508/16 has four multi-functional 8-bit binary timers(Timer0~Timer3).

Timer0 (or Timer2) is can be used as a 16-bit timer/event counter with Timer1(or Timer3). The

Timer0-1 and Timer2-3 have same functions and structures. So, We will explains about Timer0 and

Timer1 only.

Internal Data Bus

7

8

TDR0

TDR1

TM0

Data Reg. 0

8

Data Reg. 1

8

7

6 5 4 3 2 1 0

T0CN

T0ST

Comparator 0

8

Comparator 1

8

CAP0

2

ck

EC0

PS2

PS4

T 0

T 1

MUX

Clea

0

PS6

MUX

1

2

IFT1

16bit Mode

PS2

MUX

PS4

PS6

1

IFT0

MUX

0

MUX

0

T1ST

INT0

INTR0

EDGE

F / F

T1O

Operation Mode of Timer

Timer0,Timer2

Timer1,Timer3

-. 8-bit Interval Timer

-. 8-bit Event Counter

-. 8-bit input capture

-. 8-bit Interval Timer

-. 8-bit rectangular pulse

output

-. 16-bit Interval Timer

-. 16-bit Event Counter

-. 8-bit rectangular pulse output

21

HYUNDAI MicroElectronics

TIMER MODE REGISTER 0,2(TM0,TM2)

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

TM0

<00E2_H>

CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0

Input Capture Selection

0 : Timer/Counter

T0 Input Clock Selection

00 : EC0

1 : Input Capture

01 : PS2 ( 500

)

10 : PS4 (

11 : PS6 (

2

8

)

T1 Start/Stop control

0 : Cout Stop

T0 Start/Stop control

0 : COUNT Stop

1 : COUNT Start

1 : Counting start after clearing T1

T1 Input Clock Selection

T0 Start/Stop control

0 : Count Stop

1 : Counting start after clearing T0

00 : Connection to T0 (16bit Mode )

01 : PS2 ( 500

)

10 : PS4 (

11 : PS6 (

2

8

)

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

TM2

<00E3_H>

CAP2 T3ST T3SL1 T3SL0 T2ST T2CN T2SL1 T2SL0

Input Capture Selection

0 : Timer/Counter

T2 Input Clock Selection

00 : EC2

1 : Input Capture

01 : PS2 ( 500

)

10 : PS4 (

11 : PS6 (

2

8

)

T3 Start/Stop control

0 : Cout Stop

T2 Start/Stop control

0 : COUNT Stop

1 : COUNT Start

1 : Counting start after clearing T3

T3 Input Clock Selection

T2 Start/Stop control

0 : Count Stop

1 : Counting start after clearing T2

00 : Connection to T2 (16bit Mode )

01 : PS2 ( 500

)

10 : PS4 (

11 : PS6 (

2

8

)

TIMER DATA REGISTER(TDR0 ~ TDR3)

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

TDR0~3

<00E4_H~00E7_H>

( READ )

( WRITE)

Count Value Read

Modulo Data Write

22

GMS81508/16

2.6.1. Control of Timer

T0 ( T1 ) consists of 8-bit Binary Up-Counter. When the counting value of Timer0 , Timer1 and

Timer0-1(16bit) become equal to the contents of Timer Data Register(TDR0,TDR1,TDR0-1) value,

the counter is cleared to "00H" and restarts count-up operation. At this time, Interrupt request (IFT0

or IFT1) is generated.

MATCH

TDR0 VALUE

T0 VALUE

00_H

Clear

Interrupt

IFT0

Interval Period

Any of the PS2, PS4, PS6 or external clock can be selected as the clock source of T0 by

bit1(T0SLI) and bit0(T0SL0) of TM0. Any of the PS2, PS4, PS6 or overflow of T0 can be selected

as the clock source of T1 by bit5(T1SL1) and bit4(T1SL0) of TM0. When the overflow of T0 is

selected as input clock of T1, Timer0-1 operates as 16 -bit timer. In this case, Timer0-1 only is

controlled by T0ST,T0CN and the interrupt vector is Timer0 vector.

The operation of T0, T1 is controlled by bit3(T0ST), bit2(T0CN) and bit6(T1ST) of TM0. T0CN

controls count stop/start without clearing counter. T0ST and T1ST control count stop/start after

“ ”

timer clear. In order to enable count-up of timer , T0CN, T0ST and T1ST should become 1 . In

order to start count-up after clearing of counter, T0ST or T1ST should be set to "1" after set to "0"

temporarily.

MATCH

TDR0 VALUE

T0 VALUE

00_H

Clear

Interrupt

IFT0

“0”

“1” Clear & Start

T0ST

“0”

“1” Start

T0CN

COUNTER

Stop

Count

Stop

Count

23

HYUNDAI MicroElectronics

By read Timer Data Register(TDR0~3),The counting value of timer can be read at any time.

2.6.2. Interval Timer

The interrupt cycle is determined by the source clock of timer and the contents of TDR.

Interrupt cycle = source clock

the contents of TDR

In order to write data to TDR, you have to stop timer. otherwise, TDR value is invalid.

Maximum Interrupt Cycle according to source clock

8-bit TIMER Mode

source clock max. count

@ fex=8MHz

16-bit TIMER Mode

source clock

PS2 ( 0.5 )

max. count

32,768

)

128

512

PS2 ( 0.5

T0,T2

T1,T3

PS4 (

PS6 (

2

8

)

PS4 (

PS6 (

2

8

)

131,072

524,288

2,048

128

PS2 ( 0.5

)

PS4 (

PS6 (

2

8

)

512

2,048

2.6.3. Event Counter

The event counter operates in the same way as the interval timer except it counts the external

event input from R44/EC0 and R45/EC1 port. it only counts at the falling edge of event input clock.

In order to input of external event clock, the relevant Port Mode Register(bit4,bit5 of PMR4) is set

to "1". TDR value should be initialized to “FFH” because timer is cleared when it equals to TDR

value, but if you want to use interrupt, TDR value should be written to "1H~FFH".

2.6.4. Pulse Output

A pulse width 50% cycle duty is output to the R46/T1 O or R47/T3 O port and reverse the output

when timer interrupt is generated. This creates a pulse period which is two times that of the timer

interrupt cycle. The output pulse period is determined by the source clock of timer and the contents

of TDR.

output period = source clock(

)

the contents of TDR

2

In order to output of pulse, the bit6,bit7 of PMR4 is set to "1".

2.6.5. Input Capture

This function measures the period or width of pulse input from external INT. (R40/INT0, R42/INT2)

port. The period of pulse is measured by selecting rising edge or falling edge of the interrupt edge

select register(IEDS) and the width of pulse is measured by selecting both edge of IEDS.

The external interrupt is generated at the valid edge according to IEDS. At this time, The counting

value of timer is loaded into TDR and counter is cleared and restarts count-up.

24

GMS81508/16

Rising Edge

Period

Falling Edge

“H”Width

“L”Width

R40/INT0

or

R42/INT2

Both Edge

Timer Operation

the counting value of timer is latched

timer is cleared to 00H

timer restart count-up

PORT R4 MODE REGISTER

W

5

W

3

W

6

W

4

W

1

W

0

W

2

7

PMR4

EC2S

INT3S INT2S INT1S

INT0S

T3S

T1S

EC0S

<00D0_H>

R40 / INT0 Selection

0 : R40 ( Input / Output )

1 : INT0 ( Input )

R47 / T3 Selection

0 : R47 ( Input / Output )

1 : T3 ( Output )

R42 / INT2 Selection

0 : R42 ( Input / Output )

1 : INT2 ( Input )

R44/ EC0 Selection

0 : R44 ( Input / Output )

1 : EC0 ( Input )

R46 / T1 Selection

0 : R46 ( Input / Output )

1 : T1 ( Output )

R45/ EC2 Selection

0 : R45 ( Input / Output )

1 : EC2 ( Input )

25

HYUNDAI MicroElectronics

2.7. EXTERNAL INTERRUPT

An interrupt request is generated when a level-change from "H" to "L" or "L" to "H" of

INT0,INT1,INT2,INT3 pin is detected. The edge of external interrupt is selected by interrupt edge

selection register(IEDS) and ports(R40,R41,R42,R43) corresponding to INT0,INT1,INT4,INT3 are

determined as a input port for external interrupt by bit0~3 of port4 mode register(PMR4).

W

5

W

3

W

6

W

4

W

1

W

0

W

7

W

2

PMR4

EC2S

T3S

T1S

EC0S

INT2S

INT3S

INT1S INT0S

<00D0_H>

R40 / INT0 Selection

0 : R40 ( Input / Output )

1 : INT0 ( Input )

R43 / INT3 Selection

0 : R43 ( Input / Output )

1 : INT3 ( Input )

R42 / INT1 Selection

0 : R42 ( Input / Output )

1 : INT2 ( Input )

R41 / INT1 Selection

0 : R41 ( Input / Output )

1 : INT1 ( Input )

EXT. INTERRUPT EDGE SELECTION REGISTER

W

2

W

0

W

1

W

7

W

6

W

5

W

4

W

3

IEDS

IED3H IED3L IED2H IED2L

IED1H IED1L IED0H IED0L

<00F8_H>

INT0 Edge Selection

00 : -

01 : Falling

10 : Rising

11 : Falling & Rising

INT3 Edge Selection

00 : -

01 : Falling

10 : Rising

11 : Falling & Rising

INT2 Edge Selection

00 : -

01 : Falling

10 : Rising

11 : Falling & Rising

INT1 Edge Selection

00 : -

01 : Falling

10 : Rising

11 : Falling & Rising

26

GMS81508/16

2.8. A/D CONVERTER

A/D Converter has an 8-bit resolution, and input is possible up to 8 channel.

A/D Converter consists of Analog Input Multiplexer, A/D convert Mode Register, Resistance Ladder,

Sample and Holder, Successive Approximation Circuit and A/D Conversion Data Register.

Ladder

Resistor

Decoder

AVref

AVss

AN0

AN1

COMPARATOR

Successive

Approximation

Circuit

AN2

AN3

AN4

AN5

AN6

AN7

IFA

MUX

S/H

Control Register

A/D Conversion

Data Register(8bit)

-

ADEN ADS2 ADS1 ADS0 ADST ADSF

Internal Data Bus

2.8.1. Control of A/D Converter

The analog input is selected by bit2~4 of A/D Converter Mode Register(ADCM). This bits chooses

among AN0~AN7. The other analog pins which are not used not A/D conversion be used as

normal port.

The A/D Conversion is started by setting A/D Conversion Start bit (ADST) to "1"(only for ADEN=1).

After A/D Conversion is started, ADST is cleared by hardware. During A/D Conversion, when

ADST is set to "1", A/D Conversion starts again from the beginning.

The analog input voltage and the reference voltage are compared and the result is stored in the

A/D Converter Data Register(ADR) and ADSF(bit0 of ADCM) is set to "1". The A/D interrupt

request is generated at the completion of A/D conversion.

The result of the conversion is obtained by reading out the A/D register(ADR).

27

HYUNDAI MicroElectronics

A/D CONVERTER MODE REGISTER(ADCM)

-

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

RR/W

0

7

6

ADCM

ADS2 ADS1 ADS0 ADST ADSF

ADEN

<00E8_H>

A/D Conversion Status bit

0 : during A/D Conversion

1 : completed A/D Conversion

A/D Converter Enable bit

0 :Disable A/D Converter

A/D Converter input select

000 : channel 0(AN0)

001 : channel 1(AN1)

010 : channel 2(AN2)

011 : channel 3(AN3)

100 : channel 4(AN4)

101 : channel 5(AN5)

110 : channel 6(AN6)

111 : channel 7(AN7)

1 : Enable A/D Converter

A/D Conversion Start bit

0 : invalid

1 : Start A/D Conversion

(after 1 cycle, be cleared to "0")

A/D CONVERTER DATA REGISTER(ADR)

R

5

R

4

R

3

R

2

R

1

R

0

R

7

R

6

ADR

<00E9_H>

A/D Conversion Data

28

GMS81508/16

2.9. SERIAL I/O

The serial I/O is 8-bit clock synchronous type and consists of serial I/O register, serial I/O mode

register, clock selection circuit octal counter and control circuit.

Internal Data BUS

6

7

6

0

Srdy SM1 SM0 SCK1 SCK0 SIOST SOSF

SIOM

Srdy

SM1

SM0

2

PS3

Control

Circuit

PS4

PS5

Octal Counter

MUX

IFSIO

Exclk

Sclk

R

Srdy0

Q

S

Srdy In

Sout

Sin

7

6 5 4 3 2 1 0

SIOR

8

Internal Data BUS

29

HYUNDAI MicroElectronics

Serial I/O Mode Register

This register controls serial I/O function. According to SCK1 and SCK0, the internal clock or

external clock can be selected.

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R

0

7

SIOM

Srdy SM1 SM0 SCK1 SCK0 SIOST SIOSF

<00EA_H>

Serial Transmission Status Flag

0 : during transmission

1 : finished

R53/Srdy Selection

0 : R53

1 : Srdy

Serial Transmission Start

0 : Invalid

1 : Start(After one SCK, becomes”0”)

Serial Operation Mode

00 : Normal Port(R52,R51,R50)

01 : Sending Mode(Sclk,Sout,R50)

10 : Receiving Mode(Sclk,R51,Sin)

11 : Sending & Receiving

Serial Transmission Clock Selection

00 : PS3 ( 1

01 : PS4 ( 2

10 : PS5 ( 4

)

M d (S lk S

Si )

11 : External Clock

Serial I/O Data Register

The Serial I/O Data Register (SIOR) is a 8-bit shift register. First LSB is send or is received.

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

SIOR

D7

D6

D5

D4

D3

D2

D1

D0

<00EB_H>

At transmittion

Sending Data at Sending Mode

Receiving Data at Receiving Mode

30

GMS81508/16

2.9.1. Data Transmission/Receiving Timing

” ”

The serial transmission is started by setting SIOST(bit1 SIOM) to 1 . After one cycle of SCK,

“ ”

SIOST is cleared automatically to 0 . The serial output data from 8-bit shift register is output at

falling edge of Sclk. and input data is latched at rising edge of Sclk. When transmission clock is

“ ”

counted 8 times, serial I/O counter is cleared as 0 . Transmission clock is halted in H state

and serial I/O interrupt (IFSIO) occurred.

Input Clock

Sclk

SIOST

Output

Sout

Sin

D0

D1

D2

D3

D4

D5

D6

D7

Latch

D1

IFSIO

Timing Diagram of Serial I/O

2.9.2. The Serial I/O operation by Srdy pin

transmission clock = external clock

The Srdy pin becomes "L" by SIOST = "1". This signal tells to the external system that this device

is ready for serial transmission. The external system detects the "L" signal and starts transmission.

The Srdy pin becomes "H" at the first rising edge of transmission clock.

SIOST

Srdy(Output)

transmission clock = internal clock

The I/O of Srdy pin is input mode. When the external system is ready to for serial transmission, the

"L" level is inputted at this pin. At this time this device starts serial transmission.

SIOST

Srdy(Input)

31

HYUNDAI MicroElectronics

2.9.3. The method of Serial I/O

Select transmission/receiving mode

<Notice> When external clock is used, the frequency should be less than 1MHz and

recommended duty is 50%.

In case of sending mode, write data to be send to SIOR.

“ ”

Set SIOST to 1 to start serial transmission.

<Notice > If both transmission mode is selected and transmission is performed simultaneously

it would be made error.

“ ”

The SIO interrupt is generated at the completion of SIO and SIOSF is set to 1 . In SIO

interrupt service routine, correct transmission should be tested.

In case of receiving mode, the received data is acquired by reading the SIOR.

2.9.4. The Method to Test Correct Transmission with S/W

Serial I/O Interrupt

Service Routine

0

SIOSF

1

SE=0

Abnormal

Write SIOM

1

SR

0

Normal Operation

Overrun Error

Serial Method to Test Transmission.

Note) SE:

SR :

IENL ( Bit3 )

Interrupt Enable Regist Low

IRQL ( Bit3 )

Interrupt Request Flag Regist Low

32

GMS81508/16

2.10. PWM

PWM(Pulse Width Modulation) has a 8-bit resolution and the PS8,PS9,PS10,PS11 of the prescaler

can be selected as input clock PWM.

Internal Data Bus

PWMR0

Overflow

S

Comparator

Counter

Q

Polarity

R

PWM0

PS8

PS9

PS10

PS11

MUX

P1CK1 P1CK0 P0CK1 P0CK0 EN1

EN0

POL1 POL0

PWMCR

PS8

PS9

PS10

PS11

Counter

Comparator

PWMR1

MUX

Overflow

S

Q

Polarity

R

PWM1

Internal Data Bus

2.10.1. Controls of PWM

The input clock is selected by PWM Control Register (PWMCR), and the width of pulse is

determined by the PWM Register (PWMR).

The pulse period according to input clock are as follows.

Input clock

PWM Period

PS8 (32

PS9 (64

)

8,192

16,384

32,768

65,536

PS10 (128

PS11 (256

)

Bit2 (EN0) and bit3 (EN1) of PWM control Register (PWMCR) determine the operation channel of

PWM. When EN0=0 and EN1=0, PWM does not executed. The EN0 and EN1 are Enable bit of

PWM channel 0 and channel 1 respectively. When EN0=1, PWM channel0 executes. When EN1=1,

PWM channel1 executes.

POLO and POL1 are a polarity control bit of channel0 and channel1. When they are 0, LOW

active. When 1, HIGH active. PWMCR becomes "00h" in reset state.

33

HYUNDAI MicroElectronics

(a) Active Low

period

(b) Active High

period

pulse width

Counter Load Value + 1

256

Duty Cycle =

100[%]

PWM CONTROL REGISTER

W

0

7

6

5

4

3

2

1

PWMCR

P0CK P0CK

PICK1 PICK0

EN1

EN0 POL1 POL0

<00F2_H>

1

0

PWM0 Output Polarity

0 : Active Low

1 : Active High

PWM1 Clock Selection

00 : PS8

01 : PS9

10 : PS10

11 : PS11

PWM1 Output Polarity

0 : Active Low

1 : Active High

PWM0 Clock Selection

00 : PS8

01 : PS9

10 : PS10

11 : PS11

PWM Enable Flag

00 : Disable

01 : PWM0

10 : PWM1

11 : PWM0,PWM1

PWM DATA REGISTER

W

7

W

6

W

5

W

4

W

3

W

2

W

1

W

0

PWMR0

PWMR1

<00F0_H>

<00F1_H>

PWM DATA

34

GMS81508/16

2.11. BUZZER DRIVER

Buzzer driver consist of 6 bit binary counter, Buzzer Register(BUR), and selector of clock. The wide

range frequency(500Hz~250KHz) can be generated using programmable counter. PORT R55 is

assigned for output port of Buzzer Driver by setting bit5 of PMR5($00D1H) to "1".

Internal Data Bus

BUCK1 BUCK0 BU5

BU4

BU3

BU2

BU1

BU0

WtBUR

6

PS4

PS5

PS6

PS7

0

1

2

3

4

5

T

Q

MUX

Buzzer

Output

6bit Counter

PORT R5 MODE REGISTER

W

5

W

7

6

-

4

3

-

2

1

-

0

-

PMR5

WDTO

-

BUZ

<00D1_H>

R55 / BUZ Selection

0 : R55 ( Input / Output )

1 : BUZ ( Output )

BUZZER DATA REGISTER

W

6

W

4

W

3

W

2

W

1

W

0

W

5

7

BUR

BUCK1 BUCK0

BU5

BU4

BU3

BU2

BU1

BU0

<00EC_H>

Buzzer Count Data

Buzzer Source Clock

Selection

00 : PS4

01 : PS5

10 : PS6

11 : PS7

35

HYUNDAI MicroElectronics

2.11.1. Buzzer Driver Operation

The bit0-5 of Buzzer Register (BUR) determines output frequency for buzzer driving. The frequency

is calculated as shown bellows.

N = BUR data

freq. = 1/(source clock ✕ N ✕ 2)

The bit6 and bit7 of Buzzer register (BUR) selects the source clock of the buzzer counter among

PS4 (2us), PS5 (4us), PS6 (8us) and PS7 (16us).

The buzzer counter is cleared by Wt signal of BUR and starts the counting. also, It is cleared by

counter overflow, and continues count-up to output the rectangular wave of duty 50%.

* Caution: don't use BUR register as 00H. (counter reset state)

The output frequency of buzzer according to Buzzer Register bit5 - bit0 (fex = 8 MHz)

REG.

LOAD LOAD

DEC

1

2

3

4

5

6

REG.

OUTPUT FREQUENCY[KHz]

REG.

LOAD

DEC

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

REG.

LOAD

HEX

21

22

23

24

25

26

27

OUTPUT FREQUENCY[KHz]

PS4

(2us)

250

PS5

(4us)

125

PS6

(8us) (16us)

62.5 31.25

31.25 15.626

PS7

PS4

PS5

PS6

PS7

HEX

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

(2us)

(4us) (8us) (16us)

7.576 3.788 1.894 0.947

7.352 3.676 1.838 0.919

7.142 3.571 1.786 0.893

6.944 3.472 1.736 0.868

6.756 3.378 1.689 0.845

6.578 3.289 1.645 0.822

125

62.5

83.333 41.666 20.834 10.416

62.5

50

31.25 15.626 7.812

25 12.5 6.25

41.666 20.834 10.416 5.208

35.714 17.858 8.928 4.464

31.25 15.626 7.812 3.906

27.778 13.888 6.944 3.472

7

8

9

6.41

6.3

3.205 1.602 0.801

3.125 1.563 0.781

28

29

6.098 3.049 1.524 0.762

5.952 2.976 1.488 0.744

5.814 2.907 1.453 0.727

5.682 2.841 1.421 0.710

5.556 2.778 1.389 0.694

5.434 2.717 1.359 0.679

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

25

12.5

6.25

3.126

2A

2B

2C

2D

2E

2F

30

31

32

33

34

22.728 11.364 5.682

2.84

20.834 10.416 5.682 2.604

19.23 9.616 4.808 2.404

17.858 8.928 4.464 2.232

16.666 8.334 4.166 2.084

15.626 7.812 3.906 1.9541

14.706 7.352 3.676 1.838

13.888 6.944 3.472 1.736

13.158 6.579 3.288 1.644

5.32

2.660 1.33 0.665

5.208 2.604 1.302 0.651

5.102 2.551 1.276 0.638

5

2.5

1.25 0.625

4.902 2.451 1.225 0.613

4.808 2.404 1.202 0.601

4.716 2.358 1.179 0.590

12.5

6.25

3.124 1.562

11.904 5.952 2.976 1.488

11.364 5.682 2.840 1.420

35

36

37

38

4.63

2.315 1.157 0.579

10.87

5.434 2.718 1.358

4.546 2.273 1.136 0.568

4.464 2.232 1.116 0.558

4.386 2.193 1.096 0.548

10.416 5.208 2.604 1.302

10

5

2.5

1.250

39

9.616

9.26

8.928

8.62

8.334

8.064

7.812

4.808 2.404 1.202

4.630 2.314 1.158

4.464 2.232 1.116

4.310 2.156 1.078

4.166 2.084 1.042

4.032 2.016 1.008

3.906 1.954 0.976

3A

3B

3C

3D

3E

3F

4.31

2.155 1.078 0.539

4.238 2.119 1.059 0.530

4.166 2.083 1.042 0.521

4.098 2.049 1.025 0.512

4.032 2.016 1.008 0.504

3.968 1.984 0.992 0.496

36

GMS81508/16

2.12. INTERRUPTS

The interrupts are usually used when the processing routine has the higher priority than on-going

program and a routine muse be executed at specific interval.

2.12.1. Interrupt Circuit Configuration and Kinds

GMS81508/16 Interrupt circuits consists of Interrupt Enable Register (IENH,IENL), Interrupt

Request Register (IRQH,IRQL), priority circuit and selecting circuit.

The configuration of Interrupt circuit is shown in below.

Data BUS

6

8

IMOD

IENH

0

1 2 3 4 5

0

1

2

3 4 5 6 7

RESET

4

IRQH

7

IFT3

IFT2

IFT1

IFT0

INT3

INT2

INT1

INT0

T3R

T2R

T1R

T0R

Standby

Mode

Release

INT3R

INT2R

INT1R

INT0R

PRIORITY

CONTROL

to CPU

0

7

I-FLAG

IFA

IFWDT

IFBIT

IFS

AR

WDTR

BITR

SR

BRK

12

4

IRQL

INTERRUPT

VECTOR

ADDRESS

GEN.

7

6

5

4

4 -

IENL

4

8

Data BUS

37

HYUNDAI MicroElectronics

Interrupt Source

The interrupts sources are external interrupt source(INT0, INT1,INT2,INT3), peripheral function

source (T0,T1,T2,T3,B.I.T.,W.D.T.,SIO,A/DC) and software interrupt source(BRK).

After reset input(RESET), the program is executed from the address in reset vector table like

general interrupts.

Type

Mask

Priority

1

Interrupt Request Source

Reset Pin

Vector Vector

H

L

Non

RST

FFFF_HFFFE_H

Maskable

2

3

INT0R External Interrupt 0

INT1R External Interrupt 1

INT2R External Interrupt 2

INT3R External Interrupt 3

FFFB_HFFFA_H

FFF9_HFFF8_H

FFF7_HFFF6_H

FFF5_HFFF4_H

FFF3_HFFF2_H

FFF1_HFFF0_H

FFEF_HFFEE_H

FFED_HFFFC_H

FFEB_HFFEA_H

FFE9_HFFE8_H

FFE7_HFFE6_H

FFE5_HFFE4_H

FFDF_HFFDE_H

4

H/W

5

Interrupt

6

T0R

T1R

T2R

T3R

AR

Timer 0

7

Timer 1

8

Timer 2

9

Timer 3

10

11

12

13

A/D Converter

WDTR Watch Dog Timer

BITR

SR

Basic Interval Timer

Serial I/O

S/W Interrupt

Non

BRK

Break Instruction

Maskable

2.12.2. Interrupt Control

The interrupts is controlled by the interrupt master enable flag I-Flag(3'rd bit of PSW), interrupt

enable register(IENH,IENL), interrupt request register(IRQH,IRQL) except RESET and S/W

interrupt.

Interrupt Enable Register ( IENH, IENL)

This register is composed of interrupt enable flags of each interrupt source, this flags determines

whether an interrupt will be accepted or not. when enable flag is "0", an interrupt corresponding

interrupt source is prohibited.

38

GMS81508/16

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

IENH

INT0E INT1E INT2E INT3E T0E

T1E

T2E

T3E

<00F6_H>

R/W

7

R/W

6

R/W

5

R/W

4

-

3

2

1

0

IENL

-

AE WDTE BITE

SE

-

<00F4_H>

Interrupt Masking Flag

0 : Interrupt Disable

1 : Interrupt Enable

Interrupt Request Flag Register ( IRQH, IRQL)

Whenever interrupt request is generated, the interrupt request flag is set. The request flag

maintains '1" until interrupt is accepted. The accepted interrupt request flag is automatically cleared

by interrupt process cycle. Interrupt Request Flag Register ( IRQH, IRQL) is Read/ Write Register.

So, it is possible to be checked and changed by program.

R/W

5

R/W

4

R/W

1

R/W

0

R/W

7

R/W

6

R/W

3

R/W

2

IRQH

T2R

INT0R INT1R INT2R INT3R T0R

T1R

T3R

<00F7_H>

R/W

7

R/W

6

R/W

5

R/W

4

-

3

2

1

0

IRQL

-

AR WDTR BITR

SR

<00F5_H>

Interrupt Request Flag

0 : Disable

1 : Enable

2.12.3. Interrupt Priority

When two or more interrupts requests are generated at the same sampling point, the interrupt

having the higher priority is accepted. The interrupt priority is determined by H/W. however,

multiple priority processing through software is possible by using interrupt control flags(IENH, IENL,

I-flag) and interrupt mode register(IMOD).

39

HYUNDAI MicroElectronics

2.12.4. Interrupt Sequence

When interrupt is accepted, the on-going process is stopped and the interrupt service routine is

executed. After the interrupt service routine is completed it is necessary to restore everything to the

state before the interrupt occurred.

As soon as an interrupt is accepted, the contents of the program counter and the program status

word are saved in the stack area. At the same time, the contents of the vector address

corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the

program counter and interrupt service routine is executed.

In the interrupt service routine, the corresponding interrupt request flag is cleared and interrupt

master enable flag(I-flag) becomes "0", thereby another interrupts are not accepted before I-flag is

set to "1" by program.

In order to execute the interrupt service routine, it is necessary to write the jump address(the first

address of the interrupt service routine) in vector table corresponding to each interrupt.

System Clock

Instruction

Fetch

0

12 Cycles

1 Cycles

8 Cycles

A command before

Interrupt

Interrupt Process Step

Interrupt routine

Int.request Sampling

Interrupt Overhead :

9

21 Cycles

Interrupt Accept Timing

The valid timing after executing Interrupt control Flag

I-Flag is valid, after EI, DI executed

IENH, IENL register is valid after next instruction

40

GMS81508/16

System Clock

Instruction

Fetch

Address Bus

Data Bus

pc

sp

sp-1

sp-2

V.L

V.H

new pc

not Used

PCH PCL PSW

V.L

ADL ADH

Opcode

Internal Read

Internal Write

Interrupt Process Step

Interrupt Service Routine

V.L, V.H is Vector Address, ADL, ADH is start Address of Interrupt

Service Routine as Vector Contents

Interrupt Process Step Timing

2.12.5. Software Interrupt

The interrupt is the lowest priority order software interrupt by BRK instruction. B-flag is set.

Interrupt vector of BRK instruction is shared with the vector of TCALL 0. Each processing step is

determined by B-Flag as a below.

0

B-Flag ?

BRK or TCALL0

1

BRK Interrupt Routine

TCALL 0 Routine

RET

RETI

Execution of BRK/ TCALL0

41

HYUNDAI MicroElectronics

2.12.6. Multiple Interrupt

When an interrupt is accepted, and program flow goes to the interrupt service routine. The interrupt

master enable flag(I-flag) is automatically cleared and other interrupts are inhibited. When interrupt

service is completed by RETI instruction, I-flag is set automatically. If other interrupts are generated

during interrupt service, The interrupt having higher priority is accepted when the previous interrupt

service routine is completed.

In order to multiple interrupts, I-flag must be cleared by EI instruction within the interrupt routine.

Then, The higher priority interrupt is accepted among the interrupts that interrupt request flag is "1".

Interrupt Mode Register ( IMOD)

if IM1,IM0 is selected as a "01", the interrupt selected by IP0~IP3 can be accepted and other

interrupts are not accepted. Using this register, we can change the interrupt priority order by s/w.

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

7

6

IMOD

IM1

IM0

IP3

IP2

IP1

IP0

<00F3_H>

Interrupt Definition Selection

0001 : INT0

0010 : INT1

0011 : INT2

0100 : INT3

0101 : TIMER0

0110 : TIMER1

0111 : TIMER2

1000 : TIMER3

1001 : ADC

Interrupt Mode Definition

00 : Mode 0 (Priority by H/W)

01 : Mode 1(Definition by IP3 IP0)

1- : Inhibit Interrupt

1010 : WDT

1011 : BIT

1100 : SIO

42

GMS81508/16

When multiple interrupt is accepted, it is possible to change Interrupt Accept Mode.

In case of multiple interrupt at hardware priority accept mode(Mode0)

Main Program

( Mode 0 )

1’st INT. Routine

( Mode 0 )

2’nd INT. Routine

( Mode 0 )

3’rd INT. Routine

EI

Interrupt

In case of multiple interrupts nest H/W priority accept mode (Mode0) and S/W selection accept

mode(Mode1)

Main Program

( Mode 0 )

1’st INT. Routine

( Mode 0 )

2’nd INT. Routine

( Mode 1 )

3’rd INT. Routine

EI

Stacking IMOD

Change Mode

EI

Interrupt

Reload IMOD

43

HYUNDAI MicroElectronics

2.13. STANDBY FUNCTION

To save the consuming power of device, GMS81508/16 has STOP Mode.

In this mode, the execution of program is stopped. Stop Mode entered by STOP instruction.

OSC.

Circuit

Clock Pulse GEN.

CPU Clock

MUX

halt

Prescaler

Basic Interval Timer

IFBIT

STOP

S

R

Q

S

R

Q

Overflow

Detection

RESET

Release Signal from Interrupt Circuit

At STOP Mode, Device Operation State.

Peripheral Function

Oscillator

STOP Mode

CPU Clock

RAM, Register

I/O Port

Retain

Prescaler

Basic Interval Timer

Serial I/O

Operation( External Clock Selection)

WDT, Timer, A/DC,PWM,

Buzzer Driver

Address Bus, Data Bus

Rd, Wt, R/W

HALT, BRQ, BAK

C

Retain

Active

"L" level

"H" level

SYNC

44

GMS81508/16

2.13.1. STOP Mode

STOP Mode can be entered by STOP instruction during program execution. In STOP mode,

oscillator is stopped to make all clocks stop, which leads to the mode requiring much less power

consumption. All register and RAM data are preserved.

Caution) NOP instruction have to be written more than 2 to next lines of STOP instruction.

2.13.2. STOP Mode Release

The release of STOP mode is done by reset input or interrupt. When there is a release signal of

STOP mode, the instruction execution is started after stabilization oscillation time set by program.

After releasing STOP mode, instruction execution is different by I-Flag(bit 2 of PSW).

“ ”

If I-Flag = 1 entered Interrupt Service Routine,

“ ”

If I-Flag = 0 execute program from next instruction of STOP instruction.

STOP Mode Release

Release

Factor

Release Method

RESET

By RESET pin=Low level, and Device is initialized.

In the state of enable flag=1 corresponding to each interrupt at

the edge.

INT0,INT1

INT2,INT3

Serial I/O

When Serial I/O is executed by external clock, STOP mode is

released.

STOP

System Clock

Release Signal

by interrupt

Stabilization oscillation time + 8 Cycles

RESET

STOP Mode

Stabilization Oscillation Time

determined by program.

Release Timing of STOP Mode

45

HYUNDAI MicroElectronics

When release the STOP Mode, to secure oscillation stabilization time, we use Basic Interval Timer.

So, before execution STOP instruction, we must select suitable B.I.T. clock for oscillation

stabilization time. Otherwise, It is possible to release by only RESET input.

Because STOP mode is released by interrupt, even if both of interrupt enable bit(IE) and interrupt

request flag is "1", STOP mode can not be executed.

STOP Command

STOP Mode

Interrupt Request

0

IE ?

1

STOP Mode Release

0

I-Flag ?

1

NOP

Interrupt Service Routine

STOP Mode Releasing Flow

46

GMS81508/16

2.14. RESET FUNCTION

To reset the device, maintain the RESET="L" at least 8 machine cycle after power supplying and

oscillation stabilization.

RESET terminal is organized as schmitt input.

If initial value is undefined, it is needed initialize by a S/W.

System Clock

RESET

Instruction Fetch

Address Bus

Data Bus

?

FFFE

FFFF Start

?

FE

ADL ADH

Opcode

Internal Read

RESET Process Step

Main Program

FFFE_H, is vector address and ADL, ADH is start address of main program

as vector contents

RESET Operation Timing

47

HYUNDAI MicroElectronics

3. I/O PORTS

There are 7-ports(R0~R6) in this device. This ports are double-functional ports and the function can

be selected by program.

The direction of ports is determined by Port Direction Register.(1=output, 0=input) The data that is

written on the programmed output pin is stored in the port data register and is transferred to the

output pin. When data is input to the programmed pin. data is read not from output pin but from port

data register. therefore, previously output data can be read correctly regardless or the logical level

of the pin due to output loading.

Because the programmed input pin is floating, the value of the pin can be read correctly. When

data is written to the programmed input pin, it is written only to the port data register and the pin

remains floating.

3.1. R0 PORT

R0 Port is composed of 8-bit programmable I/O pin.

Register Name

R0 I/O Direction Register

R0 PORT Data Register

Symbol

R0DD

R0

R/W

W

R/W

Address

00C1_H

00C0_H

Initial Value

0000 0000

Not initialized

R0 PORT I/O DIRECTION REGISTER

W

7

W

6

W

5

W

4

W

3

W

2

W

1

W

0

R0DD

R0DD7 R0DD6 R0DD5 R0DD4 R0DD3 R0DD2 R0DD1 R0DD0

<00C1_H>

Determines I/O of R0 port

0 : Input

1 : Output

R0 PORT DATA REGISTER

R/W

7

R/W

5

R/W

4

R/W

3

R/W

2

R/W

0

6

1

R0

R07

R06

R05

R04

R03

R02

R01

R00

<00C0_H>

Port R0 output data

48

GMS81508/16

Pin Function According to Operation Modes

Single Chip Mode

Microprocessor Mode

R00/D0

R01/D1

R02/D2

R03/D3

R04/D4

R05/D5

R06/D6

R07/D7

I/O

Programmable I/O Port

Data I/O Port from/to External Memory

for CPU.

3.2. R1 PORT

R1 Port is composed of 8-bit programmable I/O pin.

Register Name

R0 I/O Direction Register

R0 PORT Data Register

Symbol

R1DD

R1

R/W

W

R/W

Address

00C3_H

00C2_H

Initial Value

0000 0000

Not initialized

R1 PORT I/O DIRECTION REGISTER

W

7

W

6

W

5

W

4

W

3

W

2

W

1

W

0

R1DD

R1DD7 R1DD6 R1DD5 R1DD4 R1DD3 R1DD2 R1DD1 R1DD0

<00C3_H>

Determines I/O of R1 port

0 : Input

1 : Output

R1 PORT DATA REGISTER

R/W

7

R/W

5

R/W

4

R/W

3

R/W

2

R/W

0

6

1

R1

R17

R16

R15

R14

R13

R12

R1

R10

<00C2_H>

Port R1 output data

Pin Function According to Operation Modes

49

HYUNDAI MicroElectronics

Single Chip Mode

Microprocessor Mode

R10/A0

R11/A1

R12/A2

R13/A3

R14/A4

R15/A5

R16/A6

R17/A7

I/O

O

Programmable I/O Port

low 8bit address of External Memory

for CPU.

3.3. R2 PORT

R2 Port is composed of 8-bit programmable I/O pin.

Register Name

R2 I/O Direction Register

R2 PORT Data Register

Symbol

R2DD

R2

R/W

W

R/W

Address

00C5_H

00C4_H

Initial Value

0000 0000

Not initialized

R2 PORT I/O DIRECTION REGISTER

W

7

W

6

W

5

W

4

W

3

W

2

W

1

W

0

R2DD

R2DD7 R2DD6 R2DD5 R2DD4 R2DD3 R2DD2 R2DD1 R2DD0

<00C5_H>

Determines I/O of R2 port

0 : Input

1 : Output

R2 PORT DATA REGISTER

R/W

7

R/W

5

R/W

4

R/W

3

R/W

2

R/W

0

6

1

R2

R27

R26

R25

R24

R23

R22

R21

R20

<00C4_H>

Port R2 output data

50

GMS81508/16

Pin Function According to Operation Modes

Single Chip Mode

Microprocessor Mode

R20/A8

I/O

O

R21/A9

R22/A10

R23/A11

R24/A12

R25/A13

R26/A14

R27/A15

Programmable I/O Port

upper 8bit address of External Memory

for CPU.

3.4. R3 PORT

R3 Port is composed of 8-bit programmable I/O pin.

Register Name

R3 I/O Direction Register

R3 PORT Data Register

Symbol

R3DD

R3

R/W

W

R/W

Address

00C7_H

00C6_H

Initial Value

0000 0000

Not initialized

R3 PORT I/O DIRECTION REGISTER

W

7

W

6

W

5

W

4

W

3

W

2

W

1

W

0

R3DD

R3DD7 R3DD6 R3DD5 R3DD4 R3DD3 R3DD2 R3DD1 R3DD0

<00C7_H>

Determines I/O of R3 port

0 : Input

1 : Output

R3 PORT DATA REGISTER

R/W

7

R/W

5

R/W

4

R/W

3

R/W

2

R/W

0

6

1

R3

R37

R36

R35

R34

R33

R32

R31

R30

<00C6_H>

Port R3 output data

51

HYUNDAI MicroElectronics

Pin Function According to Operation Modes

R30

R31

R32

R33

R34

R35

Single Chip Mode

Microprocessor Mode

I/O

O

Rd : external memory read strobe

Wt : external memory write strobe

R/W :Read/Write cycle output pin of CPU

C : timing signal output pin

Programmable I/O Port

SYNC : op code fetch output pin of CPU

BRK : bus acknowledge output pin of

CPU

R36

R37

I/O

I

BRQ : bus request input pin of CUP

HALT : CPU halt input pin

3.5. R4 PORT

R4 Port is composed of 8bit programmable I/O port and this port are double functional pin.

Register Name

R4 I/O Direction Register

R4 Port Data Register

Port R4 Mode Register

Interrupt Edge Select Register

Symbol

R4DD

R4

PMR4

IEDS

R/W

W

R/W

W

Address

00C9_H

00C8_H

00D0_H

00F8_H

Initial Value

0000 0000

Not initialized

0000 0000

R/W

R4 PORT I/O DIRECTION REGISTER

W

7

W

6

W

5

W

4

W

3

W

2

W

1

W

0

R4DD

R4DD7 R4DD6 R4DD5 R4DD4 R4DD3 R4DD2 R4DD1 R4DD0

<00C9_H>

Determines I/O of R4 port

0 : Input

1 : Output

R4 PORT DATA REGISTER

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

7

0

R4

R47

R46

R45

R44

R43

R42

R41

R40

<00C8_H>

Port R4 output data

52

GMS81508/16

PORT R4 MODE REGISTER

W

5

W

6

W

4

W

3

W

2

W

1

W

0

7

PMR4

T3S

EC2S

INT3S INT2S

EC0S INT1S INT0S

T1S

<00D0_H>

R40 / INT0 Selection

0 : R40 ( Input / Output )

1 : INT0 ( Input )

R47 / T3 Selection

0 : R47 ( Input / Output )

1 : T3 ( Output )

R41 / INT1 Selection

0 : R41 ( Input / Output )

1 : INT1 ( Input )

R46 / T1 Selection

0 : R46 ( Input / Output )

1 : T1 ( Output )

R42 / INT2 Selection

0 : R42 ( Input / Output )

1 : INT2 ( Input )

R45/ EC2 Selection

0 : R45 ( Input / Output )

1 : EC2 ( Input )

R43 / INT3 Selection

R44/ EC0 Selection

0 : R43 ( Input / Output )

1 : INT3 ( Input )

0 : R44 ( Input / Output )

1 : EC0 ( Input )

INTERRUPT EDGE SELECTION REGISTER

W

7

W

6

W

4

W

3

W

5

W

0

W

2

W

1

IEDS

IED3H IED3L IED2H IED2L

IED1H IED1L IED0H IED0L

<00F8_H>

INT3 Edge Selection

01 : Falling

10 : Rising

INT0 Edge Selection

01 : Falling

10 : Rising

11 : Falling & Rising

INT2 Edge Selection

01 : Falling

INT1 Edge Selection

01 : Falling

10 : Rising

11 : Falling & Rising

3.6. R5 PORT

R5 Port is composed of 8-bit programmable I/O port. R54,R55 is double functional pin.

Register Name

R5 I/O Direction Register

R5 Port Data Register

R5 Port Mode Register

Symbol

R5DD

R5

R/W

W

Address

00CB_H

00CA_H

00D1_H

Initial Value

0000 0000

R/W

W

Not initialized

--00 ----

PMR5

53

HYUNDAI MicroElectronics

R5 PORT I/O DIRECTION REGISTER

W

4

W

3

W

2

W

1

W

0

W

7

W

6

W

5

R5DD

R5DD4 R5DD3 R5DD2 R5DD1 R5DD0

R5DD7 R5DD6 R5DD5

<00CB_H>

Determines I/O of R5 port

0 : Input

1 : Output

R5 PORT DATA REGISTER

R/W

4

R/W

3

R/W

2

R/W

0

R/W

7

R/W

5

6

1

R5

R54

R53

R52

R51

R50

R57

R56

R55

<00CA_H>

Port R5 Output Data

PORT R5 MODE REGISTER

W

4

7

6

-

5

3

-

2

-

1

0

PMR5

WDTON

-

BUZ

-

<00D1_H>

R54 / WDTON Selection

0 : R54 ( Input / Output )

1 : WDTON ( Output )

R55 / BUZ Selection

0 : R55 ( Input / Output )

1 : BUZ ( Output )

3.7. R6 PORT

R6 Port consists of 4-bit Programmable I/O ports and 4-bit input only ports and this port can be

used as a analog input port for A/D conversion by program.

Register Name

R6 I/O Direction Register

R6 Port Data Register

Symbol

R6DD

R6

R/W

W

Address

00CD_H

00CC_H

00E8_H

Initial Value

0000 ----

R/W

W

Not initialized

A/D Converter Mode Register

ADCM

--00 000

1

54

GMS81508/16

R6 PORT I/O DIRECTION REGISTER

W

7

W

6

W

5

W

4

3

2

1

0

R6DD

R6DD3 R6DD2 R6DD1 R6DD0

R6DD7 R6DD6 R6DD5 R6DD4

<00CD_H>

Determines I/O of R6 port

0 : Input

1 : Output

R6 PORT DATA REGISTER

R/W

6

R/W

5

R/W

4

R

3

R

2

R

1

R

0

7

R6

R43

R42

R41

R40

R47

R46

R45

R44

<00CC_H>

Port R6 output data

On the initial RESET, R60 can’t be used digital input port, because this port is

selected as an analog input port by ADCM register. To use this port as a digital I/O

port, change the value of lower 4 bits of ADCM(address 0E8H). On the other

hand,R6 port, all eight pins can not be used as digital I/O port simultaneously. At

least one pin is used as an analog input.

UNUSED PORTS

All unused ports should be set properly that current flow through port doesn't exist.

First consider the setting the port as an input mode. Be sure that there is no

current flow after considering its relationship with external circuit. In input mode,

the pin impedance viewing from external MCU is very high that the current doesn’t

flow.

But input voltage level should be V_SSor V_DD. Be careful that if unspecified voltage,

i.e. if unfirmed level voltage is applied to input pin, there can be little current ( max.

1mA at 2V) flow.

If it is not appropriate to set as an input mode, then set to output mode considering

there is no current flow. Setting to High or Low is decided considering its

relationship with external circuit. For example, if there is external pull-up resistor

then it is set to output mode, i.e. to High, and if there is external pull-down register,

it is set to low.

55

HYUNDAI MicroElectronics

3.8. TERMINAL TYPES

TERMINAL TYPE

Vdd

Xin

Xout

Vss

Xout

STOP

RESET

MP

1

Data Bus

Vdd

MUX

0

Data REG.

Data Bus

R00 ~ R07

Direction REG.

Data Bus

Vss

MUX

Rd

Data Bus

Rd

56

GMS81508/16

MP

Vdd

Address Bus

Data Bus

MUX

Data REG.

R10 ~ R27

R20 ~ R27

Direction REG.

Data Bus

Vss

MUX

Data Bus

Rd

From R30 ... Rd

From R31 ... Wt

From R32 ... R/W

From R33 ... C

MP

From R34 ... SYNC

From R35 ... BAK

Vdd

MUX

R30

R31

R32

R33

R34

R35

Data REG.

Data Bus

Direction REG.

Vss

MUX

Data Bus

Rd

MP

Vdd

Data REG.

Data Bus

R36

R37

Direction REG.

Vss

MUX

Data Bus

Rd

to BRQ

to HALT

57

HYUNDAI MicroElectronics

Selection

Vdd

Data REG.

Data Bus

R40/INT0

R41/INT1

R42/INT2

R43/INT3

R44/EC0

R45/EC2

R50/Sin

Direction REG.

Data Bus

Vss

MUX

To R40

To R41

To R42

To R43

To R44

To R45

To R50

INT0

INT1

INT2

INT3

EC0

EC2

Sin

Rd

From R46 ... T1O

From R47 ... T3O

From R51 ... Sout

From R54 ... WDTO

From R55 ... BUZ

From R56 ... PWM0

From R57 ... PWM1

Selection

R46/T1O

R47/T3O

R51/Sout

R54/WDTO

R55/BUZ

Vdd

MUX

Data REG.

Data Bus

Direction REG.

R56/PWM0

R57/PWM1

Vss

MUX

Data Bus

Rd

Selection

Vdd

sck o

MUX

Data REG.

Data Bus

R52/Sclk

Direction REG.

Data Bus

exck

MUX

Vss

MUX

Data Bus

Rd

sck i

58

GMS81508/16

Selection

Srdy

Vdd

Srdy o

MUX

Data REG.

Data Bus

R53/Srdy

Direction REG.

Data Bus

Vss

MUX

Rd

Srdy in

R60/AN0

R61/AN1

R62/AN2

R63/AN3

Data Bus

Rd

To A/D Converter

Vdd

Data REG.

Data Bus

R64/AN4

R65/AN5

R66/AN6

R67/AN7

Direction REG.

Data Bus

Vss

MUX

Rd

To A/D Converter

59

HYUNDAI MicroElectronics

4. ELECTRICAL CHARACTERISTICS

4.1. ABOULUTE MAXIMUM RATINGS

Parameter

Supply Voltage

Symbol

Vdd

Unit

V

Ratings

-0.3 ~ 7.0

Input Voltage

Vi

V

-0.3 ~ Vdd+0.3

-40 ~ 125

Storage Temperature

Tstg

C

°

4.2. RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Unit

Specifications

Typ.

Min.

4.5

Max.

5.5

Supply Voltage

Vdd

fXin

V

Operating Frequency

MHz

1

8

Operating Temperature

Topr

-20

85

C

°

4.3. A/D CONVERTER CHARACTERISTICS

( Vdd = 5V

Unit

10%, Vss = 0

,

,f (Xin) = 8

)

SPECIFICATION

Typ. Max.

Parameter

Symbol

V_AIN

ETC

Min.

Analog Input Range

AN0~AN7

V

Vss

Vref

3

Accuracy

LSB

Conversion Time

Tconv

Vref

20

Analog Power Suppiy Input Range

AVref

V

Vdd

60

GMS81508/16

4.4. DC CHARACTERISTICS

( Vdd =5.0V 10%,Vss = 0 , Ta = -20 85

±

,f (Xin) = 8

)

Parameter

"H" Input voltage

"L" Input voltage

Symbol

Test Condition Unit

Specifications

Min.

Typ.

Max.

RESET,,R4,R5,R6

R0,R1,R2,R3

Xin

0.8Vdd

Vdd

Vih

V

0.7Vdd

0.9Vdd

RESET,R4,R5,R6

R0,R1,R2,R3

Xin

0

0.12Vdd

0.3Vdd

0.1Vdd

5

Vil

0

"H" Input Leakage

Current

Iih

Iil

all input pins

Vi = Vdd

Vi = Vss

-5

"L" Input Leakage

Current

all input pins

-5

5

"H" output Voltage

"L" output Voltage

Voh

R0,R1,R2,R3,R4,R5

Ioh = -2mA

Iol = 5mA

V

Vdd-1

1.0

40

Power

Operating

STOP

Idd

Istop

all input = Vss

20

Current

Hysteresis

100

V_T+ ~ V_T-

RESET,

EC2,EC0,Sin,Sclk,INT0~3

Vdd

V

0.3

2.0

0.8

RAM Data Retention

Vram

at clock stop

61

HYUNDAI MicroElectronics

4.5. AC CHARACTERISTICS

4.5.1. Input Conditions

( Vdd = 5.0V 10%, Vss = 0 , Ta = -20

85

±

,f (Xin) = 8

ETC

)

Parameter

Symbol

Unit

SPECIFICATION

MIN.

1

TYP.

MAX.

Operating Frequency

Xin

fcp

tsys

MHz

ns

-

8

System Clock

500

250

20

Oscillation Stabilization Time

External Clock Pulse Width

External Clock Transition Time

Interrupt Pulse Width

Xin, Xout

Xin

t_ST

ms

ns

tcpw

trcp,tfcp

t_IW

100

Xin

ns

20

INT0~INT3

RESET

EC0,EC2

tsys

ns

2

8

2

RESET Input "L" Width

t_RST

Event Counter Input Pulse Width

Event Counter Transition Time

t_ECW

tr_EC,tf_EC

20

Timing Chart

cpw

t

cp

t

1/f

Vdd-0.5V

0.5 V

Xin

rcp

fcp

t

IW

t

INT3

INT2

INT1

INT0

0.8 Vdd

0.2 Vdd

RST

t

RESET

0.2 Vdd

ECW

t

0.8 Vdd

0.2 Vdd

EC0

EC2

rEC

fEC

t

62

GMS81508/16

4.5.2. Serial Transfer

( Vdd = 5.0V 10%, Vss = 0 , Ta = -20

85

±

,f (Xin) = 8

etc

)

Parametet

Symbol

Unit

SPECIFICATION

MIN.

TYP.

MAX.

Serial Input Clock Pulse

Sclk

tscyc

tsckw

ns

2tsys+200

tsys+70

-

8

Serial Input Clock Pulse Width

Serial Input Clock Pulse Transition

Time

tfsck,trsck

30

Sin Input Pulse Transition Time

Sin Input Setup time(Exnternal Sclk)

Sin Input Setup time(Internal Sclk)

Sin Input Hold Time

Sin

tfsin,trsin

tsus

ns

-

30

Sin

100

200

Sin

tsus

Sin

ths

tsys+70

4tsys

Serial Output Clock Cycle Time

Serial Output Clock Transition Time

Serial Output Delay Time

Sclk

Sout

tscyc

16tsys

tsckw

2tsys-30

tfsck,trsck

tr_EC,tf_EC

30

100

Serial I/O Timing Chart

scyc

t

rsck

t

fsck

t

sckW

t

0.8 Vdd

Sclk

Sin

0.2 Vdd

sus

hs

t

0.2 Vdd

0.8 Vdd

fsin

rsin

t

ds

t

0.2 Vdd

0.8 Vdd

Sout

63

HYUNDAI MicroElectronics

4.5.3. Microprocessor Mode I/O Timing

( Vdd = 5.0V 10%, Vss = 0 , Ta = -20

85

±

,f (Xin) = 8

etc

)

Parameter

Symbol

Unit

SPECIFICATION

MIN.

TYP.

MAX.

Control Clock Output Width

Address Output Delay Time

Data Output Delay Time

Data Output Hold Time

Data Input Setup Time

Data Input Hold Time

C

tCL

tdCA

tdCD

thw

ns

90

-

A0 ~ A15

D0 ~ D7

Rd

80

180

20

ns

tsuR

thR

ns

80

15

ns

Rd Output Delay Time

Wt Output Delay Time

R/W Output Delay Time

sync Output Delay Time

tdRd

tdWt

tdRW

tdsync

tsys

90

130

50

Wt

R/W

SYNC

50

Timing Chart

tsys

tcw

0.8Vdd

0.2Vdd

0.8Vdd

0.2Vdd

C

tdCA

0.8Vdd

0.2Vdd

A0~A15

tdCD

thW

write mode

D0~D7

tstR

thR

read mode

D0~D7

tdRd

Rd

0.2Vdd

tdWt

Wt

0.2Vdd

tdRW

0.8Vdd

R/W

0.2Vdd

tdsync

0.8Vdd

SYNC

0.2Vdd

64

GMS81508/16

4.5.4. Bus Holding Timing

( Vdd = 5.0V 10%, Vss = 0 , Ta = -20

85

±

,f (Xin) = 8

etc

)

Parameter

Symbol

Unit

SPECIFICATION

MIN.

TYP.

MAX.

BRQ Setup Time

BRQ

BAK

tSUB

tdBA

tsys

100

-

BAK Delay Time

50

BAK Release Delay Time

tdRBA

220

Bus(Address,Data) Control Release

Delay Time

D0 ~ D7

A0 ~ A15

Rd,Wt,R/W

tdRA

tsys

-

210

Timing Chart

Instruction Ececution

Holding Cycle

Instruction Ececution

C

0.2Vdd

SYNC

BRQ

tsuB

0.2Vdd

tdRBA

tdBA

0.8Vdd

BAQ

D0~D7

A0~A15

Rd

tdRA

Hi-Z

0.8Vdd

0.2Vdd

Wt

R/W

65

HYUNDAI MicroElectronics

5. INSTRUCTION SET

1. ARITHMETIC/ LOGIC OPERATION

FLAG

NVGBHIZC

OP BYTE CYCLE

NO.

MNEMONIC

ADC #imm

OPERATION

CODE NO

NO

1

2

04

05

2

3

Add with carry.

( A )

ADC dp

A

( M )

C

3

4

ADC dp + X

ADC !abs

06

07

15

16

17

14

84

85

2

3

2

1

2

4

5

6

3

2

3

NV--H-ZC

5

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

6

7

8

9

AND #imm

AND dp

Logical AND

( A )

10

A

( M )

11

12

13

14

15

16

17

18

19

20

21

22

AND dp + X

AND !abs

86

87

95

96

97

94

08

09

19

18

44

45

2

3

2

1

2

3

2

4

5

6

3

2

4

5

2

3

N-----Z-

N-----ZC

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL

A

Arithmetic shift left

ASL dp

C

7

6

5

4

3

2

1

0

”0”

ASL dp + X

ASL !abs

CMP #imm

CMP dp

Compare accumulator contents with memory contents

( A ) ( M )

23

24

25

26

27

28

29

30

CMP dp + X

CMP !abs

46

47

55

56

57

54

5E

6C

2

3

2

1

2

4

5

6

3

2

3

N-----ZC

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

CMPX dp

Compare X contents with memory contents

( X ) ( M )

31

32

33

CMPX !abs

CMPY #imm

CMPY dp

7C

7E

8C

3

2

4

2

3

Compare Y contents with memory contents

( Y ) ( M )

N-----ZC

N-----Z-

34

35

CMPY !abs

COM dp

9C

2C

3

2

4

1’S Complement

:

( dp )

36

37

DAA

DAS

DF

CF

1

3

Decimal adjust for addition

N-----ZC

Decimal adjust for substraction

66

GMS81508/16

FLAG

NVGBHIZC

OP BYTE CYCLE

NO.

MNEMONIC

OPERATION

CODE NO

NO

N-----Z-

38

39

DEC

A

A8

A9

1

2

4

Deccrement

DEC dp

M

( M )

1

N-----Z-

NV--H-Z-

40

41

42

43

44

45

46

DEC dp + X

DEC !abs

B9

B8

AF

BE

9B

A4

A5

2

3

1

2

5

DEC

DIV

X

Y

2

12

2

Divide

:

YA / X Q: A, R: Y

EOR #imm

EOR dp

Exclusive OR

3

A

( A ) ( M )

47

48

49

50

51

52

53

54

EOR dp + X

EOR !abs

A6

A7

B5

B6

B7

B4

88

89

2

3

2

1

2

4

5

6

3

2

4

N-----Z-

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC

A

Increment

N-----ZC

N-----Z-

INC dp

M

( M )

1

55

56

57

58

59

60

61

62

63

INC dp + X

INC !abs

99

98

8F

9E

48

49

59

58

5B

2

3

1

2

3

1

5

2

4

5

9

N-----Z-

INC

LSR

X

Y

A

Logical shift right

LSR dp

LSR dp + X

LSR !abs

MUL

7

6

5

4

3

2

1

0

C

N-----ZC

N-----Z-

”0”

Multiply

:

YA

Y

A

64

65

OR #imm

OR dp

64

65

2

3

Logical OR

( A )

A

( M )

66

67

68

69

70

71

72

73

74

75

76

77

78

79

OR dp + X

OR !abs

66

67

75

76

77

74

28

29

39

38

68

69

79

78

2

3

2

1

2

3

1

2

3

4

5

6

3

2

4

5

2

4

5

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL

A

Rotate left through carry

N-----ZC

ROL dp

C

7

6

5

4

3

2

1

0

ROL dp + X

ROL !abs

ROR

A

Rotate right through carry

ROR dp

7

6

5

4

3

2

1

0

C

ROR dp + X

ROR !abs

67

FLAG

NVGBHIZC

OP BYTE CYCLE

NO.

MNEMONIC

SBC #imm

OPERATION

CODE NO

NO

80

81

24

25

2

3

Substract with carry

( A ) ( M )

SBC dp

A

( C )

82

83

84

85

86

87

88

SBC dp + X

SBC !abs

26

27

35

36

37

34

4C

2

3

2

1

2

4

5

6

3

NV--HZC

SBC !abs + Y

SBC [ dp + X ]

SBC [ dp ] + Y

SBC { X }

Test memory contents for negative or zero

( dp ) 00_H

Exchange nibbles within the accumulator

N-----Z-

TST dp

89

XCN

CE

1

5

A₇A₄

A₃A0

2. REGISTER / MEMORY OPERATION

FLAG

NVGBHIZC

OP

BYTE CYCLE

NO.

MNEMONIC

LDA #imm

OPERATION

CODE NO

NO

1

2

C4

C5

2

3

Load accumulator

LDA dp

A

( M )

3

4

5

6

7

8

9

LDA dp + X

LDA !abs

C6

C7

D5

D6

D7

D4

DB

2

3

2

1

4

5

6

3

4

N-----Z-

LDA !abs + Y

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

X- register auto-increment : A

( M ) ,

X

1

--------

N-----Z-

10

LDM dp,#imm

E4

3

5

Load memory with immediate data : ( M )

Load X-register

imm

11

12

LDX #imm

LDX dp

1E

2

3

CC

X

( M )

13

14

15

16

LDX dp + Y

LDX !abs

LDY #imm

LDY dp

CD

DC

3E

2

3

2

4

2

3

Load Y-register

( M )

N-----Z-

C9

Y

17

18

19

20

LDY dp + X

LDY !abs

STA dp

D9

D8

E5

E6

2

3

2

4

3

4

Store accumulator contents in memoy

( M )

STA dp + X

A

21

22

23

24

25

26

STA !abs

E7

F5

F6

F7

F4

FB

3

2

1

4

5

6

3

4

STA !abs + Y

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

--------

STA { X }+

X- register auto-increment : ( M )

A,

X

1

OP BYTE CYCLE

FLAG

68

GMS81508/16

NVGBHIZC

NO.

MNEMONIC

STX dp

OPERATION

CODE NO

NO

4

27

28

EC

ED

2

Store X-register contents in memoy

STX dp + Y

5

--------

( M )

X

29

30

31

STX !abs

STY dp

FC

E9

F9

3

2

5

4

5

Store Y-register contents in memoy

( M )

STY dp + X

Y

32

33

STY !abs

TAX

F8

E8

3

1

5

2

N-----Z-

Transfer accumulator contents to X-register :

A

X

34

35

TAY

9F

1

2

N-----Z-

Transfer accumulator contents to Y-register : Y

A

TSPX

AE

Transfer stack-pointer contents to X-register : X

sp

N-----Z-

--------

36

37

38

39

TXA

TXSP

TYA

XAX

C8

8E

BF

EE

1

2

4

Transfer X-register contents to accumulator: A

Transfer X-register contents to stack-pointer: sp

Transfer Y-register contents to accumulator: A

X

Y

Exchange X-register contents with accumulator :X

A

--------

40

XAY

DE

1

4

Exchange Y-register contents with accumulator :Y

A

41

42

XMA dp

BC

AD

2

5

6

Exchange memory contents with accumulator

XMA dp+X

N-----Z-

--------

( M )

A

43

44

XMA {X}

XYX

BB

FE

1

5

4

Exchange X-register contents with Y-register :

Y

X

3. 16-BIT OPERATION

OP BYTE CYCLE

FLAG

MNEMONIC

ADDW dp

OPERATION

NVGBHIZC

NO.

1

CODE NO

NO

16-Bits add without carry

NV--H-ZC

N-----ZC

N-----Z-

--------

NV--H-ZC

1D

5D

BD

9D

7D

DD

3D

2

5

YA

( YA )

( dp +1 ) ( dp )

2

3

4

5

6

7

CMPW dp

DECW dp

INCW dp

LDYA dp

STYA dp

SUBW dp

4

6

5

Compare YA contents with memory pair contents :

(YA) (dp+1)(dp)

Decrement memory pair

( dp+1)( dp)

( dp+1) ( dp)

1

Increment memory pair

( dp+1) ( dp)

Load YA

( dp+1) ( dp )

1

YA

( dp +1 ) ( dp )

Store YA

( dp +1 ) ( dp )

YA

16-Bits substact without carry

YA ( YA ) ( dp +1) ( dp)

69

HYUNDAI MicroElectronics

4. BIT MANIPULATION

OP BYTE CYCLE

FLAG

NVGBHIZC

MNEMONIC

OPERATION

NO.

CODE NO

NO

-------C

MM----Z-

1

2

AND1 M.bit

8B

3

4

Bit AND C-flag

: C ( C )

( M .bit )

( C )

AND1B M.bit

4

Bit AND C-flag and NOT : C

Bit test A with memory :

( M .bit )

3

4

BIT dp

0C

1C

2

3

4

5

BIT !abs

Z

( A )

( M ) ,

( M.bit )

( A.bit )

N

( M₇) ,

V

( M₆)

--------

-------0

--0-----

-0--0---

-------C

5

6

CLR1 dp.bit

CLRA1 A.bit

CLRC

y1

2B

20

40

80

AB

2

1

3

4

2

5

Clear bit

:

“0”

Clear A bit

:

7

Clear C-flag

Clear G-flag

Clear V-flag

:

C

G

V

“0”

8

CLRG

9

CLRV

10

11

EOR1 M.bit

EOR1B M.bit

Bit exclusive-OR C-flag

: C

( C )

( M .bit )

Bit exclusive-OR C-flag and NOT : C ( C )

(M .bit)

-------C

--------

-------C

--------

-------1

--1-----

--------

N-----Z-

12

13

14

15

16

17

18

19

20

21

22

LDC M.bit

LDCB M.bit

NOT1 M.bit

OR1 M.bit

OR1B M.bit

SET1 dp.bit

SETA1 A.bit

SETC

CB

4B

6B

x1

3

2

1

3

4

5

4

2

6

Load C-flag

: C

( M .bit )

Load C-flag with NOT : C

( M .bit )

Bit complement

Bit OR C-flag

:

( M .bit )

( C )

: C

( M .bit )

( C )

Bit OR C-flag and NOT : C

( M .bit )

Set bit

:

( M.bit )

: ( A.bit )

“1”

0B

A0

C0

EB

5C

Set A bit

Set C-flag

Set G-flag

:

C

G

:

“1”

( M .bit )

SETG

STC M.bit

TCLR1 !abs

Store C-flag

C

Test and clear bits with A

:

A

( M ) ,

Test and set bits with

( M ) , ( M )

( M )

( A )

N-----Z-

23

TSET1 !abs

3C

3

6

A

:

A

( M )

( A )

5. BRANCH / JUMP OPERATION

OP BYTE CYCLE

FLAG

NVGBHIZC

MNEMONIC

OPERATION

NO.

CODE NO

NO

4/6

5/7

--------

1

2

BBC A.bit,rel

BBC dp.bit,rel

y2

y3

2

3

Branch if bit clear :

if ( bit )

0 , then pc

( pc )

rel

3

4

BBS A.bit,rel

BBS dp.bit,rel

x2

x3

2

3

4/6

5/7

Branch if bit set :

if ( bit )

1 , then pc

--------

5

6

7

BCC rel

BCS rel

BEQ rel

50

D0

2

2/4

Branch if carry bit clear

if ( C ) 0 , then pc ( pc ) rel

Branch if carry bit set

if ( C ) 1 , then pc ( pc ) rel

Branch if equal

if ( Z )

1 , then pc

( pc )

rel

70

GMS81508/16

OP BYTE CYCLE

FLAG

NVGBHIZC

MNEMONIC

BMI rel

OPERATION

NO.

8

CODE NO

NO

--------

90

70

10

2F

30

B0

2

2/4

Branch if minus

if ( N )

1 , then pc

( pc )

rel

Branch if not equal

9

BNE rel

BPL rel

BRA rel

BVC rel

BVS rel

2/4

4

if ( Z )

0 , then

10

11

12

13

Branch if minus

if ( N )

0 , then pc

Branch always

pc

( pc )

rel

Branch if overflow bit clear

if (V) 0 , then pc ( pc) rel

2/4

Branch if overflow bit set

if (V) 1 , then pc ( pc ) rel

14

15

CALL !abs

CALL [dp]

3B

5F

3

2

8

Subroutine call

--------

sp

M( sp)

- 1,

( pc_H), sp sp - 1, M( sp)

( pc_L), sp

if !abs, pc abs ; if [dp], pc_L( dp ), pc_H

( dp+1 ) .

--------

16

17

CBNE dp,rel

FD

8D

3

5/7

6/8

Compare and branch if not equal :

CBNE dp+X,rel

if ( A )

Decrement and branch if not equal :

if ( M ) 0 , then pc ( pc )

Unconditional jump

( M ) , then pc

( pc )

rel.

18

19

DBNE dp,rel

DBNE Y,rel

AC

7B

3

2

5/7

4/6

rel.

20

21

22

23

JMP !abs

1B

1F

3F

4F

3

2

3

5

4

6

--------

JMP [!abs]

JMP [dp]

pc

jump address

PCALL upage

U-page call

M( sp) ( pc_H), sp sp - 1, M( sp)

( pc_L),

sp sp - 1, pc_L( upage ), pc_H”0FF_H” .

--------

24

TCALL

n

nA

1

8

Table call : (sp) ( pc_H), sp sp - 1,

M( sp) ( pc_L),sp sp - 1,

pc_L(Table vector L), pc_H(Table vector H)

71

HYUNDAI MicroElectronics

6. CONTROL OPERATION & etc.

OP BYTE CYCLE

FLAG

NVGBHIZC

MNEMONIC

OPERATION

NO.

CODE NO

NO

---1-0--

1

BRK

0F

1

8

Software interrupt :

sp - 1, M( s ) ( pc_L), sp sp - 1, M( sp) ( PSW ),

sp sp -1, pc_L( 0FFDE_H) , pc_H( 0FFDF_H) .

B

”1”, M( sp) ( pc_H), sp

-----0--

-----1--

--------

2

3

DI

EI

60

1

3

Disable interrups

Enable interrups

No operation

:

I

“0”

“1”

E0

:

I

4

5

NOP

POP

FF

0D

1

2

4

A

X

Y

sp

1,

A

X

Y

M( sp )

--------

( restored )

--------

6

7

POP

2D

4D

6D

0E

2E

4E

6E

6F

1

4

5

8

POP PSW

1, PSW

M( sp )

9

PUSH

A

X

Y

M( sp )

A ,

sp

1

10

11

12

13

X ,

Y ,

PUSH PSW

RET

PSW , sp

sp

1

--------

( restored )

--------

Return from subroutine

sp sp +1, pc_L

pc_HM( sp )

M( sp ), sp

sp +1,

14

15

RETI

7F

00

1

6

3

Return from interrupt

sp

pc_L

sp +1, PSW M( sp ), sp sp +1,

M( sp ), sp sp +1, pc_HM( sp )

STOP

Stop mode ( halt CPU, stop oscillator )

72

GMS81508/16

HYUNDAI MicroElectronics

With these socket adapters, the GMS81516AT can

easy be programming and verifying using Intel

27C256 EPROM mode on general-purpose PROM

programmer.

6. GMS81516AT (OTP) PROGRAMMING

The GMS81516AT is one-time PROM (OTP) micro-

controller with 16K bytes electrically programmable

read only memory for the GMS81508/16 system

evaluation, first production and fast mass production.

In assembler and file type, two files are generated after

compiling. One is "*.HEX", another is "*.OTP". The

"*.HEX" file is used for emulation in circuit emulator

(CHOICE-Dr^TMor CHOICE-Jr^TM) and "*.OTP" file

is used for programming to the OTP device.

To programming the OTP device, user can have two

way. One is using the universal programmer which is

support HME microcontrollers, other is using the gen-

eral EPROM programmer.

Programming Procedure

1. Using the Universal programmer

1. Select the EPROM device and manufacturer on

EPROM programmer (Intel 27C256).

Third party universal programmer support to program

the GMS81516AT microcontrollers and lists are

shown as below.

2. Select the programming algorithm as an Intelligent

mode (apply 1ms writing pulse), not a Quick pulse

mode.

Manufacturer: Advantech

Web site: http://www.aec.com.tw

Programmer: LabTool-48

3. Load the file (*.OTP) to the programmer.

Manufacturer: Hi-Lo systems

Web site: http://www.hilosystems.com.tw

Programmer: ALL-11, GANG-08

4. Set the programming address range as below table.

Socket adapters are supported by third party program-

mer manufacturer.

Address

Buffer start address

Buffer end address

Device start address

Set Value

4000_H

2. Using the general EPROM(27C256)

programmer

7FFF_H

4000_H

The programming algorithm is simmilar with the stan-

dart EPROM 27C256. It gives some convience that user

can use standard EPROM programmer. Make sure

that 1ms programming pulse must be used, it gener-

ally called "Intelligent Mode". Do not use 100us

programming pulse mode, "Quick Pulse Mode".

5. Mount the socket adapter with the GMS81516AT on

the PROM programmer.

6. Start the PROM programmer to programming/

verifying.

When user use general EPROM programmer, socket

adaper is essencially required. It convert pin to fit the

pin of general 27C256 EPROM.

Three type socket adapters are provided according to

package variation as below table.

Socket Adapter

OA815A-64SD

Package Type

64 pin SDIP

OA815A-64QF-10

OA815A-64QF

64 pin LQFP (10 x 10)

64 pin QFP (14 x 20)

GMS81516AT PROGRAMMING

MANUAL

HYUNDAI MicroElectronics

GMS81516AT EPROM PROGRAMMING

DEVICE OVERVIEW

The GMS81516AT is a high-performance CMOS 8-bit microcontroller with 16K bytes of EPROM. The device

is one of GMS800 family. The HME GMS81516AT is a powerful microcontroller which provides a highly

flexible and cost effective solution to many embedded control applications. The GMS81516AT provides the

following standard features: 16K bytes of EPROM, 448 bytes of RAM, 56 I/O lines, 16-bit or 8-bit timer/counter,

a precision analog to digital converter, PWM, on-chip oscillator and clock circuitry.

PIN CONFIGURATION

64SDIP

GMS81516AT

2

GMS81516AT EPROM PROGRAMMING

HYUNDAI MicroElectronics

64QFP

64LQFP

3

HYUNDAI MicroElectronics

GMS81516AT EPROM PROGRAMMING

64SDIP Package for GMS81516AT

Pin No.

1

MCU Mode

OTP Mode

Pin No.

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

MCU Mode

I/O

OTP Mode

A15

A14

A13

A12

A11

A10

A9

V

-

V

-

I

R27

R26

R25

R24

R23

R22

R21

R20

R17

R16

R15

R14

R13

R12

R11

R10

R07

R06

R05

R04

R03

R02

R01

R00

R37

R36

R35

R34

R33

R32

R31

R30

I

DD

PP

2

MP

I

V

I/O

I

3

AVSS

I

(1)

I

4

AVREF

I

(1)

(2)

CE

OE

(1)

(3)

I

5

R67/AN7

R66/AN6

R65/AN5

R64/AN4

R63/AN3

R62/AN2

R61/AN1

R60/AN0

R57/PWM1

R56/PWM0

R55/BUZ

R54/WDTO

R53/SRDY

R52/SCLK

R51/SOUT

R50/SIN

R47/T3O

R46/T1O

R45/EC2

R44/EC0

R43/INT3

R42/INT2

R41/INT1

R40/INT0

RESET

I/O

I

6

I

7

I

8

I

A8

I

9

I

A7

I

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

I

A6

I

A5

I

A4

I

I/O

I

A3

I

A2

I

A1

I

A0

I

O7

I/O

I

O6

I/O

I

O5

I/O

I

O4

I/O

I

O3

I/O

I

O2

I/O

I

O1

I/O

I

O0

I/O

I

(1)

I

(1)

I

(1)

I

(1)

I

(1)

X

I

(1)

IN

X

O

-

(1)

OUT

V

-

V

(1)

SS

NOTES:

I/O: Input/Output Pin

I: Input Pin

(1) These pins must be connected to V

, because these

SS

pins are input ports during programming, program verify and reading

(2) These pins must be connected to V

O: Output Pin

.

DD

pin must be opened during programming.

(3) X

OUT

4

GMS81516AT EPROM PROGRAMMING

HYUNDAI MicroElectronics

64QFP Package for GMS81516AT

Pin No.

1

MCU Mode

R65/AN5

OTP Mode

(1)

Pin No.

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

MCU Mode

OTP Mode

A9

I/O

I

O

-

I

R21

R20

R17

R16

R15

R14

R13

R12

R11

R10

R07

R06

R05

R04

R03

R02

R01

R00

R37

R36

R35

R34

R33

R32

R31

R30

I/O

-

I

2

R64/AN4

R63/AN3

R62/AN2

R61/AN1

R60/AN0

R57/PWM1

R56/PWM0

R55/BUZ

R54/WDTO

R53/SRDY

R52/SCLK

R51/SOUT

R50/SIN

(1)

A8

I

3

(1)

A7

I

4

I

(1)

A6

I

5

I

(1)

A5

I

6

I

(1)

A4

I

7

I/O

I

(1)

A3

I

8

(1)

A2

I

9

(1)

A1

I

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

(1)

A0

I

(1)

O7

O6

O5

O4

O3

O2

O1

O0

(1)

I/O

(1)

I/O

(1)

I/O

(1)

I/O

R47/T3O

R46/T1O

R45/EC2

R44/EC0

R43/INT3

R42/INT2

R41/INT1

R40/INT0

RESET

(2)

I/O

(2)

I/O

CE

OE

(1)

I/O

I

-

I

(1)

X

I

(1)

IN

X

O

(3)

(1)

OUT

V

-

V

(1)

SS

A15

A14

A13

A12

A11

A10

R27

R26

R25

R24

R23

R22

I/O

V

DD

PP

MP

I

V

AV

I

(1)

SS

AV

I

(1)

REF

R67/AN7

R66/AN6

I/O

NOTES:

I/O: Input/Output Pin

I: Input Pin

(1) These pins must be connected to V

, because these

SS

pins are input ports during programming, program verify and reading

(2) These pins must be connected to V

O: Output Pin

.

DD

pin must be opened during programming.

(3) X

OUT

5

HYUNDAI MicroElectronics

GMS81516AT EPROM PROGRAMMING

64LQFP Package for GMS81516AT

Pin No.

1

MCU Mode

R63/AN3

OTP Mode

(1)

Pin No.

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

MCU Mode

I/O

OTP Mode

A7

I

O

-

I

R17

R16

R15

R14

R13

R12

R11

R10

R07

R06

R05

R04

R03

R02

R01

R00

R37

R36

R35

R34

R33

R32

R31

R30

I

2

R62/AN2

R61/AN1

R60/AN0

R57/PWM1

R56/PWM0

R55/BUZ

R54/WDTO

R53/SRDY

R52/SCLK

R51/SOUT

R50/SIN

I

(1)

I/O

-

A6

I

3

I

(1)

A5

I

4

I

(1)

A4

I

5

I/O

I

(1)

A3

I

6

(1)

A2

I

7

(1)

A1

I

8

(1)

A0

I

9

(1)

O7

O6

O5

O4

O3

O2

O1

O0

(1)

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

29

30

31

32

(1)

I/O

(1)

I/O

(1)

I/O

R47/T3O

R46/T1O

R45/EC2

R44/EC0

R43/INT3

R42/INT2

R41/INT1

R40/INT0

RESET

(2)

I/O

(2)

I/O

CE

OE

(1)

I/O

I

-

I

(1)

X

I

(1)

IN

X

O

(3)

(1)

OUT

V

-

V

(1)

SS

A15

A14

A13

A12

A11

A10

A9

R27

R26

R25

R24

R23

R22

R21

R20

I/O

V

DD

PP

MP

I

V

AV

I

(1)

SS

AV

I

(1)

REF

R67/AN7

R66/AN6

R65/AN5

R64/AN4

I/O

A8

NOTES:

I/O: Input/Output Pin

I: Input Pin

(1) These pins must be connected to V

, because these

SS

pins are input ports during programming, program verify and reading

(2) These pins must be connected to V

O: Output Pin

.

DD

pin must be opened during programming.

(3) X

OUT

6

GMS81516AT EPROM PROGRAMMING

HYUNDAI MicroElectronics

PIN FUNCTION (OTP Mode)

V

(Program Voltage)

is the input for the program voltage for programming the EPROM.

PP

CE ( Chip Enable)

CE is the input for programming and verifying internal EPROM.

OE (Output Enable)

OE is the input of data output control signal for verify.

A ~A (Address Bus)

0

15

A ~A are address input pins for internal EPROM.

0

15

O ~O (EPROM Data Bus)

0

7

These are data bus for internal EPROM.

PROGRAMMING

The GMS81516AT has address A ~A pins. Therefore, the programmer just program the data (from 4000 to

0

15

H

7FFF ) into the GMS81516AT OTP device, during addresses A ,A must be pulled to a logic high.

H

14 15

When the programmer write the data from 4000 to 7FFF , consequently, the data actually will be written into

H

addresses C000 to FFFF of the OTP device.

H

1. The data format to be programmed is made up of Motorola S1 format.

Ex) "Motorola S1" format;

S0080000574154434880

S1244000E1FF3BFF04A13F8F06E101711B821B1BE01D1B3B191BF6181BF01C1BFF081BFF0AE0

S12440211BF5091BFF0B1BFF3F1B003E1B003D1B003C1BFF3B1B003A1BFF391BFF381BFF353D

:

S1057FF2983FB2

S1057FFEFF3F3F

S9030000FC

2. Down load above data into programmer from PC.

3. Programming the data from address 4000 to 7FFF into the OTP MCU, the data must be turned over

H

respectively, and then record the data. When read the data, it also must be turned over.

Ex) 00(00000000)® FF(11111111), 76(01110110)® 89(10001001), FF(11111111)® 00(00000000) etc.

4. Of course, the check sum is result of the sum of whole data from address 4000 to 7FFF in the file (not reverse

H

data of OTP MCU).

* When GMS81516AT shipped, the blank data of GMS81516AT is initially 00 (not FF ).

H

7

HYUNDAI MicroElectronics

GMS81516AT EPROM PROGRAMMING

Programming Flow

GMS81516AT

xxxxxxxx.OTP

Address

C000

4000

H

Program

Verify

Reading

Down

Loading

File Type:

Program

area

Universal

Programmer

Motorola

S-format

16 K BYTES

7FFF

H

FFFF

H

Programming Example

File

xxxxxxxx.O TP

Programmer

Buffer

GMS81516AT device

Data

Address

Data

Address

Data

Address

E1

FF

3B

FF

04

A1

3F

8F

:

4000

4001

4002

4003

4004

4005

4006

4007

:

E1

FF

3B

FF

04

A1

3F

8F

:

4000

4001

4002

4003

4004

4005

4006

4007

:

H

1E

00

C4

00

FC

5E

C0

70

:

C000

C001

C002

C003

C004

C005

C006

C007

:

H

Down

Loading

Program

:

Up

Loading

Reading

Verify

98

3F

:

FF

3F

7FF2

7FF3

:

7FFE

7FFF

98

3F

:

FF

3F

7FF2

7FF3

:

7FFE

7FFF

H

67

C0

:

00

C0

FFF2

FFF3

:

FFFE

FFFF

H

Checksum = E1+FF+3B+FF+04+A1+3F+8F+ × × × × × × × × + 98+3F+ × × × × +FF+3F

8

GMS81516AT EPROM PROGRAMMING

HYUNDAI MicroElectronics

DEVICE OPERATION MODE

(T = 25°C ± 5°C)

A

Mode

CE

OE

A

~A

X

V

PP

V

DD

V

DD

V

PP

V

PP

V

O ~O

0 7

0

15

DD

Read

X

5.0V

D

OUT

Output Disable

Programming

Program Verify

NOTES:

V

X

Hi-Z

IH

IL

IH

X

V

D

IN

DD

X

D

OUT

1. X = Either V or V

IL

IH

2. See DC Characteristics Table for V

and V

voltages during programming.

PP

DD

DC CHARACTERISTICS

(V =0 V, T = 25°C ± 5°C)

SS

A

Symbol

Item

Min

12.0

5.75

Typ

Max

13.0

6.25

50

Unit

V

Test condition

V

Intelligent Programming

-

PP

(1)

(2)

V

DD

PP

I

V

supply current

mA

V

CE=V

IL

PP

DD

30

DD

V

Input high voltage

Input low voltage

0.8 V

DD

IH

IL

0.2 V

V

DD

V

Output high voltage

Output low voltage

Input leakage current

V

-1.0

V

I

= -2.5 mA

= 2.1 mA

OH

OL

DD

OH

OL

0.4

5

V

I

uA

IL

NOTES:

1. V

must be applied simultaneously or before V

and removed simultaneously or after V

.

PP

DD

PP

2. The maximum current value is with outputs O to O unloaded.

0

7

9

HYUNDAI MicroElectronics

GMS81516AT EPROM PROGRAMMING

SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Will be steady

Must be steady

Will be changing

from H to L

May change

from H to L

Will be changing

from L to H

May change

from L to H

Changing state

unknown

Do not care any

change permitted

Center line is

high impedance

"Off" state

Does not apply

READING WAVEFORMS

V

IH

IL

Addresses

Address Valid

V

IH

IL

(2)

OE

t

OE

AS

t

DH

V

IH

IL

High-Z

Output

Valid Output

NOTES:

1. The input timing reference level is 1.0 V for a V and 4.0V for a V

at V =5.0V

DD

IL

IH

2. To read the output data, transition requires on the OE from the high to the low after address setup time t

.

AS

10

GMS81516AT EPROM PROGRAMMING

HYUNDAI MicroElectronics

PROGRAMMING ALGORITHM WAVEFORMS

Program

Verify

Program

V

IH

Address Stable

Addresses

Data

V

IL

t

AS

t

AH

V

IH

High-Z

Data In Stable

V

IL

Data out Valid

t

DFP

t

DH

t

DS

12.5V

V

PP

DD

V

DD

t

VPS

6.0V

5.0V

t

VDS

V

IH

CE

OE

V

IL

t

OES

t

PW

t

OE

IH

t

OPW

V

IL

NOTES:

1. The input timing reference level is 1.0 V for a V and 4.0V for a V

IL

at V

=5.0V

DD

IH

11

HYUNDAI MicroElectronics

GMS81516AT EPROM PROGRAMMING

AC READING CHARACTERISTICS

(V =0 V, T = 25°C ± 5°C)

SS

A

Symbol

Item

Address setup time

Data output delay time

Data hold time

Min

Typ

Max

Unit

us

Test condition

t

2

AS

OE

DH

200

ns

0

ns

NOTES:

1. V

must be applied simultaneously or before V

and removed simultaneously or after V

.

PP

DD

PP

AC PROGRAMMING CHARACTERISTICS

(V =0 V, T = 25°C ± 5°C; See DC Characteristics Table for V

and V voltages.)

PP

SS

A

DD

Condition*

(Note 1)

Symbol

Item

Min

Typ

Max

Unit

t

Address set-up time

OE set-up time

2

us

ms

AS

t

2

OES

t

Data setup time

2

DS

AH

DH

Address hold time

Data hold time

0

1

t

Output disable delay time

0

DFP

VPS

VDS

V

setup time

2

PP

DD

2

Intelligent

(Note 2)

t

Program pulse width

0.95

1.0

1.05

78.75

200

PW

CE pulse width when over

programming

t

2.85

ms

ns

OPW

t

Data output delay time

OE

*AC CONDITIONS OF TEST

Input Rise and Fall Times (10% to 90%) .

.

20 ns

Input Pulse Levels

.

0.45V to 4.55V

1.0V to 4.0V

Input Timing Reference Level

Output Timing Reference Level

NOTES:

1. V

must be applied simultaneously or before V

and removed simultaneously or after V

.

PP

DD

PP

2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X

Refer to page 13.

12

GMS81516AT EPROM PROGRAMMING

HYUNDAI MicroElectronics

Intelligent Programming Algorithm

START

ADDRESS= FIRST LOCATION

V

= 6.0V

DD

V

= 12.5V

PP

X = 0

PROGRAM ONE 1 ms PULSE

INCREMENT X

YES

X = 25 ?

NO

FAIL

VERIFY

BYTE

FAIL

VERIFY

ONE BYTE

PASS

PROGRAM ONE PULSE

OF 3X msec DURATION

NO

LAST

ADDRESS ?

INCREMENT

ADDRESS

YES

V

= V

= 5.0V

PP

DD

COMPARE

FAIL

ALL BYTES TO

ORIGINAL

DATA

PASS

DEVICE PASSED

DEVICE FAILED

13


型号：	UPA102B-E1
厂家：	HYNIX SEMICONDUCTOR
描述：	USER’S MANUAL 用户手册晶体晶体管 CD 放大器
文件：	总91页 (文件大小：862K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPA102B-E1 [HYNIX]

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