IBM0118160T3-50 [IBM]
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44;
| 型号： | IBM0118160T3-50 |
| 厂家： | 
IBM |
| 描述： | Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总27页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IBM0118160 1M
x 1610/10, 5.0V. IBM0118160P1M x 1610/10, 3.3V, LP, SR. IBM0118160M 1M x 1610/10, 5.0V, LP, SR. IBM0118160B1M x 1610/10, 3.3V.
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Features
• Low Power Dissipation
• 1,048,576 word by 16 bit organization
- Active (max) - 185 mA / 160 mA / 140 mA
- Standby: TTL Inputs (max) - 2.0 mA
- Standby: CMOS Inputs (max)
- 1.0 mA (SP version)
• Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply
• Standard Power (SP) and Low Power (LP)
- 0.2 mA (LP version)
- Self Refresh (LP version only)
- 200µA (3.3 Volt)
• 1024 Refresh Cycles
- 16 ms Refresh Rate (SP version)
- 128 ms Refresh Rate (LP version)
- 300µA (5.0 Volt)
• High Performance:
• 2 CAS
-50
-60
-70
• Read-Modify-Write
tRAC
tCAC
tAA
RAS Access Time
50ns
13ns
25ns
60ns
15ns
30ns
70ns
20ns
35ns
• RAS Only and CAS before RAS
• Hidden Refresh
CAS Access Time
Column Address Access Time
Cycle Time
• Package:
tRC
95ns 110ns 130ns
35ns 40ns 45ns
- TSOP-II 50/44 (400milx825mil)
- SOJ 42/42 (400mil)
tPC
Fast Page Mode Cycle Time
Description
vide high performance, low power dissipation, and
high reliability. The devices operate with a single
3.3V ± 0.3V or 5.0V ± 0.5V power supply. The 20
addresses required to access any bit of data are
multiplexed (10 are strobed with RAS, 10 are
strobed with CAS).
The IBM0118160 is a dynamic RAM organized
1,048,576 words by 16 bits, which has a very low
“sleep mode” power consumption option. These
devices are fabricated in IBM’s advanced 0.5µm
CMOS silicon gate process technology. The circuit
and process have been carefully designed to pro-
Pin Assignments (Top View)
Pin Description
RAS
LCAS / UCAS
WE
Row Address Strobe
L/U Column Address Strobe
Read/Write Input
Address Inputs
50/44 TSOP
42/42 SOJ
VCC
IO0
IO1
IO2
IO3
VCC
IO4
IO5
IO6
IO7
NC
1
50
VSS
VCC
IO0
IO1
IO2
IO3
VCC
IO4
IO5
IO6
IO7
1
2
3
4
5
6
7
8
42
VSS
2
3
4
5
49 IO15
48 IO14
47 IO13
46 IO12
41 IO15
40 IO14
39 IO13
38 IO12
A0 - A9
OE
Output Enable
6
7
8
9
10
11
45
VSS
37
VSS
44 IO11
43 IO10
42 IO9
41 IO8
40 NC
36 IO11
35 IO10
34 IO9
33 IO8
32 NC
I/O0 - I/O15
VCC
Data Input/Output
Power (+3.3V or +5.0V)
Ground
9
10
VSS
NC
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
15
16
17
18
19
20
21
22
23
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
A1
A2
25 A6
24 A5
A3
VCC
20
21
23 A4
24
25
22
VSS
26
VSS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 1 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Ordering Information
Part Number
SP / LP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
LP
Self Refresh Power Supply
Speed
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
Package
Notes
1
IBM0118160T3 -50
IBM0118160T3 -60
IBM0118160T3 -70
IBM0118160BT3 -50
IBM0118160BT3 -60
IBM0118160BT3 -70
IBM0118160J3 -50
IBM0118160J3 -60
IBM0118160J3 -70
IBM0118160BJ3 -50
IBM0118160BJ3 -60
IBM0118160BJ3 -70
IBM0118160MT3 -50
IBM0118160MT3 -60
IBM0118160MT3 -70
IBM0118160PT3 -50
IBM0118160PT3 -60
IBM0118160PT3 -70
IBM0118160MJ3 -50
IBM0118160MJ3 -60
IBM0118160MJ3 -70
IBM0118160PJ3 -50
IBM0118160PJ3 -60
IBM0118160PJ3 -70
No
No
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
1
No
1
No
1
No
1
No
1
No
1
No
1
No
1
No
1
No
1
No
1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
LP
1
LP
1
LP
1
LP
1
LP
1
LP
1
LP
1
LP
1
LP
1
LP
1
LP
1
1. SP = Standard Power version (IBM0118160 and IBM0118160B); LP = Low Power version (IBM0118160M and IBM00118160P)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 2 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Block Diagram
I/O0
I/O15
Vss
Vcc
(5.0 Volt version)
(to OCDs)
16
16
Regulator
OE
V
DD
(internal)
Data In Buffer
Data Out Buffer
WE
&
16
16
UCAS
LCAS
CAS Clock
Generator
OR
Column Address
Buffer (10)
16
Column Decoder and I/O Gate
Sense Amplifiers
10
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
1024 x 16
Controller
Refresh Counter
(10)
Memory Array
10
10
1024
1024 x 1024 x 16
Row Address
Buffer (10)
10
RAS Clock
Generator
RAS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 3 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Truth Table
Row
Address Address
Column
Function
RAS
LCAS UCAS
WE
OE
I/O0 - I/O15
H→X H→X
Standby
H
L
X
H
X
L
X
X
High Impedance
Data Out
Read: Word
L
L
L
Row
Col
Lower Byte: Data Out
Upper Byte: High-Z
Read: Lower Byte
Read: Upper Byte
L
L
L
L
L
H
H
H
L
L
L
Row
Row
Row
Row
Row
Col
Col
Col
Col
Col
Lower Byte: High-Z
Upper Byte: Data Out
H
L
L
L
Write: Word
Early-Write
X
X
X
Data In
Write: Lower Byte
Early-Write
Lower Byte: Data In
Upper Byte: High-Z
L
H
L
L
Write: Upper Byte
Early-Write
Lower Byte: High-Z
Upper Byte: Data In
H
L
H→L
H
L→H
Read-Modify-Write
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
H→L
H→L
H→L
H→L
H→L
H→L
H
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Col
Col
Col
Col
Col
Col
Col
N/A
N/A
Col
Data Out, Data In
Data Out
1st Cycle
L
L
L
Fast Page Mode
Read
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
L
H
Data Out
L
L
X
Data In
Fast Page Mode
Write
L
L
X
Data In
H→L
H→L
X
L→H
L→H
X
L
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
Data Out
Fast Page Mode
Read-Modify-Write
L
L
RAS-Only Refresh
H→L
L→H→L
CAS-Before-RAS Refresh
L
L
H
X
Read
Write
L
L
H
L
Row
Hidden Refresh
L
L
H
X
Row
X
Col
X
Data In
L→H→L
H→L
Self Refresh (LP version only)
L
L
H
X
High Impedance
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 4 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Absolute Maximum Ratings
Rating
Symbol
Parameter
Units Notes
3.3 Volt Device
-0.5 to +4.6
5.0 Volt Device
-1.0 to +7.0
VCC
VIN
Power Supply Voltage
Input Voltage
V
V
1
1
1
1
1
1
1
-0.5 to min (VCC+0.5, 4.6)
-0.5 to min (VCC+0.5, 4.6)
0 to +70
-0.5 to min (VCC+0.5, 7.0)
VOUT
TOPR
TSTG
PD
-0.5 to min (VCC+0.5, 7.0)
Output Voltage
V
°C
°C
W
mA
Operating Temperature
Storage Temperature
Power Dissipation
0 to +70
-55 to +150
1.0
-55 to +150
1.0
IOUT
Short Circuit Output Current
50
50
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Recommended DC Operating Conditions (T = 0 to 70˚C)
A
3.3 Volt Device
5.0 Volt Device
Symbol
Parameter
Units
Notes
Min.
3.0
Typ.
3.3
—
Max.
3.6
Min.
4.5
Typ.
5.0
—
Max.
5.5
VCC
VIH
VIL
Supply Voltage
V
V
V
1
V
CC + 0.5
0.8
VCC + 0.5
0.8
Input High Voltage
Input Low Voltage
2.0
2.4
1, 2
1, 2
-0.5
—
-0.5
—
1. All voltages referenced to VSS
.
2. VIH may overshoot to VCC + 1.2V for pulse widths of ≤ 4.0ns with 3.3 Volt, or VCC + 2.0V for pulse widths of ≤ 4.0ns (or VCC + 1.0V
for ≤ 8.0ns) with 5.0 Volt. Additionally, VIL may undershoot to -2.0V for pulse widths ≤ 4.0ns with 3.3 Volt, or to -2.0V for pulse
widths ≤ 4.0ns (or -1.0V for ≤ 8.0ns) with 5.0 Volt. Pulse widths measured at 50% points with amplitude measured peak to DC ref-
erence.
Capacitance (T = 25°C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
Symbol
CI1
Parameter
Input Capacitance (A0 - A9)
Min.
—
Max.
Units
pF
Notes
5
7
7
1
1
1
CI2
Input Capacitance (RAS, LCAS, UCAS, WE, OE)
Output Capacitance (I/O0 - I/O15)
—
pF
CO
—
pF
1. Input capacitance measurements made with rise time shift method with CAS = VIH to disable output.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 5 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
DC Electrical Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
Symbol
Parameter
Units
mA
Notes
1, 2, 3
Min.
Max.
185
165
140
-50
-60
-70
—
—
—
Operating Current
ICC1
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min.)
Standby Current (TTL)
Power Supply Standby Current
(RAS = CAS = VIH)
ICC2
—
1
mA
mA
-50
-60
—
—
—
—
—
—
—
185
165
140
100
90
RAS Only Refresh Current
Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS = VIH: tRC = tRC min)
ICC3
1, 3
-70
-50
Fast Page Mode Current
Average Power Supply Current
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
ICC4
ICC5
ICC6
-60
mA
mA
mA
1, 2, 3
-70
80
Standby Current (CMOS)
Power Supply Standby Current
(RAS = CAS = VCC - 0.2V)
SP version
1
LP version
—
0.2
-50
-60
—
—
—
—
185
165
140
200
CAS Before RAS Refresh Current
Average Power Supply Current, CAS Before RAS Mode
(RAS, CAS, Cycling: tRC = tRC min)
1, 3
-70
Self Refresh Current, LP version only
3.3V
Average Power Supply Current during Self Refresh
CBR cycle with RAS ≥ tRASS (min); CAS held low;
WE = VCC - 0.2V; Addresses and DIN = VCC - 0.2V or 0.2V.
ICC7
µA
5.0V
—
300
Input Leakage Current
Input Leakage Current, any input
(0.0 ≤ VIN ≤ (VCC + 0.3V)), All Other Pins Not Under Test = 0V
II(L)
IO(L)
VOH
µA
µA
V
-5
-5
+5
+5
Output Leakage Current
(DOUT is disabled, 0.0 ≤ VOUT ≤ VCC
)
Output Level (TTL)
Output “H” Level Voltage
(IOUT = -2.0mA for 3.3V, or IOUT = -5mA for 5.0V)
VCC
2.4
Output Level (TTL)
Output “L” Level Voltage
VOL
0.0
0.4
V
(IOUT = +2.0mA for 3.3V, or IOUT = +4.2mA for 5.0V)
1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3. Address can be changed once or less while RAS =VIL. In the case of ICC4, it can be changed once or less when CAS =VIH.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 6 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
AC Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
1. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using the internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only
refresh cycles is required.
2. AC measurements assume tT=5ns.
3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH
and VIL.
4. When both LCAS and UCAS go low at the same time, all 16 bits of data are read/written into the device. LCAS and UCAS cannot be
staggered within the same read/write cycle.
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
-50
-60
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max.
tRC
tRP
Random Read or Write Cycle Time
RAS Precharge Time
95
30
10
50
13
0
—
—
110
40
10
60
15
0
—
—
130
50
10
70
20
0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCP
CAS Precharge Time
—
—
—
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
RAS Pulse Width
10K
10K
—
10K
10K
—
10K
10K
—
CAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
10
0
—
10
0
—
10
0
—
—
—
—
10
20
15
13
50
5
—
10
20
15
15
60
5
—
10
20
15
20
70
5
—
37
25
—
45
30
—
50
35
—
1
2
CAS Hold Time
—
—
—
CAS to RAS Precharge Time
OE to DIN Delay Time
—
—
—
13
0
—
15
0
—
15
0
—
3
4
4
5
OE Delay Time from DIN
CAS Delay Time from DIN
Transition Time (Rise and Fall)
—
—
—
0
—
0
—
0
—
3
50
3
50
3
50
1. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC
2. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is
.
greater than the specified tRAD(max.) limit, then access time is controlled by tAA
.
3. Either tCDD or tOED must be satisfied.
4. Either tDZC or tDZO must be satisfied.
5. AC measurements assume tT=5ns.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 7 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Write Cycle
-50
-60
-70
Symbol
Parameter
Units
Notes
1
Min. Max. Min. Max. Min. Max.
tWCS
tWCH
tWP
Write Command Set Up Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
DIN Setup Time
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
10
10
13
13
0
15
15
15
15
0
15
15
20
20
0
tRWL
tCWL
tDS
2
2
tDH
DIN Hold Time
10
12
15
1. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical charac-
teristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance)
through the entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min), and tCPW ≥ tCPW (min)(Fast Page Mode), the
cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of con-
ditions are satisfied, the condition of the data out (at access time) is indeterminate.
2. These parameters are referenced to LCAS or UCAS leading edge in early write cycles and to WE leading edge in Read-Modify-
Write cycles.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 8 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Read Cycle
-50
-60
-70
Symbol
Parameter
Access Time from RAS
Units
Notes
Min. Max. Min. Max. Min. Max.
tRAC
tCAC
tAA
—
—
—
—
0
50
13
25
13
—
—
—
—
—
—
—
—
13
13
—
—
—
—
—
0
60
15
30
15
—
—
—
—
—
—
—
—
15
15
—
—
—
—
—
0
70
20
35
20
—
—
—
—
—
—
—
—
15
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
1, 3
2, 3
3
Access Time from CAS
Access Time from Address
Access Time from OE
tOEA
tRCS
tRCH
tRRH
tRAL
tCAL
tCLZ
tOH
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
CAS to Output in Low-Z
0
0
0
4
4
0
0
0
25
25
0
30
30
0
35
35
0
3
Output Data Hold Time
3
3
3
tOHO
tOFF
tOEZ
tCDD
Output Data Hold from OE
Output Buffer Turn-Off Delay
Output Buffer Turn-Off Delay from OE
CAS to DIN Delay Time
3
3
3
—
—
13
—
—
15
—
—
15
5
5
6
1. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC
2. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD
.
is greater than the specified tRAD(max.) limit, then access time is controlled by tAA
.
3. Measured with the specified current load and 100pF.
4. Either tRCH or tRRH must be satisfied for a read cycle.
5. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and are not referenced to output
voltage levels.
6. Either tCDD or tOED must be satisfied.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 9 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Read-Modify-Write Cycle
-50
-60
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max.
tRWC
tRWD
tCWD
tAWD
tOEH
Read-Modify-Write Cycle Time
RAS to WE Delay Time
128
68
31
43
13
—
—
—
—
—
150
80
35
50
15
—
—
—
—
—
180
95
45
60
15
—
—
—
—
—
ns
ns
ns
ns
ns
1
1
1
CAS to WE Delay Time
Column Address to WE Delay Time
OE Command Hold Time
1. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical charac-
teristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance)
through the entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min), and tCPW ≥ tCPW (min)(Fast Page Mode), the
cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of con-
ditions are satisfied, the condition of the data out (at access time) is indeterminate.
Fast Page Mode Cycle
-50
-60
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max.
tPC
Fast Page Mode Cycle Time
35
50
—
30
—
200K
28
40
60
—
35
—
200K
35
45
70
—
40
—
200K
40
ns
ns
ns
ns
tRASP
tCPA
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
1
tCPRH
—
—
—
1. Measured with the specified current load and 100pF.
Fast Page Mode Read-Modify-Write Cycle
-50
-60
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max.
Fast Page Mode Read-Modify-Write
Cycle Time
tPRWC
tCPW
71
48
—
—
80
55
—
—
95
65
—
—
ns
ns
WE Delay Time from CAS Precharge
1
1. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical charac-
teristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance)
through the entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min), and tCPW ≥ tCPW (min)(Fast Page Mode), the
cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of con-
ditions are satisfied, the condition of the data out (at access time) is indeterminate.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 10 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Refresh Cycle
-50
-60
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max.
CAS Setup Time
(CAS before RAS Refresh Cycle)
tCSR
tCHR
tWRP
5
—
—
—
5
—
—
—
5
—
—
—
ns
ns
ns
CAS Hold Time
(CAS before RAS Refresh Cycle)
10
10
10
10
10
10
WE Setup Time
(CAS before RAS Refresh Cycle)
WE Hold Time
(CAS before RAS Cycle)
tWRH
tRPC
10
5
—
—
10
5
—
—
10
5
—
—
ns
ns
RAS Precharge to CAS Hold Time
Self Refresh Cycle - Low Power version only
-50
-60
-70
Symbol
Parameter
Units
Notes
Min.
100
Max.
—
Min. Max. Min. Max.
RAS Pulse Width
tRASS
tRPS
tCHS
tCHD
µs
ns
ns
µs
100
104
-50
—
—
—
—
100
124
-50
—
—
—
—
1
During Self Refresh Cycle
RAS Precharge Time
During Self Refresh Cycle
89
-50
350
—
—
—
1
CAS Hold Time From RAS Rising
During Self Refresh Cycle
1, 2
1, 2
CAS Hold Time From RAS Falling
During Self Refresh Cycle
350
350
1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation:
If row addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles,
then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR- Distributed/Burst; or CBR-Burst) over the refresh interval, then a
full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.
2. If tRASS > tCHD (min) then tCHD applies. If tRASS ≤ tCHD (min) then tCHS applies.
Refresh
-50
Max.
-60
Max.
-70
Max.
SYMBOL
Parameter
Units
ms
Notes
1
Min.
—
Min.
—
Min.
—
SP version
LP version
16
16
16
tREF
Refresh Period
—
128
—
128
—
128
1. 1024 cycles.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 11 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Read Cycle
tRC
tRP
tRAS
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
UCAS
LCAS
tCAS
VIL
tRAD
tASC
tRAL
tCAL
tASR
tRAH
tCAH
VIH
Address
Row
Column
VIL
tRCH
tRCS
tRRH
VIH
VIL
WE
OE
tAA
VIH
VIL
tOEA
tDZC
tCDD
tDZO
tOED
VIH
VIL
Hi-Z
DIN
tCAC
tOFF
tCLZ
tOEZ
VOH
VOL
Valid Data Out
DOUT
Hi-Z
Hi-Z
tRAC
tOH
: “H”: or “L”
tOHO
©IBM Corporation. All rights reserved.
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43G9388
SA14-4209-04
Revised 11/96
Page 12 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Write Cycle (Early Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
tCAS
UCAS
LCAS
VIL
tRAD
tASC
tASR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWCS
tWCH
VIH
VIL
tWP
WE
OE
VIH
VIL
tDS
tDH
VIH
VIL
DIN
Valid Data In
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 13 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Write Cycle (Delayed Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
VIL
UCAS
LCAS
tCAS
tRAD
tASC
tASR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tCWL
tRCS
VIH
VIL
tWP
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tOED
tDZO
tDS
tDZC
VIH
VIL
Valid Data In
DIN
Hi-Z
tOEZ
tCLZ
tOEA
VOH
VOL
*
DOUT
Hi-Z
Hi-Z
*
tOEH greater than or equal to tCWL
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 14 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Read-Modify-Write Cycle
tRWC
tRP
tRAS
VIH
RAS
VIL
tCSH
tRSH
tCAS
tCRP
tRCD
VIH
UCAS
LCAS
tRAD
tASC
VIL
tASR
tRAH
tCAH
VIH
VIL
Row
Column
Address
tCWD
tRWL
tCWL
tAWD
tRWD
tAA
tWP
VIH
VIL
WE
OE
tRCS
tOEH
VIH
VIL
tOEA
tDZC
tDH
tDS
tDZO
Hi-Z
VIH
VIL
DIN
DIN
tCAC
tCLZ
tOED
tOEZ
VOH
VOL
*
Hi-Z
Hi-Z
DOUT
DOUT
tRAC
tOHO
: “H” or “L”
*
tOEH greater than or equal to tCWL
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 15 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Fast Page Mode Read Cycle
tRASP
tRP
VIH
tCPRH
RAS
VIL
tPC
tRCD
tCP
tCP
tRSH
tCAS
tCAL
tCRP
VIH
UCAS
tCAS
tCAS
LCAS
VIL
tCSH
tASC
tRAL
tASC
tRAH
tCAH
tASR
tCAH
tASC
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column n
tRAD
tRCS
tRCS
tRCS
tRCH
tRCH
tRCH
VIH
VIL
WE
OE
tRRH
tAA
tAA
tAA
tCPA
tCPA
tOEA
tOEA
tOEA
VIH
VIL
tOHO
tOH
tOHO
tOH
tOHO
tOH
tDZC
tDZC
tDZC
tCDD
tOED
tDZO
tDZO
tDZO
tOED
tOED
VIH
VIL
DIN
tCAC
tCAC
tCAC
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
tRAC
tCLZ
tCLZ
tCLZ
VOH
VOL
DOUT
DOUT
1
D
OUT 2
DOUT N
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 16 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Fast Page Mode Write Cycle
tRASP
tRP
VIH
RAS
VIL
tPC
tRSH
tCAS
tCRP
tCP
tCP
tRCD
VIH
UCAS
LCAS
tCAS
VIL
tCSH
tASC
tASR tRAH
tCAH
tCAH
tCAH
tASC
tASC
VIH
VIL
Address
Row
Column 1
Column 2
Column n
tRAD
tCWL
tCWL
tRWL
tCWL
tWCH
tWCH
tWCH
tWCS
tWCS
tWCS
VIH
VIL
tWP
tWP
tWP
WE
OE
VIH
VIL
tDS
tDH
tDH
tDH
tDS
tDS
VIH
VIL
DIN
DIN
1
DIN
2
DIN N
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 17 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Fast Page Mode Read-Modify-Write Cycle
tRASP
tRP
VIH
RAS
VIL
tPRWC
tCRP
tRCD
tCP
tCP
tRSH
tCAS
VIH
VIL
UCAS
LCAS
tCAS
tCAS
tCSH
tASC
tCWL
tCWL
tCWL
tASC tCAH
tASC
tRWL
tASR
tCAH
tRAH
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column n
tCPW
tAWD
tCPW
tAWD
tRWD
tAWD
tRCS
tWP
tRCS
tWP
tRCS
tCWD
tCWD
tCWD
tWP
VIH
VIL
WE
OE
tCAC
tCAC
tCAC
tAA
tAA
tAA
tRAD
tCPA
tCPA
VIH
VIL
tOEH
tOEH
tOEH
tOEA
tOEA
tOEA
tDH
tDS
tDH
tDS
tDH
tDS
tDZC
tOED
tOED
tOED
tDZO
VIH
VIL
DIN
DIN
1
DIN 2
DIN N
tOEZ
tOHO
tOEZ
tOHO
tOEZ
tOHO
tCLZ
tCLZ
tCLZ
VOH
VOL
*
DOUT
Hi-Z
tRAC
DOUT
1
DOUT
2
DOUT
N
*
t
OEH greater than or equal to tCWL
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 18 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
RAS Only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCRP
VIH
UCAS
LCAS
VIL
tASR
tRAH
VIH
Address
Row
VIL
VOH
VOL
Hi-Z
DOUT
: “H” or “L”
NOTE: WE, OE and DIN are “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 19 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
CAS Before RAS Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tRPC
tCSR
tCSR
tCP
tCHR
VIH
VIL
UCAS
LCAS
tWRH
tWRH
tWRP
tWRP
VIH
VIL
WE
VIH
VIL
OE
tODD
tCDD
VOH
VOL
DIN
Hi-Z
tOEZ
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: Address is “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 20 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Hidden Refresh Cycle (Read)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRCD
tRSH
tCRP
tCHR
VIH
VIL
UCAS
LCAS
tRAL
tWRH
tWRP
tRAD
tASC
tASR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tRRH
tRCS
VIH
VIL
WE
OE
tAA
VIH
VIL
tOEA
tDZC
tCDD
tDZO
tOED
VIH
VIL
Hi-Z
DIN
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Valid Data Out
Hi-Z
Hi-Z
tRAC
tOH
tOHO
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 21 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Hidden Refresh Cycle (Write)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRSH
tCRP
tRCD
tCHR
VIH
VIL
UCAS
LCAS
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRP
tWRH
tWCS
tWCH
VIH
VIL
tWP
WE
OE
VIH
VIL
tDH
tDS
VIH
VIL
DIN
Valid Data
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 22 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Self Refresh Cycle (Sleep Mode) - Low Power version only
tRASS
tRPS
VIH
RAS
VIL
tRPC
tCHS
tCSR
tCRP
tCP
tCHD
VIH
VIL
UCAS
LCAS
tWRH
tWRP
VIH
VIL
WE
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTES:
1. Address and OE are “H” or “L”
2. Once RAS (min) is provided and RAS remains low, the DRAM
will be in Self Refresh, commonly known as “Sleep Mode.”
3. If tRASS > tCHD (min) then tCHD applies.
If tRASS ≤ tCHD (min) then tCHS applies.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 23 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
PACKAGE DIMENSIONS (400mil; 50/44 lead; Thin Small Outline Package)
20.95 ± 0.10
Detail A
+0.075
-0.005
0.125
Lead #1
Seating Plane
0.10
+ 0.10
- 0.05
0.35
0.80 Basic
0.875 REF
Detail A
0.25 Basic
1.00 ± 0.05
Gage Plane
+0.10
-0.00
0.5 ± 0.1
0.05
NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 24 of 26
IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
PACKAGE DIMENSIONS (400mil; 42/42 lead; Small Outline J-Lead)
27.305 ± 0.127
3.505 ± 0.254
2.083 min
0.76 min
+0.097
0.203
-0.025
Lead #1 I.D.
Lead #1
Seating Plane
0.10
+0.088
0.42
-0.039
+0.123
-0.03
1.27 Basic
0.69
NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 25 of 26
IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Revision Log
Revision
Contents Of Modification
01/94
Initial Release
Change Fast Page Mode Currents (ICC4) from 85, 75, 65, 55mA to 100, 90, 80, 70mA
06/17/94
Combine the 3.3 Volt and the 5.0 Volt specifications
Change the Refresh Period from 256ms to 128ms
09/06/94
Change ICC1, ICC3, ICC6 from 215, 195, 170, 150mA to 225, 205, 180, 160mA
1. Iout changed to +2.0 mA and -2.0 mA in DC Electrical Characteristics table.
2. Packaging diagrams modified to clarify lead thickness and standoff height.
3. t
4. t
min changed from 0 to 5ns.
min changed from 20 to 10ns.
RPC
CHR
5. Currents in DC Electrical Characteristics table revised.
6. Test Modes and Test Circuit Diagram removed.
7. Rename t
to t
.
ODD
OED
11/15/95
8. t
9. t
, t
OED CDD OEZ
, t
, and t
min changed from 20 to 15ns, for the 70ns part.
OFF
min changed from 5 to 0ns for all speed sorts.
min changed from 20 to 15ns for the 70ns part.
min changed from 5 to 10ns for all speed sorts.
RRH
OEH
CSR
10. t
11. t
12. tCAH min changed from 15 to 10ns on 60 and 70ns parts.
13. t max changed from 20 to 15ns for 70ns parts.
OFF
1. The Low Power and Standard Power Specifications were combined. ES# 43G9387 and ES# 43G9388 were
combined into ES# 43G9388.
2. Added Die Rev E part numbers.
3. tDH was reduced from 15ns to 12ns for the -60 speed sort.
4. tCHD was added to the Self Refresh Cycle with a value of 350µs for all speed sorts.
12/10/95
5. The Self Refresh timing diagram was changed to allow CAS to go high tCHD (350µs) after RAS falls entering a
Self Refresh.
6. The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
7. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “L” to ” H”.
1. ICC2 was changed from 2mA to 1mA.
2. II(L) and IO(L) were altered from +/- 10uA to +/- 5uA.
3. tT was initially at a max of 30ns. It has been modified to 50ns for all speed sorts.
4. tCPA was decreased from 30ns to 28ns for the -50 speed sort.
5. tRASP max of 125K was raised to 200K for all speed sorts.
6. tRP was changed from 35ns to 30ns for the -50 speed sort.
09/01/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 26 of 26
International Business Machines Corp.1996
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
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