IBM0316809CT3D-10 [IBM]
Synchronous DRAM, 2MX8, 8ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44;
| 型号： | IBM0316809CT3D-10 |
| 厂家： | 
IBM |
| 描述： | Synchronous DRAM, 2MX8, 8ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总120页 (文件大小：1896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Discontinued (12/98 - last order; 9/99 last ship)
.
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Features
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR), Self Refresh (SR)
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64ms
• High Performance:
-80
CL=3
-360
CL=3
-10
CL=3
Units
fCK
tCK
tAC
Clock Frequency
Clock Cycle
125
8
100
10
100 MHz
10
8
ns
ns
Clock Access Time
6
5.5
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Random Column Address every CLK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• Dual Banks controlled by A11 (Bank Select)
• Programmable CAS Latency: 1,2,3
• Supports LVTTL I/O interface
• Programmable Burst Length: 1,2,4,8,full-page
• Package: 44 pin 400 mil TSOP-Type II (x4,x8)
50 pin 400 mil TSOP-Type II (x16)
2-High Stack TSOJ
• Programmable Wrap Sequence: Sequential or
Interleave
Description
IBM’s 0316409C, 0316809C, and 0316169C
are dual bank Synchronous DRAMs organized as
2Mbit x 4 I/O x 2 Bank, 1Mbit x 8 I/O x 2 Bank, and
512Kbit x 16 I/O x 2 Bank, respectively. These
address A9 is dropped on the x8 device and column
addresses A8 and A9 are dropped on the x16
device. Access to the lower or upper DRAM in a
stacked device is controlled by CS0 and CS1.
devices support LVTTL I/O interface levels.
stacked version of the x 4 component is also
offered. These synchronous devices achieve high
speed data transfer rates of up to 125 MHz. The
chip is fabricated with IBM’s advanced 16Mbit
CMOS DRAM process technology.
A
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A11
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the two memory banks in an inter-
leave fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length,
CAS latency, and speed grade of the device.
The device is designed to comply with all
JEDEC standards set for synchronous DRAM prod-
ucts, both electrically and mechanically. All of the
control, address and data input/output circuits are
synchronized with the positive edge of an externally
supplied clock (CLK).
Internal chip operating modes are defined by
combinations of RAS, CAS, WE, and CS and a com-
mand decoder initiates the necessary timings for
each operation. A twelve bit address bus accepts
address data in the conventional RAS/CAS multi-
plexing style. Eleven row addresses (A0-A10) and a
bank select address (A11) are strobed with RAS.
Ten column addresses (A0-A9) plus A10 and a bank
select address (A11) are strobed with CAS. Column
Auto Refresh (CBR) and Self Refresh (SR)
operation are supported. Refreshing both decks of a
stacked device simultaneously is allowed during
Self Refresh but all other stacked device operations
must be performed on a single deck at a time.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Pin Assignments for Planar Components (Top View)
VDD
1
44
V
VDD
1
44
V
VDD
1
50
V
SS
SS
SS
NC
VSSQ
DQ0
2
43
42
41
40
39
38
37
36
35
NC
DQ0
VSSQ
DQ1
2
43
42
41
40
39
38
37
36
35
DQ7
DQ0
DQ1
2
49
48
47
46
45
44
43
42
41
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
3
VSSQ
DQ3
VDDQ
NC
3
VSSQ
DQ6
3
4
4
VSSQ
DQ2
4
VDDQ
NC
5
VDDQ
DQ2
5
VDDQ
DQ5
5
6
6
DQ3
6
VSSQ
DQ1
7
VSSQ
DQ2
VDDQ
NC
VSSQ
DQ3
7
VSSQ
DQ4
VDDQ
DQ4
7
8
8
8
VDDQ
NC
9
VDDQ
NC
9
VDDQ
NC
DQ5
9
10
10
VSSQ
10
NC
WE
11
12
34
33
NC
NC
WE
11
12
34
33
NC
DQ6
DQ7
11
12
40
39
DQ9
DQ8
DQM
DQM
CAS
RAS
13
14
15
16
17
18
19
20
32
31
30
29
28
27
26
25
CLK
CKE
NC
A9
CAS
RAS
13
14
15
16
17
18
19
20
32
31
30
29
28
27
26
25
CLK
CKE
NC
A9
VDDQ
LDQM
13
14
15
16
17
18
19
20
38
37
36
35
34
33
32
31
VDDQ
NC
UDQM
CLK
CKE
NC
CS
A11(BS)
CS
A11(BS)
WE
CAS
A10
A0
A8
A10
A0
A8
RAS
CS
A7
A7
A1
A6
A1
A6
A11(BS)
A10
A9
A2
A5
A2
A5
A8
A3
VDD
21
22
24
23
A4
A3
VDD
21
22
24
23
A4
V
SS
A0
A1
21
22
23
30
29
28
A7
A6
V
SS
A2
A5
A3
VDD
24
25
27
26
A4
V
SS
44-pin Plastic TSOP(II) 400 mil
2Mbit x 4 I/O x 2 Bank
IBM0316409CT3
44-pin Plastic TSOP(II) 400 mil
1Mbit x 8 I/O x 2 Bank
IBM0316809CT3
50-pin Plastic TSOP(II) 400 mil
512Kbit x 16 I/O x 2 Bank
IBM0316169CT3
Pin Description
CLK
CKE
CS
Clock Input
DQ0-DQ15
Data Input/Output
Data Mask
Clock Enable
Chip Select
DQM, LDQM, UDQM
VDD
VSS
VDDQ
VSSQ
NC
Power (+3.3V)
Ground
RAS
CAS
Row Address Strobe
Column Address Strobe
Write Enable
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
WE
A11 (BS)
A0 - A10
Bank Select
Address Inputs
—
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Pin Assignments for 2-High Stack Package (Dual CS Pins) (Top View)
VDD
1
44
V
SS
NC
VSSQ
DQ0
2
43
42
41
40
39
38
37
36
35
NC
3
VSSQ
DQ3
4
VDDQ
NC
5
VDDQ
NC
6
VSSQ
DQ1
7
VSSQ
DQ2
8
VDDQ
NC
9
VDDQ
NC
10
NC
WE
11
12
34
33
NC
DQM
CAS
RAS
13
14
15
16
17
18
19
20
32
31
30
29
28
27
26
25
CLK
CKE
NC/CS1 *
A9
* CS0/NC
A11 (BS)
A10
A0
A8
A7
A1
A6
A2
A5
A3
VDD
21
22
24
23
A4
V
SS
44-pin Plastic TSOJ(II) 400 mil
(2Mbit x 4 I/O x 2 Bank) x 2 High
IBM03164B9CT3
* CS0 selects the lower DRAM in the stack.
* CS1 selects the upper DRAM in the stack.
Pin Description
CLK
CKE
Clock Input
DQ0-DQ3
DQM
VDD
Data Input/Output
Data Mask
Clock Enable
Chip Select
CS0, CS1
RAS
Power (+3.3V)
Ground
Row Address Strobe
Column Address Strobe
Write Enable
VSS
CAS
VDDQ
VSSQ
NC
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
WE
A11 (BS)
A0 - A10
Bank Select
Address Inputs
—
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Input/Output Functional Description
Symbol
Type Signal
Polarity
Function
Positive The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
CLK
Input
Input
Pulse
Level
Edge
clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deacti-
vating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
Active
High
CKE
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables
Pulse Active Low the command decoder when high. When the command decoder is disabled, new com-
mands are ignored but previous operations continue.
CS,
CS0, CS1
Input
RAS, CAS
WE
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
Input
Input
Pulse Active Low
A11 (BS)
A0 - A10
Level
Selects which bank is to be active. A11 low selects bank A and A11 high selects bank B.
—
During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge.
A10 is used to invoke Auto-Precharge operation. If A10 is high, Auto-Precharge is
selected and A11 defines the bank to be precharged (low=bank A, high=bank B). If A10 is
low, Auto-Precharge is disabled.
Input
Level
—
During a Precharge command cycle, A10 is used in conjunction with A11 to control which
bank(s) to precharge. If A10 is high, both bank A and bank B will be precharged regardless
of the state of A11. If A10 is low, then A11 is used to define which bank to precharge.
Input
Output
DQ0 - DQ15
Level
Data Input/Output pins operate in the same manner as on conventional DRAMs.
—
The DQ mask (DQM) places the DQ buffers in a high impedance state when sampled
high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers
Pulse Active Low consistent with an output enable. In Write mode, DQM has a latency of zero and operates
as a word mask by allowing input data to be written if it is low but blocks the write opera-
tion if DQM is high.
DQM
LDQM
UDQM
Input
VDD, V
SS
Supply
—
—
—
—
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immu-
nity.
VDDQ, VSSQ Supply
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Ordering Information - Planar Devices (Single CS Pin)
CAS
Latencies
I/O
Width
I/O
Type
Power
Supply
Clock
Cycle
Part Number
Package
IBM0316409CT3D-80
IBM0316409CT3D-10
IBM0316809CT3D-80
IBM0316809CT3D-360
IBM0316809CT3D-10
IBM0316169CT3D-80
IBM0316169CT3D-10
2,3
1,2,3
2,3
x4
x4
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
400mil Type II TSOP-44
400mil Type II TSOP-44
400mil Type II TSOP-44
400mil Type II TSOP-44
400mil Type II TSOP-44
400mil Type II TSOP-50
400mil Type II TSOP-50
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
8ns
10ns
8ns
x8
2,3
x8
10ns
10ns
8ns
1,2,3
2,3
x8
x16
x16
1,2,3
10ns
Ordering Information - 2 High Stacked Devices (Dual CS Pins)
CAS
Latencies
I/O
Width
I/O
Type
Power
Supply
Clock
Cycle
Part Number
Package
IBM03164B9CT3D-10
1,2,3
x4
LVTTL
400mil Type II TSOJ-44 2-High
3.3V
10ns
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Block Diagram (2Mbit x 4 I/O x 2 Bank)
2048 x 1024
2048
Memory Bank A
CKE Buffer
CKE
Self
Refresh Clock
Row
Address
Counter
Sense Amplifiers
Bank A
Row/Column
Select
Column Decoder and DQ Gate
CLK Buffer
CLK
4
8
Predecode A
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Sequential
Control
Bank A
Data Latches
3
12
2
DQ0
DQ1
DQ2
DQ3
8
8
Mode Register
11
A10
A11 (BS)
Sequential
Control
Bank B
CS Buffer
RAS Buffer
CAS Buffer
3
CS
RAS
CAS
Data Latches
8
11
Predecode B
Bank B
Row/Column
Select
Column Decoder and DQ Gate
Sense Amplifiers
WE Buffer
WE
Memory Bank B
2048 x 1024
2048
DQM Buffer
DQM
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Block Diagram (1Mbit x 8 I/O x 2 Bank)
2048 x 512
2048
Memory Bank A
CKE Buffer
CKE
Self
Refresh Clock
Row
Address
Counter
8
Sense Amplifiers
Bank A
Row/Column
Select
Column Decoder and DQ Gate
8
CLK Buffer
CLK
8
8
Predecode A
11
DQ0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Data Latches
Sequential
Control
Bank A
DQ1
3
12
12
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
8
8
Mode Register
11
A10
A11 (BS)
Sequential
Control
Bank B
8
CS Buffer
RAS Buffer
CAS Buffer
3
CS
RAS
CAS
Data Latches
8
11
Predecode B
8
Bank B
Row/Column
Select
Column Decoder and DQ Gate
Sense Amplifiers
8
WE Buffer
WE
Memory Bank B
2048
2048 x 512
DQM Buffer
DQM
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Block Diagram (512Kbit x 16 I/O x 2 Bank)
2048 x 256
Memory Bank A
CKE Buffer
CKE
2048
Self
Refresh Clock
16
Row
Address
Counter
DQ0
DQ1
16
SenseAmplifiers
Column Decoder and DQ Gate
DQ2
Bank A
Row/Column
Select
DQ3
DQ4
CLK Buffer
CLK
DQ5
16
DQ6
8
Predecode A
DQ7
11
Data Latches
DQ8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Sequential
Control
Bank A
DQ9
3
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
12
12
16
8
Mode Register
11
8
A10
A11 (BS)
Sequential
Control
Bank B
16
CS Buffer
RAS Buffer
CAS Buffer
3
CS
RAS
CAS
WE
Data Latches
8
11
Predecode B
16
Bank B
Row/Column
Column Decoder and DQ Gate
Select
Sense Amplifiers
16
WE Buffer
DQM Buffer
DQM Buffer
2048
Memory Bank B
2048 x 256
UDQM
LDQM
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Block Diagram (2Mbit x 4 I/O x 2 Bank) x 2-High
CS0
CS1
CKE
CLK
DQ0
DQ1
DQ2
DQ3
A10-A0
A11(BS)
2Mb x 4 I/O x 2 Bank
RAS
CAS
WE
DQM
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following
power on and initialization sequence guarantees the device is preconditioned to each user’s specific needs.
Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined man-
ner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage no
later than any of the input signal voltages. The power on voltage must not exceed VDD+0.3V on any of the
input pins or VDD supplies. After power on, an initial pause of 100µs is required followed by a precharge of
both banks using the precharge command. To reduce the possibility of data contention on the DQ bus during
power on, it is recommended that the DQM pin(s) be held high during the initial pause period. Once both
banks have been precharged, a minimum of two Auto Refresh cycles (CBR) must occur before the Mode
Register can be programmed. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined vari-
ables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command.
Contents of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user
chooses to modify only a subset of the Mode Register variables, all variables must be redefined when the
Mode Register Set Command is issued.
After initial power up, the Mode Register Set Command must be issued before read or write cycles may
begin. Both banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of
RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the
parameters to be set as shown in the Mode Register Operation table. A new command may be issued on the
second clock following the mode register set command.
CAS Latency
CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a
rising clock edge to when the data from that Read Command becomes available at the outputs. CAS latency
is expressed in terms of clock cycles and can be programmed to a value of 1, 2, or 3 cycles. The value of
CAS latency is determined by the speed grade of the device and the clock frequency that is used in the appli-
cation. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears
in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been
selected it must be programmed into the mode register after power up. For an explanation of this procedure,
see Programming the Mode Register in the previous section.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Mode Register Operation (Address Input For Mode Set)
BS
A10
A9
Address Bus (Ax)
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Operation Mode
CAS Latency
BT
Burst Length
Operation Mode
Burst Type
M11 M10 M9 M8 M7
Mode
M3
0
Type
0
0
0
1
0
0
0
0
Normal
Sequential
Interleave
Multiple Burst with
Single Write
1
X
X
CAS Latency
Burst Length
M6 M5 M4
Latency
Reserved
1
Length
M2 M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sequential Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
2
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). There are three parameters that define how the burst mode will operate.
These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst
length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set com-
mand. Operation mode is also programmable and is set by address bits A7 - A10 and BS.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM.
Two types of burst sequences are supported, sequential and interleaved. See Table.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits
to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full
page (actual page length is dependent on organization: x4, x8, or x16). Full page burst operation is only pos-
sible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation
implies that the device will perform burst operations on both read and write cycles until the desired burst
length is satisfied. Multiple burst with single write operation was added to support Write Through Cache oper-
ation. Here, the programmed burst length only applies to read cycles. All write cycles are single write opera-
tions when this mode is selected.
Burst Length and Sequence
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
0, 1
Interleave Addressing (decimal)
0, 1
x x 0
x x 1
x 0 0
x 0 1
x 1 0
x 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
n n n
2
1, 0
1, 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
4
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
Cn, Cn+1, Cn+2, ......
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Not Supported
8
Full Page (Note)
Note: Page length is a function of I/O organization and column addressing.
x4 organization (CA0-CA9); Page Length = 1024 bits
x8 organization (CA0-CA8); Page Length = 512 bits
x16 organization (CA0-CA7); Page Length = 256 bits
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling
RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the
rising edge of the clock. The bank select address, A11 (sometimes referred to as BS), is used to select the
desired bank. If BS is low then bank A is activated, if BS is high then bank B is activated. The row address A0
- A10 is used to determine which row to activate in the selected bank. Only banks A and B within a single
deck of a 2-High stacked device can be accessed. Simultaneous operation of both decks in a stacked device
is not allowed, except during Self Refresh.
The Bank Activate command must be applied before any Read or Write operation can be executed. The
delay from when the Bank Activate command is applied to when the first read or write operation can begin
must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time inter-
val between successive Bank Activate commands to the same bank is determined by the RAS cycle time of
the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B
and vice versa) is the Bank to Bank delay time (tRRD).
Bank Activate Command Cycle (CAS Latency = 3, t
= 3)
RCD
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
. . . . . . . . . .
Bank A
Col. Addr.
Bank A
Row Addr.
Bank B
Row Addr.
Bank A
Row Addr.
. . . . . . . . . .
ADDRESS
RAS-CAS delay (tRCD
)
RAS - RAS delay time (tRRD
)
Write A
with Auto-
Precharge
Bank B
NOP
Bank A
Activate
Bank A
Activate
. . . . . . . . . .
NOP
NOP
NOP
COMMAND
Activate
RAS Cycle time (tRC
)
: “H” or “L”
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Discontinued (12/98 - last order; 9/99 last ship)
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IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be
defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation
(WE low).
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles at data rates of up to 125 MHz. The number of serial
data bits for each access is equal to the burst length, which is programmed into the Mode Register. Although
the burst length is user programmable, the boundary of the burst cycle is restricted to specific segments of
the page length.
For example, the 2Mbit x 4 I/O x 2 Bank device has a page length of 1024 bits (defined by CA0-CA9). If a
burst length of 4 is programmed into the Mode Register, then the page length is divided into 256 uniquely
addressable boundary segments (4-bits each). A 4-bit burst operation will occur entirely from one of the 256
groups beginning with the column address supplied to the device during the Read or Write Command (CA0-
CA9). The second, third, and fourth access will also occur within this group segment, however, the burst
order is a function of the starting address, the burst sequence, and burst boundary.
The above discussion does not apply when full page burst is programmed into the Mode Register. Full page
burst operation is only allowed for the sequential burst sequence and has no address boundaries. The
SDRAM device will continue bursting data even after all locations of the page have been accessed. The burst
sequence will start at the column address defined during the read or write cycle and will increment sequen-
tially until the highest order column address has been reached. At this point, the burst counter will reset to
address 0 and continue to perform burst read or burst write operations sequentially until either a Burst Stop
Command is issued, a Precharge Command is issued to the bursting bank, or until a new Read or Write
Command is issued.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers
latch the selected row address information. The refresh period (tREF) is what limits the number of random col-
umn accesses to an activated bank. A new burst access can be done even before the previous burst ends.
The ability to interrupt a burst operation at every clock cycle is supported, this is referred to as the 1-N rule.
When the previous burst is interrupted by another Read or Write Command, the remaining addresses are
overridden by the new address once the CAS Latency has been satisfied.
Precharging an active bank after each read or write operation is not necessary providing the same row is to
be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must
be precharged and a new Bank Activate command must be issued. When both Bank A and Bank B are acti-
vated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst
length and alternating the access and precharge operations between the two banks, fast and seamless data
access operation among many different pages can be realized. When the two banks are activated, column to
column interleave operation can be done between two different pages. Finally, Read or Write Commands can
be issued to the same bank or between active banks on every clock cycle.
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register
sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the start
of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS
latency that is set in the Mode Register.
Burst Read Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
0
1
2
3
t
CK1, DQs
CAS latency = 2
DOUT A
3
0
1
2
t
CK2, DQs
CAS latency = 3
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
t
CK3, DQs
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When a
burst read operation is interrupted, the remaining addresses of the current burst cycle are overridden starting
with the new column address applied with the interrupting Read Command. The data from the first Read
Command continues to appear on the DQs until the CAS latency of the interrupting Read Command is satis-
fied. At this point, the data from the interrupting Read Command will appear on the DQs and continue for the
full burst length.
Read Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
READ B
DOUT A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DOUT B
DOUT A
DOUT B
DOUT B
DOUT B
3
0
0
1
2
t
CK1, DQs
CAS latency = 2
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
0
0
1
2
3
t
CK2, DQs
CAS latency = 3
DOUT A
DOUT B
DOUT B
3
0
0
1
2
t
CK3, DQs
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM must be used to avoid data contention on the data bus
by placing the chip output drivers in a high impedance state at least one clock cycle before the Write Com-
mand is initiated. To insure the chip output drivers are tri-stated one cycle before the write operation begins,
DQM must be activated at least 3 clock cycles before the Write Command and be deactivated in the same
clock cycle as the Write Command.
Read Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
: “H” or “L”
DQM
READ A
NOP
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
COMMAND
Must be Hi-Z before
the Write Command
CAS latency = 1
DOUT A
DOUT A
DOUT A
DIN A
0
DIN A
DIN A
DIN A
3
0
1
2
1
2
tCK1, DQs
CAS latency = 2
DOUT A
DOUT A
DIN A
DIN A
DIN A
DIN A
3
0
1
0
1
2
t
CK2, DQs
CAS latency = 3
DOUT A
DIN A
DIN A
DIN A
DIN A
3
0
0
1
2
tCK3, DQs
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Write Command
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. There is no CAS latency
required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same
clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subse-
quent rising clock edge until the burst length is completed. When the burst has finished, any additional data
supplied to the DQ pins will be ignored.
Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQs
DIN A
0
don’t care
DIN A
DIN A
DIN A
3
1
2
The first data element and the Write
are registered on the same clock edge.
Extra data is masked.
Write Interrupted by a Write
A burst write operation may be interrupted before completion of the burst. When a burst write cycle is inter-
rupted by a new Write Command, the remaining addresses of the initial write cycle are overridden starting
with the new column address applied with the interrupting Write Command. Data will be written into the
device until the programmed burst length of the last write command is satisfied.
Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQs
1 Clk Interval
DIN A
DIN B
0
DIN B
DIN B
DIN B
3
0
1
2
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is
registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data
appears on the outputs to avoid data contention. When the Read Command is registered, any residual data
from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is
initiated will actually be written to the memory.
Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DIN A
0
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
2
3
t
CK1, DQs
CAS latency = 2
don’t care
don’t care
DIN A
0
DOUT B
DOUT B
0
1
2
3
t
CK2, DQs
CAS latency = 3
don’t care
DIN A
0
DOUT B
DOUT B
DOUT B
3
0
1
2
t
CK3, DQs
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the Write is masked.
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Stop Command
Once a burst read or write operation has been initiated, there exist several methods in which to terminate the
burst operation prematurely. These methods include using another Read or Write Command to interrupt an
existing burst operation, using a Precharge Command to interrupt a burst cycle and close the active bank, or
using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future
Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read
or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to use when terminating a burst operation before it has been
completed.
The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. When using the Burst Stop Command during a burst read cycle, the data DQs go to a high imped-
ance state after a delay which is equal to the CAS Latency set in the Mode Register.
Termination of a Burst Read Operation (Burst Length > 4, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
The burst ends after a delay equal to the CAS latency.
The bank remains activated.
CAS latency = 1
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
0
1
0
2
3
2
1
t
CK1, DQs
CAS latency = 2
DOUT A
DOUT A
DOUT A
3
1
0
t
CK2, DQs
CAS latency = 3
DOUT A
DOUT A
3
2
t
CK3, DQs
When a Burst Stop Command is issued during a burst write operation, only data presented prior to the Burst
Stop command will be written into the device. Any data presented to the device coincident with the Burst Stop
command or later will be ignored.
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Termination of a Burst Write Operation (Burst Length =X, CAS Latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1,2,3
don’t care
DIN A
0
DIN A
DIN A
2
1
DQs
Input data for the Write is masked.
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM,
the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically
begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the
Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank
remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is
issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute
as normal with the exception that the active bank will begin to precharge immediately and may finish before
all burst read cycles have been completed. This feature allows the precharge operation to be partially or com-
pletely hidden during the burst read cycles (dependent upon burst length) thus improving system perfor-
mance for random data access. Auto-precharge can also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. How-
ever, a Read or Write Command with auto-precharge can not be interrupted by a command to the same
bank. Therefore use of a Read, Write, Precharge, or Burst Stop Command to the same bank is prohibited
during a read or write cycle with auto-precharge until the entire burst operation is completed.
If A10 is high when a Read Command is issued, the Read with auto-precharge function is initiated. Once the
precharge operation has started the bank cannot be reactivated until an asynchronous delay time equal to tRP
+ tDPL, expressed in nanoseconds rather than clocks, has been satisfied. It should be noted that the device will
not respond to the Auto-Precharge Command if the device is programmed for full page burst read or write
cycles.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Read with Auto-Precharge (Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tRP + tDPL
DOUT A
*
tCK2
DQs
DOUT A
DOUT A
DOUT A
3
0
1
2
tRP*+ tDPL
tCK3
DQs
*
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
Bank can be reactivated after completion of tRP + tDPL
For Auto-Precharge, this is an asynchronous delay
which may complete prior to a clock edge,depending
.
*
Begin Auto-precharge.
on tRP tDPL
tCK. The bank cannot be reactivated
,
and
until the rising clock edge following the completion of
*
tRP, tRCD= 2 clocks for -360
the delay.
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it
can be interrupted by a Read or Write Command to the other bank. The auto-precharge function will begin
normally with the issuing command.
Burst Read w/ Auto-precharge Interrupted by Read (Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ B
COMMAND
Auto-Precharge
tRP + tDPL
*
CAS latency = 2
t
CK2, DQs
DOUT A
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
0
1
0
0
1
1
2
3
tRP*+ tDPL
*
CAS latency = 3
t
CK3, DQs
DOUT A
DOUT A
DOUT B
DOUT B
DOUT B
3
0
1
2
Begin Auto-precharge A
Bank can be reactivated at completion of t
t
RP + DPL
*
*
tRP, tRCD= 2 clocks for-360
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ
contention.
Burst Read with Auto-precharge Interrupted by Write (Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRITE B
DOUT B
COMMAND
Auto-Precharge
tRP+tDPL
*
CAS latency = 2
t
CK2, DQs
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
4
0
0
1
2
3
DQM
Begin Auto-precharge A
Bank A can be reactivated at completion of t
t
RP + DPL
*
If A10 is high when a Write Command is issued, the Write with auto-precharge function is initiated. The bank
undergoing auto-precharge can not be reactivated until tDPL and tRP are satisfied. This is referred to as tDAL,
Data-in to Active delay (tDAL= tDPL + tRP), and is an asynchronous delay time during auto-precharge.
Burst Write with Auto-Precharge (Burst Length = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tDAL
tCK2
DQs
DIN A
DIN A
DIN A
DIN A
0
1
*
tDAL
tCK3
DQs
0
1
*
*
Bank can be reactivated after completion of tDAL
.
For Auto-Precharge, tDAL is an asynchronous delay
which may complete prior to a clock edge, depending
on tRP tDPL
until the rising clock edge following the delay.
tCK. The bank cannot be reactivated
Begin Auto-precharge.
,
and
©IBM Corporation. All rights reserved.
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08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command
to the same bank. It can be interrupted by a Read or Write Command to the other bank, however. The auto-
precharge function is unaffected by the interrupting command and will begin as normally scheduled according
to burst length.
Burst Write with Auto-Precharge Interrupted by Write (Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
NOP
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tDAL
*
CAS latency = 3
t
CK3, DQs
DIN A
DIN A
DIN B
DIN B
DIN B
DIN B
3
0
1
0
1
2
Begin Auto-precharge
*
tRP, tDPL = 2 clocks for-360
Bank A can be reactivated at completion of tDAL
*
Burst Write with Auto-Precharge Interrupted by Read (Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tDAL
*
CAS latency = 3
t
CK3, DQs
DIN A
0
DIN A
DIN A
2
DOUT B
DOUT B
DOUT B
2
1
0
1
Begin Auto-precharge
*
tRP, tDPL = 2 clocks for-360
Bank A can be reactivated at completion of tDAL
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank separately or both banks simultaneously. Two
address bits A10 and A11 (BS) are used to define which bank(s) is to be precharged when the command is
issued.
Bank Selection for Precharge by Address Bits
A10
LOW
LOW
HIGH
BS(A11)
LOW
Precharged Bank(s)
Bank A only
HIGH
Bank B only
DON’T CARE
Both Banks A and B
For read cycles, the Precharge Command may be applied consistent with the CAS Latency set in the Mode
Register. The data DQs go to a high impedance state after a delay which is equal to the latency, similar to a
Burst Stop Command. Refer to the following figures.
For write cycles, however, a delay must be satisfied from the start of the last burst write cycle until the Pre-
charge Command can be issued. This delay is known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (tRP).
Burst Read followed by Precharge Command (Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
COMMAND
0
tRP
*
CAS latency = 2
DOUT Ax
DOUT Ax
DOUT Ax
DOUT Ax
3
0
1
2
t
CK2, DQs
Bank can be reactivated at completion of t
.
RP
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Read followed by Precharge Command (Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
COMMAND
0
tRP
*
CAS latency = 3
DOUT Ax
DOUT Ax
1
DOUT Ax
DOUT Ax
3
0
2
t
CK3, DQs
(-80,-10)
Bank can be reactivated at completion of t
.
RP
*
Burst Read followed by Precharge Command (Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
COMMAND
0
tRP
*
CAS latency = 3
DOUT Ax
DOUT Ax
1
DOUT Ax
DOUT Ax
0
2
3
t
CK3, DQs
(-360)
Bank can be reactivated at completion of t
.
RP
*
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Use is further subject to the provisions at the end of this document.
08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Write followed by Precharge Command (Burst Length = 2, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Activate
Bank Ax
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tRP
tDAL
*
CAS latency = 2
t
CK2, DQs
DIN Ax
DIN Ax
1
0
Bank can be reactivated at completion of tDAL (tDPL + tRP).
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Write followed by Precharge Command (Burst Length = 2, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
Activate
Bank Ax
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
COMMAND
WRITE Ax
0
tDPL
tRP
tDAL
CAS latency=3
tCK3, DQs
(-80, -10)
*
DIN Ax
DIN Ax
1
0
Activate
Bank Ax
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tDAL
tRP
*
CAS latency=3
tCK3, DQs
(-360)
DIN Ax
DIN Ax
0
1
Bank can be reactivated at completion of tDAL (tDPL + tRP).
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the
Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read
operations, valid data will continue to appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge (Burst Length = 8, CAS latency = 1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
READ Ax
NOP
NOP
NOP
NOP
NOP
Precharge A
tRP
NOP
COMMAND
0
*
CAS latency = 1
DOUT Ax
DOUT Ax
0
1
t
CK1, DQs
Bank can be reactivated at completion of t
RP
.
Burst is terminated one clock after the Precharge command,
consistent with CAS Latency.
*
Burst Read Interrupted by Precharge (Burst Length = 8, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
DOUT Ax
NOP
COMMAND
0
tRP
*
CAS latency = 2
DOUT Ax
DOUT Ax
0
1
2
t
CK2, DQs
Bank can be reactivated at completion of t
.
Burst is terminated two clocks after the Precharge command,
consistent with CAS Latency.
RP
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst Read Interrupted by Precharge (Burst Length = 8, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
DOUT Ax
COMMAND
0
tRP
*
CAS latency = 3
t
CK3, DQs
DOUT Ax
DOUT Ax
DOUT Ax
3
0
1
2
(-80, -10)
Bank can be reactivated at completion of tRP
.
Burst is terminated three clocks after the Precharge command,
consistent with CAS Latency.
*
Burst Read Interrupted by Precharge (Burst Length = 8, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax
NOP
NOP
NOP
tRP
NOP
NOP
NOP
NOP
Precharge A
COMMAND
0
*
DQM
CAS latency = 3
t
CK3, DQs
DOUT Ax
DOUT Ax
DOUT Ax
DOUT Ax
3
0
1
2
(-360)
Burst is terminated three clocks after the Precharge command,
consistent with CAS Latency.
Bank can be reactivated at completion of tRP
.
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst write operations will be terminated by the Precharge command. However, write data written to the
device prior to the Precharge command may be stored incorrectly and is a function of CAS latency and tDPL
.
When CAS latency is set to equal 1 or 2 or when set to 3 with tDPL = 1 clock, the last write data that will be
properly stored in the device is that write data that is presented to the device on the clock cycle prior to the
Precharge command. The write data presented during the Precharge command will not be written.
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tRP
tDAL
*
CAS latency = 1
t
CK1, DQs
DIN Ax
DIN Ax
DIN Ax
2
0
1
Bank can be reactivated at completion of t
DAL
*
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tRP
tDAL
*
CAS latency = 2
t
CK2, DQs
DIN Ax
DIN Ax
DIN Ax
2
0
1
Bank can be reactivated at completion of tDAL
.
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tRP
tDPL
tDAL
*
CAS latency = 3
CK3,DQs
t
DIN Ax
DIN Ax
DIN Ax
2
0
1
(-80, -10)
Bank can be reactivated at completion of tDAL
.
*
When CAS latency is set to equal 3 and tDPL = 2 clocks, the last write data that will be properly stored in the
device is that write data that is presented to the device two clocks prior to the Precharge command. The write
data presented during the clock cycle prior to the Precharge command may be stored incorrectly. To prevent
the writing of invalid data to the device, DQM must be asserted high one clock cycle prior to the Precharge
command to mask the invalid write data.
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tRP
tDAL
*
CAS latency = 3
tCK3,
DQs
DIN Ax
DIN Ax
1
0
-360
(
)
DQM is needed to mask
the invalid data
Bank can be reactivated at completion of tDAL
.
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Automatic Refresh Command (CAS Before RAS Refresh)
When CS, RAS and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters
the Automatic Refresh mode (CBR). Both banks of the SDRAM must be precharged and idle for a minimum
of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. For a stacked device,
only one deck at a time can be refreshed using Automatic Refresh Mode. An address counter, internal to the
device, supplies the bank address during the refresh cycle. No control of the external address pins is required
once this cycle has started.
When the refresh cycle has completed, both banks of the SDRAM will be in the precharged (idle) state. A
delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto
Refresh Command must be greater than or equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command
is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the
Command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM
has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is
internally disabled during Self Refresh Operation to save power. The user may halt the external clock while
the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self
Refresh operation. Once the clock is cycling, the exit command will be registered asynchronously by bringing
CKE high. After CKE is brought high, an internal timer is started to insure CKE is held high for approximately
10ns before registering the Self Refresh exit command. The purpose of this circuit is to filter out noise glitches
on the CKE input which may cause the SDRAM to erroneously exit Self Refresh operation. Once the Self
Refresh command is registered, a delay equal to the RAS cycle time (tRC) must be satisfied before any new
command can be issued to the device. CKE must remain high for the entire Self Refresh exit period (tSREX
and commands must be gated off with CS held high. Alternatively, NOP commands may be registered on
each positive clock edge during the Self Refresh exit interval. (See Self Refresh Exit figures.) When using
Self Refresh, both decks of a stacked device may be refreshed at the same time.
)
Self Refresh Exit (Commands Gated Off with CS High)
T
T
T
T
T
T
T
T
T
m
m+1
m+2
m+3
m+4
m+5
m+6
m+7
m+8
CLK
CKE
CS
tRC
COMMAND
Any
Command
Self Refresh
Exit
: “H” or “L”
Begin Self Refresh Exit
Self Refresh
Exit Command
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Self Refresh Exit (Commands Gated Off with NOP Commands)
T
T
T
T
T
T
T
T
T
m
m+1
m+2
m+3
m+4
m+5
m+6
m+7
m+8
CLK
CKE
CS
tRC
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Any
Command
Self Refresh
Exit
Begin Self Refresh Exit
Self Refresh
Exit Command
: “H” or “L”
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When
the Data Mask is high during a write cycle, the write operation is prohibited immediately (zero clock latency).
If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance
after a two clock delay, independent of CAS latency.
Data Mask Activated During a Read Cycle (Burst Length = 4, CAS Latency = 1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DOUT A
DQs
DOUT A
1
0
A two clock delay before
the DQs become Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The pur-
pose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands
between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held
high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is
still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command
occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.
Power Down Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active
Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the neces-
sary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. If a bank is acti-
vated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a
Power Down Mode Command when the device is performing a Read or Write operation causes the device to
enter Clock Suspend mode. See the following section.) Once the Power Down mode is initiated by holding
CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not per-
form any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh
period (tREF) of the device.
The Power Down mode is exited by bringing CKE high. A one clock delay after the registration of CKE high is
required for the SDRAM to exit the Power Down mode.
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Clock Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is registered low while at least
one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the inter-
nal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a one
clock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends.
While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend
mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when
Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last
valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend During a Read Cycle (Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CKE
A one clock delay to exit
the Suspend command
A one clock delay before
suspend operation starts
NOP
READ A
NOP
NOP
NOP
NOP
COMMAND
DOUT A
DOUT A
2
DOUT A
DQs
0
1
DOUT element at the DQs when the
suspend operation starts is held valid
: “H” or “L”
If Clock Suspend mode is initiated during a burst write operation, then the input data is masked and ignored
until the Clock Suspend mode is exited.
Clock Suspend During a Write Cycle (Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CKE
A one clock delay to exit
the Suspend command
A one clock delay before
suspend operation starts
NOP
WRITE A
NOP
NOP
NOP
NOP
COMMAND
DIN A
DIN A
DIN A
3
DIN A
0
DQs
1
2
: “H” or “L”
DIN is masked during the Clock Suspend Period
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Command Truth Table (Notes: 1)
CKE
Function
CS
RAS
CAS
WE
DQM A11
A10
A9 - A0
Notes
Previous Current
Cycle
H
H
H
L
Cycle
Mode Register Set
Auto (CBR) Refresh
Entry Self Refresh
Exit Self Refresh
X
L
L
L
H
L
L
L
L
L
L
L
L
L
H
X
X
X
X
X
L
L
L
L
L
H
H
X
L
X
OP Code
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
L
H
X
X
L
X
H
H
H
L
X
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
L
BS
X
2
X
L
L
H
X
L
H
L
BS
BS
BS
BS
BS
X
Row Address
2
2
2
2
2
3
Write
X
H
H
H
H
H
H
X
X
X
X
X
X
L
H
L
Column
Write with Auto-Precharge
Read
X
L
L
Column
X
L
H
H
L
Column
Read with Auto-Precharge
Burst Termination
X
L
H
X
X
X
X
X
X
X
X
Column
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Operation
X
H
X
X
X
X
X
X
X
Device Deselect
X
X
Clock Suspend/Standby Mode
Data Write/Output Enable
Data Mask/Output Disable
Power Down Mode Entry
Power Down Mode Exit
X
X
4
5
H
H
X
X
X
X
H
X
X
X
5
L
X
6, 7
6, 7
X
H
X
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. For
stacked devices: only one deck can be operated at once, except during Self Refresh.
2. Bank Select (BS), if BS = 0 then bank A is selected, if BS = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock tim-
ing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for
Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Precharge Power Down Mode. If banks are active, Active Power Down Mode is
entered. The Power Down Mode does not perform any refresh operations, therefore the device can’t remain in this mode longer
than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. If CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle.
©IBM Corporation. All rights reserved.
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08J3348.E35853
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Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Clock Enable (CKE) Truth Table
CKE
Command
WE
Current State
Action
Notes
Previous Current
CS
RAS CAS
A11 A10 - A0
Cycle
H
L
Cycle
X
X
H
L
X
X
H
H
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
1
2
2
2
2
2
H
H
H
H
H
L
X
H
H
L
Exit Self Refresh with Device Deselect
Exit Self Refresh with No Operation
ILLEGAL
L
Self Refresh
L
L
L
L
X
X
X
X
X
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
X
X
H
L
ILLEGAL
L
X
X
H
L
X
X
X
X
X
X
H
L
Maintain Self Refresh
INVALID
H
L
X
1
2
2
H
H
L
Power Down mode exit, all banks idle
ILLEGAL
Power Down
L
L
X
H
L
Maintain Power Down Mode
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
3
3
3
Refer to the Idle State section of the
Current State Truth Table
L
L
L
X
X
CBR Refresh
L
L
L
OP Code
Mode Register Set
4
3
3
3
4
All Banks Idle
H
L
X
H
L
X
X
H
L
X
X
X
H
L
Refer to the Idle State section of the
Current State Truth Table
L
L
L
L
L
L
X
X
Entry Self Refresh
Mode Register Set
Power Down
L
L
L
L
OP Code
X
X
X
X
X
X
X
X
4
5
Refer to operations in the Current
State Truth Table
H
H
X
X
X
X
X
Any State
other than
listed above
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
1. For the given Current State, CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE (tCES) must be satisfied before any command other than Exit is issued.
3. The address inputs (A11 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table
for more information.
4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Current State Truth Table (Part 1 of 4) (Notes: 1)
Command
Current State
Action
Notes
CS RAS CAS WE A11
A10 - A0
OP Code
Description
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set
Set the Mode Register
2
X
X
X
Auto or Self Refresh Start Auto or Self Refresh
2, 3
L
H
H
L
BS
Precharge
No Operation
L
H
L
BS Row Address Bank Activate
Activate the specified bank and row
Idle
Row Active
Read
H
H
H
H
X
L
BS
BS
X
Column
Write w/o Precharge ILLEGAL
Read w/o Precharge ILLEGAL
4
4
L
H
L
Column
H
H
X
L
X
X
X
Burst Termination
No Operation
No Operation
H
X
L
X
No Operation
X
Device Deselect
Mode Register Set
No Operation or Power Down
ILLEGAL
5
OP Code
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
Precharge
6
L
H
L
BS Row Address Bank Activate
ILLEGAL
4
H
H
H
H
X
L
BS
BS
X
Column
Write
Start Write; Determine if Auto-Precharge
Start Read; Determine if Auto-Precharge
No Operation
7, 8
7, 8
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
H
X
L
X
No Operation
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
Precharge Terminate Burst; Start the Precharge
L
H
H
L
BS
L
H
L
BS Row Address Bank Activate
ILLEGAL
4
H
H
H
H
X
BS
BS
X
Column
Write
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Terminate the Burst
8, 9
8, 9
L
H
L
Column
Read
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
H
X
X
Continue the Burst
X
Continue the Burst
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-
mand is being applied to.
2. Both Banks must be idle; otherwise it is an illegal action.
3. If CKE is active (high), the SDRAM will start the Auto (CBR) Refresh operation. If CKE is inactive (low), then the Self Refresh mode
is entered.
4. The Current State only refers to one of the banks. If BS selects this bank, then the action is illegal. If BS selects the bank not being
referenced by the Current State, then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low), then the Power Down mode is entered. Otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Current State Truth Table (Part 2 of 4) (Notes: 1)
Command
Current State
Action
Notes
CS RAS CAS WE A11
A10 - A0
OP Code
Description
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set
ILLEGAL
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BS Row Address Bank Activate
4
Write
H
H
H
H
X
L
BS
BS
X
Column
Write
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Terminate the Burst
8, 9
8, 9
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
H
X
L
X
Continue the Burst
X
Continue the Burst
OP Code
ILLEGAL
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
ILLEGAL
4
4
4
4
L
H
L
BS Row Address Bank Activate
ILLEGAL
Read with
Auto-
Precharge
H
H
H
H
X
L
BS
BS
X
Column
Write
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
ILLEGAL
H
X
L
X
Continue the Burst
Continue the Burst
ILLEGAL
X
OP Code
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
ILLEGAL
4
4
4
4
L
H
L
BS Row Address Bank Activate
ILLEGAL
Write with
Auto-
Precharge
H
H
H
H
X
BS
BS
X
Column
Write
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
ILLEGAL
H
X
X
Continue the Burst
Continue the Burst
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-
mand is being applied to.
2. Both Banks must be idle; otherwise it is an illegal action.
3. If CKE is active (high), the SDRAM will start the Auto (CBR) Refresh operation. If CKE is inactive (low), then the Self Refresh mode
is entered.
4. The Current State only refers to one of the banks. If BS selects this bank, then the action is illegal. If BS selects the bank not being
referenced by the Current State, then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low), then the Power Down mode is entered. Otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Current State Truth Table (Part 3 of 4) (Notes: 1)
Command
Current State
Action
Notes
CS RAS CAS WE A11
A10 - A0
OP Code
Description
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set
ILLEGAL
X
X
X
Auto or Self Refresh ILLEGAL
No Operation; Bank(s) idle after tRP
ILLEGAL
L
H
H
L
BS
Precharge
L
H
L
BS Row Address Bank Activate
4
4
4
H
H
H
H
X
L
BS
BS
X
Column
Write
ILLEGAL
Precharging
L
H
L
Column
Read
ILLEGAL
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
ILLEGAL
4
4, 10
4
L
H
L
BS Row Address Bank Activate
ILLEGAL
H
H
H
H
X
L
BS
BS
X
Column
Write
ILLEGAL
Row Activating
L
H
L
Column
Read
ILLEGAL
4
No Operation; Row Active after tRCD
No Operation; Row Active after tRCD
No Operation; Row Active after tRCD
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
ILLEGAL
4
4
9
9
L
H
L
BS Row Address Bank Activate
ILLEGAL
Write
Recovering
H
H
H
H
X
BS
BS
X
Column
Write
Start Write; Determine if Auto-Precharge
Start Read; Determine if Auto-Precharge
No Operation; Row Active after tDPL
No Operation; Row Active after tDPL
No Operation; Row Active after tDPL
L
H
L
Column
Read
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
H
X
X
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-
mand is being applied to.
2. Both Banks must be idle; otherwise it is an illegal action.
3. If CKE is active (high), the SDRAM will start the Auto (CBR) Refresh operation. If CKE is inactive (low), then the Self Refresh mode
is entered.
4. The Current State only refers to one of the banks. If BS selects this bank, then the action is illegal. If BS selects the bank not being
referenced by the Current State, then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low), then the Power Down mode is entered. Otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Current State Truth Table (Part 4 of 4) (Notes: 1)
Command
Current State
Action
Notes
CS RAS CAS WE A11
A10 - A0
OP Code
Description
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set
ILLEGAL
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
4
L
H
L
BS Row Address Bank Activate
4
Write
Recovering
with Auto-
Precharge
H
H
H
H
X
L
BS
BS
X
Column
Write
4, 9
4, 9
L
H
L
Column
Read
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
ILLEGAL
L
H
L
BS Row Address Bank Activate
ILLEGAL
H
H
H
H
X
L
BS
BS
X
Column
Write
ILLEGAL
Refreshing
L
H
L
Column
Read
ILLEGAL
No Operation; Idle after tRC
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
BS
Precharge
ILLEGAL
L
H
L
BS Row Address Bank Activate
ILLEGAL
Mode Register
Accessing
H
H
H
H
X
BS
BS
X
Column
Write
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
ILLEGAL
H
X
X
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-
mand is being applied to.
2. Both Banks must be idle; otherwise it is an illegal action.
3. If CKE is active (high), the SDRAM will start the Auto (CBR) Refresh operation. If CKE is inactive (low), then the Self Refresh mode
is entered.
4. The Current State only refers to one of the banks. If BS selects this bank, then the action is illegal. If BS selects the bank not being
referenced by the Current State, then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low), then the Power Down mode is entered. Otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN
Parameter
Power Supply Voltage
Rating
-1.0 to +4.6
-1.0 to +4.6
-1.0 to +4.6
-1.0 to +4.6
0 to +70
-55 to +125
1.0
Units
V
Notes
1
1
1
1
1
1
1
1
Power Supply Voltage for Output
Input Voltage
V
V
VOUT
TA
Output Voltage
V
°C
°C
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
TSTG
PD
W
IOUT
Short Circuit Output Current
50
mA
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Recommended DC Operating Conditions (TA= 0 to 70˚C)
Rating
Symbol
Parameter
Units
Notes
Min.
3.0
Typ.
3.3
3.3
—
Max.
3.6
VDD
VDDQ
VIH
Supply Voltage
V
V
V
V
1
1
1
1
Supply Voltage for Output
Input High Voltage
3.0
3.6
2.0
VDD + 0.3
0.8
VIL
Input Low Voltage
-0.3
—
1. All voltages referenced to VSS and VSSQ.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Capacitance (T = 25°C, f=1MHz, V = 3.3V ± 0.3V)
A
DD
Symbol
CI1
Parameter
Min.
2.0
2.0
2.0
Typ
2.7
2.7
4.0
Max.
4.0
Units
pF
Notes
Input Capacitance (A0 - A11)
1
1
1
CI2
Input Capacitance (RAS, CAS, WE, CS, CLK, CKE, DQM)
Output Capacitance (DQ0 - DQ15)
4.0
pF
CO
5.0
pF
1. Multiply given planar values by 2 for 2-High stacked device.
DC Electrical Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V)
A
DD
Symbol
Parameter
Min.
Max.
+1
Units
Input Leakage Current, any input
II(L)
µA
-1
-1
(0.0V ≤ VIN ≤ 3.6V), All Other Pins Not Under Test = 0V
Output Leakage Current
IO(L)
VOH
VOL
µA
V
+1
VDDQ
0.4
(DOUT is disabled, 0.0V ≤ VOUT ≤ 3.6V)
Output Level (TTL)
2.4
0.0
Output “H” Level Voltage (IOUT = -2.0mA)
Output Level (TTL)
V
Output “L” Level Voltage (IOUT = +2.0mA)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Standby and Refresh Currents (T = 0 to +70˚C, V = 3.3V ± 0.3V) (Notes: 1)
A
DD
Organization
Parameter
Symbol
Test Condition
Units
Notes
2
x4
3
x8
3
x16
3
ICC1P
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = Infinity
mA
mA
Precharge Standby Current in
Power Down Mode
I
CC1PS
2
2
2
CKE ≥ VIH(min), tCK = 15ns
CS=High
2
I
CC1N
25
10
25
10
25
10
mA
mA
Input Change every 30ns
Precharge Standby Current in
Non-Power Down Mode
CKE ≥ VIH(min), tCK = Infinity
ICC1NS
2
No Input Change
ICC2
P
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = Infinity
3
2
3
2
3
2
mA
mA
3, 11
4, 11
Active Standby Current in
Power Down Mode
ICC2PS
CKE ≥ VIH(min), tCK = 15ns
CS=High
5
I
CC2N
25
15
85
25
15
85
25
15
85
mA
mA
mA
Input Change every 30ns
Active Standby Current in
Non-Power Down Mode
CKE ≥ VIH(min), tCK = Infinity
I
CC2NS
6, 11
No Input Change
CAS Latency = 1
tRC ≥ tRC(min)
-10
-80
-360
-10
110
—
110
90
110
—
CAS Latency = 2
RC ≥ tRC(min)
t
7, 8, 9,
10
mA
ICC3
Auto (CBR) Refresh Current
90
140
—
90
90
140
—
-80
140
140
110
2
CAS Latency = 3
-360
-10
tRC ≥ tRC(min)
mA
110
2
110
2
-80/-10
-360
mA
mA
2
ICC4
CKE ≤ 0.2V
Self Refresh Current
—
2
—
1. For stacked devices: only one deck may be active at a time, except during self refresh.
2. For stacked devices: multiply the given planar (individual deck) values by 2.
3. For stacked devices: this is the active portion only.The total stack current includes the Precharge Standby current of the inactive
deck (ICC2P + ICC1P).
4. For stacked devices: this is the active portion only.The total stack current includes the Precharge Standby current of the inactive
deck (ICC2PS + ICC1PS).
5. For stacked devices: this is the active portion only.The total stack current includes the Precharge Standby current of the inactive
deck (ICC2N + ICC1N).
6. For stacked devices: this is the active portion only.The total stack current includes the Precharge Standby current of the inactive
deck (ICC2NS+ ICC1NS).
7. For stacked devices: this is the active portion only.The total stack current includes the Precharge Standby current of the inactive
deck (ICC3 + ICC1N).
8. The specified values are valid when addresses are changed no more than once during tCK(min).
9. The specified values are valid when No Operation commands are registered on every rising clock edge during tRC(min).
10. The specified values are valid when data inputs (DQs) are stable during tRC(min).
11. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Operating Currents (T = 0 to +70˚C, V = 3.3V ± 0.3V)
A
DD
Organization
X8
CAS
Speed
Sort
tRC(min)
Symbol
Parameter
Test Condition
Units Notes
mA
Latency
X4
95
X16
95
CL=1
CL=2
90 ns
72 ns
-10
-80
95
130
—
130
105
105
155
160
125
75
135
—
90 ns
-360
-10
mA
t
t
RC = tRC(min)
CK ≥ tCK(min)
O = 0mA
Operating Current
Burst Length = 1
ICC5
90 ns
105
155
—
110
160
—
1, 2, 3
I
72 ns
-80
CL=3
CL=1
CL=2
70 ns
-360
-10
mA
mA
90 ns
125
75
130
80
120 ns
84 ns
-10
-80
125
—
125
100
100
155
155
125
65
130
—
105 ns
105 ns
80 ns
-360
-10
mA
t
t
RC = tRC(min)
CK ≥ tCK(min)
O = 0mA
Operating Current
Burst Length = 2
1, 2, 3,
4
ICC6
ICC7
ICC8
100
155
—
105
160
—
I
-80
CL=3
CL=1
CL=2
80 ns
-360
-10
mA
mA
100 ns
180 ns
108 ns
135 ns
135 ns
96 ns
125
65
130
70
-10
-80
115
—
120
95
125
—
-360
-10
mA
t
t
RC = tRC(min)
CK ≥ tCK(min)
O = 0mA
Operating Current
Burst Length = 4
1, 2, 3,
4
90
95
100
160
—
I
-80
150
—
155
150
125
60
CL=3
CL=1
CL=2
100 ns
120 ns
300 ns
156 ns
195 ns
195 ns
128 ns
140 ns
160 ns
-360
-10
mA
mA
120
55
130
65
-10
-80
105
—
110
90
120
—
-360
-10
mA
t
t
RC = tRC(min)
CK ≥ tCK(min)
O = 0mA
Operating Current
Burst Length = 8
1, 2, 3,
4
85
90
100
165
—
I
-80
150
—
155
145
125
CL=3
-360
-10
mA
120
135
1. The specified values are obtained with the output open.
2. The specified values are valid when addresses and DQs are changed no more than once during tCK(min).
3. For stacked devices: this is the active portion only.The total stack current includes the Precharge Standby current of the inactive
deck (Operating Current+ ICC1N).
4. The specified values are obtained when the programmed burst length is executed to completion without interruption by a subse-
quent burst Read or Write cycle.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Operating Currents (T = 0 to +70˚C, V = 3.3V ± 0.3V)
A
DD
Organization
Units Notes
CAS
Speed
Sort
tRC(min)
Symbol
Parameter
Test Condition
Latency
X4
40
X8
X16
tRC = ∞
tCK=30 ns
CL=1
CL=2
-10
-80
45
55
mA
tRC = ∞
tCK=12 ns
90
—
95
75
110
—
tRC = ∞
tCK=15 ns
-360
-10
mA
t
RC = Infinity
CK ≥ tCK(min)
O = 0mA
Operating Current
Burst Length = Full
Page
1, 2, 3,
4
tRC = ∞
tCK=15 ns
ICC9
t
70
75
90
I
tRC = ∞
tCK=8 ns
-80
125
—
130
105
105
85
170
—
tRC = ∞
tCK=10 ns
CL=3
CL=1
CL=2
-360
-10
mA
mA
mA
tRC = ∞
tCK=10 ns
100
85
135
90
tRC = ∞
tCK=30 ns
-10
tRC = ∞
tCK=12ns
-80
165
—
165
130
130
220
175
175
175
—
Operating Current
1-N Rule
tRC = ∞
tCK=15 ns
-360
-10
t
RC = Infinity
tRC = ∞
tCK=15 ns
(Continuous
ICC10
t
CK ≥ tCK(min)
130
220
—
140
240
—
1, 2, 3
Read/Write cycles
with new column
address registered
each clock cycle)
IO = 0mA
tRC = ∞
tCK=8 ns
-80
tRC = ∞
tCK=10 ns
CL=3
-360
-10
mA
tRC = ∞
tCK=10 ns
175
190
1. The specified values are obtained with the output open.
2. The specified values are valid when addresses and DQs are changed no more than once during tCK(min).
3. For stacked devices: this is the active portion only.The total stack current includes the Precharge Standby current of the inactive
deck (Operating Current+ ICC1N).
4. The specified values are obtained when the programmed burst length is executed to completion without interruption by a subse-
quent burst Read or Write cycle.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
AC Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V)
A
DD
1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum of
two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. The Transition time is measured between VIH and VIL (or between VIL and VIH).
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point.
5. AC measurements assume tT=1.0 ns.
tT
VIH
1.4V
Clock
VIL
Vtt=1.4V
tSETUP
50Ω
tHOLD
Output
Z = 50Ω
o
50pF
1.4V
Input
AC Output Load Circuit
tOH
tAC
tLZ
1.4V
Output
Clock and Clock Enable Parameters
-80
-360
Max.
100MHz 10 100MHz ns
-10
Symbol
Parameter
Units Notes
Min.
Max.
Min.
10
15
—
—
—
—
3
Min. Max.
tCK3
tCK2
tCK1
tAC3
tAC2
tAC1
tCKH
tCKL
tCES
tCEH
tCESP
tT
Clock Cycle Time,CAS Latency=3
Clock Cycle Time,CAS Latency=2
Clock Cycle Time,CAS Latency=1
Clock Access Time,CAS Latency=3
Clock Access Time,CAS Latency=2
Clock Access Time,CAS Latency=1
Clock High Pulse Width
8
12
—
—
—
—
3
125MHz
83MHz
—
66MHz
—
15
30
—
—
—
3.5
3.5
3
66MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33MHz
8
6
5.5
9
1, 2
1, 2
1, 2
3
7
9
—
—
27
—
—
—
Clock Low Pulse Width
3
—
3
—
—
3
Clock Enable Set-up Time
2
—
2
—
—
Clock Enable Hold Time
1
—
1
—
1
—
CKE Set-up Time (Power down mode)
Transition Time (Rise and Fall)
2
—
2
—
3
—
1
30
1
30
1
30
1. Access time is measured at 1.4V. See AC Characteristics: notes 1,2,3,4,5 and load circuit.
2. Access time is measured assuming a clock rise time of 1 ns. If clock rise time is longer than 1 ns, then (trise/2-0.5)ns should be
added to the parameter.
3. Assumes clock rise and fall times are equal to 1 ns. If rise or fall time exceeds 1 ns, then other AC parameters under consider-
ation should be compensated by an additional [(trise+tfall)/2-1]ns.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Common Parameters
-80
-360
-10
Symbol
Parameter
Units
Min.
2
Max.
—
Min.
2
Max.
—
Min.
3
Max.
—
tCS
tCH
Command Setup Time
ns
ns
Command Hold Time
1
—
1
—
1
—
tAS
Address and Bank Select Set-up Time
Address and Bank Select Hold Time
RAS to CAS Delay
2
—
2
—
3
—
ns
tAH
1
—
1
—
1
—
ns
tRCD
tRC
tRAS
tRP
tRRD
tCCD
24
72
48
24
16
1
—
20
70
50
20
20
1
—
30
90
60
30
20
1
—
ns
Bank Cycle Time
120K
120K
—
120K
120K
—
120K
120K
—
ns
Active Command Period
Precharge Time
ns
ns
Bank to Bank Delay Time
CAS to CAS Delay Time (Same Bank)
—
—
—
ns
—
—
—
CLK
Refresh Cycle
-80
-360
-10
Symbol
Parameter
Units Notes
Min.
—
Max.
Min.
Max.
Min.
—
Max.
tREF
Refresh Period
Self Refresh Exit Time
64
—
64
64
ms
ns
1, 2
3
10ns +
tRC
10ns +
10ns +
tRC
tSREX
—
—
—
tRC
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-
up” the device.
3. Self Refresh Exit is an asynchronous operation. Self refresh exit is accomplished by starting the clock (CLK) and then asserting
CKE high. During the exit time (tSREX), no commands may be issued until tRC is satisfied and CKE must remain high. It is recom-
mended to hold CS high during the self refresh exit time, but NOP commands may be issued with each rising clock edge during this
period as an alternative. To prevent erroneous exit of self refresh operation, a glitch suppressor circuit is incorporated into the CKE
receiver. If CKE is asserted high (system noise) for less than 10ns (approximately), then the device will not exit self refresh opera-
tion.
Read Cycle
-80
-360
Max.
-10
Symbol
Parameter
Units Notes
Min.
2.5
2.5
2.5
2.5
—
Max.
—
—
6
Min.
3
Min.
3
Max.
—
—
8
tOH
tLZ
Data Out Hold Time
—
—
5.5
8
ns
ns
1
Data Out to Low Impedance Time
2.5
2.5
2.5
—
3
tHZ3
tHZ2
tHZ1
tDQZ
Data Out to High Impedance Time,CL= 3
Data Out to High Impedance Time,CL= 2
Data Out to High Impedance Time,CL= 1
DQM Data Out Disable Latency
3
ns
2
2
2
7
3
8
ns
—
—
—
—
3
15
—
ns
2
2
2
CLK
1. -360: 50pf load.
2. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Write Cycle
-80
-360
-10
Symbol
Parameter
Units Notes
Min.
2
Max.
—
Min.
2
Max.
—
Min.
3
Max.
—
tDS
tDH
tDPL
tDQW
Data In Set-up Time
Data In Hold Time
ns
ns
1
—
1
—
1
—
Data Input to Precharge
DQM Write Mask Latency
8
—
15
0
—
10
0
—
ns
0
—
—
—
CLK
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Clock Frequency and Latency
Symbol
fCK
tCK
Parameter
-80
-360
-10
66
15
2
Units
MHz
ns
Clock Frequency
Clock Cycle Time
CAS Latency
125
8
83
12
2
100
10
3
66
15
2
100
10
3
33
30
1
tAA
3
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
tRCD
tRL
RAS to CAS Delay
3
2
2
2
3
2
1
RAS Latency
6
4
5
4
6
4
2
tRC
Bank Cycle Time
9
6
7
6
9
6
3
tRAS
tRP
Minimum Bank Active Time
Precharge Time
6
4
5
4
6
4
2
3
2
2
2
3
2
1
tDPL
tDAL
tRRD
tCCD
tWL
Data In to Precharge
Data In to Active/Refresh
Bank to Bank Delay Time
CAS to CAS Delay Time
Write Latency
1
1
2
1
1
1
1
4
3
4
3
4
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
tDQW
tDQZ
tCSL
DQM Write Mask Latency
DQM Data Disable Latency
Clock Suspend Latency
0
0
0
0
0
0
0
2
2
2
2
2
2
2
1
1
1
1
1
1
1
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Timing Diagrams
Page
AC Parameters for Write Timing...............................................................................................................55
AC Parameters for Read Timing...............................................................................................................56
Mode Register Set ....................................................................................................................................57
Power on Sequence and Auto Refresh (CBR)..........................................................................................58
Clock Suspension During a Burst Read (Using CKE)
CAS Latency = 1...............................................................................................................59
CAS Latency = 2...............................................................................................................60
CAS Latency = 3, t
= 3................................................................................................61
RCD
Clock Suspension During a Burst Write (Using CKE)
CAS Latency = 1...............................................................................................................62
CAS Latency = 2...............................................................................................................63
CAS Latency = 3, t = 3................................................................................................64
RCD
Power Down Mode and Clock Suspend ...................................................................................................65
Auto Refresh (CBR)..................................................................................................................................66
Self Refresh (Entry and Exit) ....................................................................................................................67
Random Column Read (Page within same Bank)
CAS Latency = 1...............................................................................................................68
CAS Latency = 2...............................................................................................................69
CAS Latency = 3, t
CAS Latency = 3, t
, t = 3.........................................................................................70
RCD RP
, t = 2.........................................................................................71
RCD RP
Random Column Write (Page within same Bank)
CAS Latency = 1...............................................................................................................72
CAS Latency = 2...............................................................................................................73
CAS Latency = 3, t
CAS Latency = 3, t
, t = 3, t
= 1 .........................................................................74
= 2 ..........................................................................75
RCD RP
DPL
, t = 2, t
RCD RP
DPL
Random Row Read (Interleaving Banks)
CAS Latency = 1...............................................................................................................76
CAS Latency = 2...............................................................................................................77
CAS Latency = 3, t
, t = 3.........................................................................................78
RCD RP
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Timing Diagrams
Page
Random Row Write (Interleaving Banks)
CAS Latency = 1............................................................................................................... 79
CAS Latency = 2............................................................................................................... 80
CAS Latency = 3, t
, t = 3 ........................................................................................ 81
RCD RP
Read And Write Cycle
CAS Latency = 1............................................................................................................... 82
CAS Latency = 2............................................................................................................... 83
CAS Latency = 3, t
, t = 3 ........................................................................................ 84
RCD RP
Interleaved Column Read Cycle
CAS Latency = 1............................................................................................................... 85
CAS Latency = 2............................................................................................................... 86
CAS Latency = 3, t
, t = 3 ........................................................................................ 87
RCD RP
Interleaved Column Write Cycle
CAS Latency = 1............................................................................................................... 88
CAS Latency = 2............................................................................................................... 89
CAS Latency = 3, t
CAS Latency = 3, t
, t = 3, t
= 1.......................................................................... 90
= 2.......................................................................... 91
RCD RP
DPL
DPL
, t = 2, t
RCD RP
Auto-Precharge after a Read Burst
CAS Latency = 1............................................................................................................... 92
CAS Latency = 2............................................................................................................... 93
CAS Latency = 3, t
, t = 3 ........................................................................................ 94
RCD RP
Auto-Precharge after a Write Burst
CAS Latency = 1............................................................................................................... 95
CAS Latency = 2............................................................................................................... 96
CAS Latency = 3, t
, t = 3 ........................................................................................ 97
RCD RP
Full Page Read Cycle
CAS Latency = 1............................................................................................................... 98
CAS Latency = 2............................................................................................................... 99
CAS Latency = 3, t
, t = 3 ........................................................................................ 100
RCD RP
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Timing Diagrams
Page
Full Page Write Cycle
CAS Latency = 1...............................................................................................................101
CAS Latency = 2...............................................................................................................102
CAS Latency = 3, t
, t = 3.........................................................................................103
RCD RP
Byte Write Operation.................................................................................................................................104
Burst Read and Single Write Operation....................................................................................................105
Full Page Burst Read and Single Write Operation....................................................................................106
Random Row Read (Interleaving Banks)..................................................................................................107
Full Page Random Column Read .............................................................................................................108
Full Page Random Column Write .............................................................................................................109
Precharge Termination of a Burst
CAS Latency = 1...............................................................................................................110
CAS Latency = 2...............................................................................................................111
CAS Latency = 3, t
, t = 3.........................................................................................112
RCD RP
CS Function (Only CS signal needs to be asserted at minimum rate)......................................................113
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Burst Length = 4, CAS Latency = 2
AC Parameters for Write Timing
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
tCKH
tCKL
tCS
CKE
CS
Begin Auto-Precharge
Bank A
Begin Auto-Precharge
Bank B
tCES
tCEH
tCH
RAS
CAS
WE
A11(BS)
tAH
RAx
RBx
RBx
RAy
RAz
RAz
RBy
RBy
A10
tAS
RAx
CAx
CBx
RAy
CAy
A0 - A9
DQM
tRCD
tDAL
tDS
tDPL
tRC
tRP
tRRD
tDH
Hi-Z
Ax0
Ax1
Ax2
Ax3
DQ
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
Activate
Write with
Activate
Write with
Activate
Write
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank A
Command Auto-Precharge Command Auto-Precharge Command
Bank A
Command
Bank A
Bank B
Command
Bank B
Bank A
Burst Length = 2, CAS Latency = 2
AC Parameters for Read Timing
T0
T1
T7
T2
T3
T4
T5
T6
T8
T9
T10
T12
T11
T13
CLK
tCK2
tCS
tCKH tCKL
Begin Auto-
Precharge
Bank B
CKE
tCEH
tCES
tCH
CS
RAS
CAS
WE
A11(BS)
tAH
RAx
RBx
RAy
RAy
A10
tAS
RAx
CAx
RBx
CBx
A0 - A9
DQM
tRRD
tRAS
tRC
tAC2
tLZ
tOH
tRP
tHZ
tRCD
tHZ
Hi-Z
Ax0
Ax1
Bx0
Bx1
DQ
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Precharge
Command
Bank A
Auto-Precharge
Command
Bank B
Mode Register Set
CAS Latency = 2
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
2 Clock min.
RAS
CAS
WE
A11(BS)
A10
Address Key
A0 - A9
DQM
DQ
tRP
Hi-Z
Mode Register
Any
Precharge
Command
All Banks
Set Command Command
Power on Sequence and Auto Refresh (CBR)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High level
is required
CKE
CS
2 Clock min.
Minimum of 2 Refresh Cycles are required
RAS
CAS
WE
A11(BS)
A10
Address Key
A0 - A9
DQM
DQ
tRP
tRC
Hi-Z
Mode Register
Set Command
Precharge
Command
All Banks
2nd Auto Refresh
Command
Any
Command
1st Auto Refresh
Command
Inputs must be
stable for 100µs
Burst Length = 4, CAS Latency = 1
Clock Suspension During Burst Read (Using CKE) (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
RAx
CAx
A0 - A9
DQM
DQ
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Read
Command
Bank A
Burst Length = 4, CAS Latency = 2
Clock Suspension During Burst Read (Using CKE) (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
RAx
CAx
A0 - A9
DQM
DQ
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Burst Length = 4, CAS Latency = 3, tRCD = 3
Clock Suspension During Burst Read (Using CKE) (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
RAx
CAx
A0 - A9
DQM
DQ
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Read command may be issued 1 clock sooner for -360 (tRCD = 2 clocks)
Burst Length = 4, CAS Latency = 1
Clock Suspension During Burst Write (Using CKE) (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
RAx
CAx
A0 - A9
DQM
DQ
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Write
Command
Bank A
Burst Length = 4, CAS Latency = 2
Clock Suspension During Burst Write (Using CKE) (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAx
A10
CAx
A0 - A9
DQM
DQ
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Write
Command
Bank A
Burst Length = 4, CAS Latency = 3, tRCD = 3
Clock Suspension During Burst Write (Using CKE) (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAx
A10
CAx
A0 - A9
DQM
DQ
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Write
Command
Bank A
Write command may be issued 1 clock sooner for -360 (tRCD = 2 clocks)
Burst Length = 4, CAS Latency = 2
Power Down Mode and Clock Suspend
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
tCESP
tCESP
CKE
CS
VALID
RAS
CAS
WE
A11(BS)
RAx
A10
RAx
CAx
A0 - A9
DQM
DQ
tHZ
Hi-Z
Ax0 Ax1
Ax2
Ax3
Precharge
Command
Bank A
Read
Command
Bank A
ACTIVE
STANDBY
Power Down
Mode Exit
Activate
Command
Bank A
Clock Suspension
Start
Clock Suspension
End
Power Down
Mode Entry
PRECHARGE
STANDBY
Any
Command
Clock Suspension
Mode Entry
Clock Suspension
Mode Exit
Burst Length = 4, CAS Latency = 2
Auto Refresh (CBR)
T0
T1
T7
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAx
A10
CAx
A0 - A9
tRP
tRC
tRC
DQM
DQ
Hi-Z
Ax0 Ax1 Ax2 Ax3
Auto Refresh
Command
Auto Refresh
Command
Read
Command
Bank A
Precharge
Command
All Banks
Activate
Command
Bank A
Self Refresh (Entry and Exit) ***Note: The CLK signal must be reestablished prior to CKE returning high.
T0
T1
T2
T3
T4
Tm
Tm+1
Tm+3
Tm+8
Tm+12
Tm+9 Tm+10 Tm+11 Tm+13 Tm+14 Tm+15
Tm+2
Tm+4 Tm+5 Tm+6 Tm+7
CLK
CKE
CS
tSREX
RAS
CAS
WE
A11(BS)
A10
A0 - A9
DQM
DQ
tRC
Hi-Z
Self Refresh
Entry
Begin Self Refresh Exit
All Banks
must be idle
Any Command
Self Refresh
Exit
Self Refresh
Exit Command
Burst Length = 4, CAS Latency = 1
Random Column Read (Page within same Bank) (1 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RAw
RAz
RAz
A10
RAw
CAw
CAx
CAy
CAz
A0 - A9
DQM
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Az1
Az2
Az3
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Burst Length = 4, CAS Latency = 2
Random Column Read (Page within same Bank) (2 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAw
RAz
RAz
A10
CAw
CAx
CAy
CAz
RAw
A0 - A9
DQM
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Az1
Az2
Az3
Read
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Burst Length = 4, CAS Latency = 3, tRCD, tRP = 3
Random Column Read (Page within same Bank) (3 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAw
RAz
RAz
A10
CAw
CAx
CAy
CAz
RAw
A0 - A9
DQM
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Read
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Burst Length = 4, CAS Latency = 3, tRCD, tRP = 2
Random Column Read (Page within same Bank) (4 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAw
RAz
RAz
A10
CAw
CAx
CAy
CAz
RAw
A0 - A9
DQM
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Az1
Read
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Burst Length = 4, CAS Latency = 1
Random Column Write (Page within same Bank) (1 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RBw
RBz
RBz
A10
RBw
CBw
CBx
CBy
CBz
A0 - A9
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Burst Length = 4, CAS Latency = 2
Random Column Write (Page within same Bank) (2 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RBw
RBz
A10
RBw
CBw
CBx
CBy
RBz
CBz
A0 - A9
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Burst Length = 4, CAS Latency = 3, tRCD, tRP= 3, tDPL = 1
Random Column Write (Page within same Bank) (3 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RBw
RBz
A10
RBw
CBw
CBx
CBy
RBz
CBz
A0 - A9
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Random Column Write (Page within same Bank) (4 of 4)
Burst Length = 4, CAS Latency = 3, tRCD , tRP = 2, tDPL = 2
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RBw
RBz
A10
RBw
CBw
CBx
CBy
RBz
CBz
A0 - A9
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Burst Length = 8, CAS Latency = 1
Random Row Read (Interleaving Banks) (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
High
CKE
CS
RAS
CAS
WE
A11(BS)
RBx
RAx
RAx
RBy
A10
RBx
CBx
CAx
RBy
CBy
A0 - A9
DQM
DQ
tRCD tAC1
tRP
Hi-Z
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
By2
Read
Command
Bank B
Precharge
Command
Bank A
Activate
Precharge
Command
Bank B
Activate
Command
Bank B
Command
Bank A
Activate
Read
Read
Command
Bank B
Command
Bank B
Command
Bank A
Burst Length = 8, CAS Latency = 2
Random Row Read (Interleaving Banks) (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAx
RBx
RBy
RBy
A10
CAx
CBx
CBy
RBx
A0 - A9
DQM
DQ
tRCD
tRP
tAC2
Hi-Z
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
Read
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Burst Length = 8, CAS Latency = 3, tRCD , tRP = 3
Random Row Read (Interleaving Banks) (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAx
RBx
RBy
RBy
A10
CBx
CAx
CBy
RBx
A0 - A9
DQM
DQ
tAC3
tRCD
tRP
Hi-Z
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Burst Length = 8, CAS Latency = 1
Random Row Write (Interleaving Banks) (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RAy
RAy
A10
RAx
CAx
CBx
CAy
A0 - A9
DQM
DQ
tRCD
tRP
tDPL
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7
DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Burst Length = 8, CAS Latency = 2
Random Row Write (Interleaving Banks) (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RAy
RAy
A10
RAx
CAX
CBx
CAy
A0 - A9
DQM
DQ
tRCD
tDPL
tDPL
tRP
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Write
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Burst Length = 8, CAS Latency = 3, tRCD , tRP = 3
Random Row Write (Interleaving Banks) (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RAy
RAy
A10
RAx
CAX
CAy
CBx
A0 - A9
DQM
DQ
tRCD
tDPL
tRP
tDPL
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Burst Length = 4, CAS Latency = 1
Read and Write Cycle (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
CAy
CAz
RAx
CAx
A0 - A9
DQM
DQ
Hi-Z
Ax0
Ax1 Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Write
Command
Bank A
Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
The Write Data
is Masked with a
Zero Clock
Activate
Command
Bank A
Latency
Latency
Read
Command
Bank A
Burst Length = 4, CAS Latency = 2
Read and Write Cycle (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
RAx
CAx
CAy
CAz
A0 - A9
DQM
DQ
Hi-Z
DAy0 DAy1
DAy3
Az0
Az1
Az3
Ax0
Ax1 Ax2
Ax3
Read
Command
Bank A
Write
Command
Bank A
Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
The Write Data
is Masked with a
Zero Clock
Activate
Command
Bank A
Latency
Latency
Read and Write Cycle (3 of 3)
Burst Length = 4, CAS Latency = 3, tRCD, tRP = 3
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
RAx
CAx
CAy
CAz
A0 - A9
DQM
DQ
Hi-Z
Ax0
Ax1 Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Read
Command
Bank A
Write
Command
Bank A
Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
The Write Data
is Masked with a
Zero Clock
Activate
Command
Bank A
Latency
Latency
Burst Length = 4, CAS Latency = 1
Interleaved Column Read Cycle (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBw
RBw
A10
RAx
CAx
CBw
CBx
CBy
CAy
CBz
A0 - A9
DQM
DQ
tRCD tAC1
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bw0 Bw1 Bx0
Bx1
By0
By1
Ay0
Ay1
Bz0
Bz1
Bz2
Bz3
Activate
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Burst Length = 4, CAS Latency = 2
Interleaved Column Read Cycle (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBw
RBw
A10
CBw
CBx
CBy
CBz
RAx
CAx
CAy
A0 - A9
DQM
DQ
tRCD
tAC2
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bw0 Bw1 Bx0
Bx1
By0
By1
Ay0
Ay1
Bz0
Bz1
Bz2
Bz3
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank A
Burst Length = 4, CAS Latency = 3, tRCD, tRP = 3
Interleaved Column Read Cycle (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
A10
RAx
CAx
CBx
CBy
CBz
CAy
A0 - A9
DQM
DQ
tRCD
tAC3
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
By0
By1
Bz0
Bz1
Ay0
Ay1
Ay2
Ay3
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Burst Length = 4, CAS Latency = 1
Interleaved Column Write Cycle (1 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBw
RBw
A10
RAx
CAx
CBw
CBx
CBy
CAy
CBz
A0 - A9
DQM
DQ
tRP
tDPL
tRCD
tRRD
tRP
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1
DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Write
Command
Bank A
Burst Length = 4, CAS Latency = 2
Interleaved Column Write Cycle (2 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBw
RBw
A10
RAx
CAx
CBw
CBx
CBy
CAy
CBz
A0 - A9
DQM
DQ
tRP
tDPL
tRP
tRCD
tRRD
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Interleaved Column Write Cycle (3 of 4)
Burst Length = 4, CAS Latency = 3, tRCD , tRP = 3, tDPL = 1
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBw
RBw
A10
RAx
CAx
CBw
CBx
CBy
CAy
CBz
A0 - A9
DQM
DQ
tRP
tRCD
tDPL
tRRD
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Write
Command
Bank A
Burst Length = 4, CAS Latency = 3, tRCD , tRP = 2, tDPL = 2
Interleaved Column Write Cycle (4 of 4)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBw
RBw
A10
RAx
CAx
CBw
CBx
CBy
CAy
CBz
A0 - A9
DQM
DQ
tDPL
tRP
tRCD
tRRD
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Write
Command
Bank A
Burst Length = 4, CAS Latency = 1
Auto-Precharge after Read Burst (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
High
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank A
Start Auto-Precharge
Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBy
RBz
RBz
A10
RAx
CAx
CBx
CAy
RBy
CBy
CBz
A0 - A9
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3
Bz0
Bz1
Bz2
Bz3
Activate
Activate
Activate
Command
Bank B
Read with
Activate
Command
Bank A
Command
Bank B
Command
Bank B
Auto-Precharge
Command
Bank B
Read with
Read with
Auto-Precharge
Command
Read with
Auto-Precharge
Command
Bank B
Read
Command
Bank A
Auto-Precharge
Command
Bank B
Bank A
Burst Length = 4, CAS Latency = 2
Auto-Precharge after Read Burst (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank A
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank A
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBy
RAz
A10
CAx
CBx
CAy
CBy
CAz
RAx
RBy
RAz
A0 - A9
DQM
DQ
Hi-Z
Az0
Az1
Az2
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3
Read with
Read with
Read with
Read with
Read
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank A
Auto-Precharge
Command
Bank B
Auto-Precharge
Command
Bank A
Auto-Precharge
Command
Bank B
Auto-Precharge
Command
Bank A
Burst Length = 4, CAS Latency = 3, tRCD , tRP = 3
Auto-Precharge after Read Burst (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank A
Start Auto-Precharge
Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
RBx
RBx
RBy
RAx
A10
CAx
CBx
CAy
RBy
CBy
RAx
A0 - A9
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3
Activate
Activate
Command
Bank B
Read with
Read with
Activate
Command
Bank A
Command
Bank B
Auto-Precharge
Command
Bank B
Auto-Precharge
Command
Bank B
Read with
Auto-Precharge
Command
Read
Command
Bank A
Bank A
Burst Length = 4, CAS Latency = 1
Auto-Precharge after Write Burst (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
Start Auto-
Precharge
Bank A
High
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank A
Start Auto-Precharge
Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBy
RAz
A10
RAx
CAx
CBx
CAy
RBy
CBy
RAz
CAz
A0 - A9
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3
DAz0 DAz1 DAz2 DAz3
Activate
Activate
Command
Bank A
Write with
Auto-Precharge
Command
Write with
Auto-Precharge
Command
Activate
Command
Bank A
Activate
Command
Bank B
Command
Bank B
Write with
Write with
Auto-Precharge
Command
Bank B
Bank B
Auto-Precharge
Command
Bank A
Write
Command
Bank A
Bank A
Burst Length = 4, CAS Latency = 2
Auto-Precharge after Write Burst (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
Start Auto
Precharge
Bank A
High
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank A
Start Auto-Precharge
Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
RBx
RBx
RBy
RAx
RAz
A10
CAx
CBx
CAy
RBy
CBy
CAz
RAx
RAz
A0 - A9
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3
Write with
Auto-Precharge
Command
Write with
Auto-Precharge
Command
Write with
Auto-Precharge
Command
Write with
Auto-Precharge
Command
Write
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank A
Bank B
Bank A
Bank B
Bank A
Burst Length = 4, CAS Latency = 3, tRCD , tRP = 3
Auto-Precharge after Write Burst (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
Start Auto-Precharge
Bank B
Start Auto-Precharge
Bank A
Start Auto-
CKE
CS
Precharge
Bank B
RAS
CAS
WE
A11(BS)
RBx
RBx
RBy
RBy
RAx
A10
CAx
CBx
CAy
CBy
RAx
A0 - A9
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Write with
Auto-Precharge
Command
Write with
Auto-Precharge
Command
Write with
Auto-Precharge
Command
Activate
Command
Bank B
Activate
Command
Bank A
Bank B
Bank A
Bank B
Write
Command
Bank A
Burst Length = Full Page, CAS Latency = 1
Full Page Read Cycle (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBy
RBy
A10
RAx
CAx
RBx
CBx
A0 - A9
DQM
DQ
tRP
tRRD
Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7
Page Length:
Precharge
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
2Mb x 4I/O x 2 Banks = 1024
1Mb x 8I/O x 2 Banks = 512
512kb x 16I/O x 2 Banks = 256
Activate
Command
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Activate
Command
Bank B
Read
Command
Bank A
Burst Stop
Command
Burst Length = Full Page, CAS Latency = 2
Full Page Read Cycle (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBy
RBy
A10
RAx
CAx
CBx
A0 - A9
DQM
DQ
tRP
Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6
Read
Full Page burst operation does not
Command
Bank B
Precharge
Command
Bank B
Read
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Burst Stop
Command
Burst Length = Full Page, CAS Latency = 3, tRCD, tRP = 3
Full Page Read Cycle (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBy
RBy
A10
RAx
CAx
CBx
A0 - A9
DQM
DQ
tRP
Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Full Page burst operation does not
terminate when the length is
satisfied; the burst counter
increments and continues
bursting beginning with
Read
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
the starting address.
Burst Stop
Command
Burst Length = Full Page, CAS Latency = 1
Full Page Write Cycle (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBy
RBy
A10
RAx
CAx
RBx
CBx
A0 - A9
DQM
DQ
Hi-Z
DAx DAx+1 DAx+2 DAx+DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 DBx+7
Page Length:
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
2Mb x 4I/O x 2 Banks = 1024
1Mb x 8I/O x 2 Banks = 512
512kb x 16I/O x 2 Banks = 256
Data is ignored.
Activate
Command
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Activate
Command
Bank B
Write
Command
Bank A
Burst Stop
Command
Burst Length = Full Page, CAS Latency = 2
Full Page Write Cycle (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBy
RBy
A10
RAx
CAx
CBx
A0 - A9
DQM
DQ
Hi-Z
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Data is ignored.
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Burst Stop
Command
Burst Length = Full Page, CAS Latency = 3, tRCD, tRP = 3
Full Page Write Cycle (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBy
RBy
A10
RAx
CAx
CBx
A0 - A9
DQM
DQ
Data is ignored.
Hi-Z
DAx DAx+1 DAx+2 DAx+DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Activate
Command
Bank B
Write
Precharge
Command
Bank B
Command Full Page burst operation does not
Bank B terminate when the length is
satisfied; the burst counter
increments and continues
bursting beginning with
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Burst Stop
Command
the starting address.
Burst Length = 4, CAS Latency = 2
Byte Write Operation
T0
T1
T7
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
A10
CAx
CAy
CAz
RAx
A0 - A9
LDQM
UDQM
Hi-Z
Hi-Z
DQ0 - DQ7
DQ8 - DQ15
Ax0
Ax1
Ax2
DAy1 DAy2
Az1
Az2
Ax1
Ax2
Ax3
DAy0 DAy1
Write
DAy3
Ax0 Az1
Az2
Az3
Activate
Command
Bank A
Read
Command
Bank A
Lower Byte
is masked
Read
Lower Byte
is masked
Lower Byte
is masked
Upper Byte
is masked
Command
Bank A
Upper Byte
is masked
Command
Bank A
Burst Length = 4, CAS Latency = 2
Burst Read and Single Write Operation
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
CKE
CS
RAS
CAS
WE
A11(BS)
A10
A0 - A9
LDQM
UDQM
RAv
CAv
CAw
CAx
CAy
CAz
RAv
Hi-Z
Hi-Z
DQ0 - DQ7
DQ8 - DQ15
Av0
Av1
Av2
Av3
DAw0
Ay0
Ay1
Ay3
Az0
Az0
DAx0
Av0
Av1
Av2
Av3
DAw0
Ay0
Ay2
Ay3
Lower Byte
is masked
Lower Byte
is masked
Activate
Command
Bank A
Read
Command
Bank A
Single Write
Command
Bank A
Read
Command
Bank A
Single Write
Command
Bank A
Single Write
Command
Bank A
Upper Byte
is masked
Burst Length = Full Page, CAS Latency = 3, tRCD, tRP = 3
Full Page Burst Read and Single Write Operation
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
CKE
CS
RAS
CAS
WE
A11(BS)
A10
A0 - A9
LDQM
UDQM
RAv
CAv
CAw
CAx
CAy
RAv
Hi-Z
Hi-Z
DQ0 - DQ7
DQ8 - DQ15
Av0
Av1
Av2
Av3
DAw0
DAw0
DAx0
DAx0
Ay0
Ay1
Ay2
Ay3
Av0
Av1
Av2
Av3
Ay0
Ay1
Ay2
Ay3
Activate
Command
Bank A
Read
Command
Bank A
Burst Stop
Command
Single Write
Command
Bank A
Read
Command
Bank A
Burst Stop
Command
Single Write
Command
Bank A
Burst Length = 2, CAS Latency = 1
Random Row Read (Interleaving Banks)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
High
CKE
CS
Begin Auto- Begin Auto- Begin Auto- Begin Auto- Begin Auto- Begin Auto- Begin Auto- Begin Auto- Begin Auto- Begin Auto- Begin Auto-
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
RAS
CAS
WE
A11(BS)
RBu
RBu
RAu
RAu
RBv
RBv
RAv
RAv
RBw
RBw
RAw
RAw
RBx
RBx
RAx
RAx
RBy
RBy
RAy
RAy
RBz
RBz
RAz
A10
CBu
CAu
CBv
CAv
CBw
CAw
CBx
CAx
CBy
CAy
CBz
RAz
A0 - A9
DQM
DQ
tRP
tRP
tRP
tRP
tRP
tRP
tRP
tRP
tRP
tRP
Hi-Z
Bu0
Bu1
Au0
Au1
Bv0
Bv1
Av0
Av1
Bw0 Bw1 Aw0 Aw1 Bx0
Bx1
Ax0
Ax1
By0
By1
Ay0
Ay1
Bz0
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
with Auto-
Precharge
Burst Length = Full Page, CAS Latency = 2
Full Page Random Column Read
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBw
A10
RAx
CAx
CBx
CAy
CBy
CAz
CBz
RBw
A0 - A9
DQM
DQ
tRP
tRRD
tRCD
Hi-Z
Ax0
Bx0
Ay0
Ay1
By0
By1
Az0
Az1
Az2
Bz0
Bz1
Bz2
Precharge
Command Bank B
(Precharge Termination)
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Burst Length = Full Page, CAS Latency = 2
Full Page Random Column Write
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBx
RBw
A10
RAx
CAx
CBx
CAy
CBy
CAz
CBz
RBw
A0 - A9
DQM
DQ
tDPL
tRP
tRRD
tRCD
Hi-Z
DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command Bank B
(Precharge Termination)
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Write Data
is masked
Burst Length = Full Page, CAS Latency = 1
Precharge Termination of a Burst (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAy
RAy
RAz
A10
RAx
CAx
CAy
RAz
CAz
A0 - A9
DQM
DQ
tRP
tRP
Precharge
Termination of
a Read Burst.
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4
Ay0
Ay1
Ay2
DAz0 DAz1 DAz2 DAz3 DAz4 DAz5 DAz6 DAz7
Activate
Command
Bank A
Write
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
Write
Activate
Command
Bank A
Activate
Command
Bank A
of a Write Burst.
Command
Bank A
Write data is masked.
Burst Length = 8 or Full Page, CAS Latency = 2
Precharge Termination of a Burst (2 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK2
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAy
RAy
RAz
RAz
A10
RAx
CAx
CAy
CAz
A0 - A9
DQM
DQ
tRP
tRP
tRP
Hi-Z
DAx0 DAx1 DAx2 DAx3
Ay0
Ay1
Ay2
Az0
Az1
Az2
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
Precharge Termination
of a Read Burst.
Burst Length = 4,8 or Full Page, CAS Latency = 3, tRCD , tRP = 3
Precharge Termination of a Burst (3 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RAy
RAy
RAz
RAz
A10
RAx
CAx
CAy
A0 - A9
DQM
DQ
tRP
tRP
Hi-Z
DAx0 DAx1
Ay0
Ay1
Ay2
Ay3
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Write Data
is masked
Precharge Termination
of a Read Burst.
Precharge Termination
of a Write Burst.
at 100MHz Burst Length = 4, CAS Latency = 3, tRCD, tRP = 3
CS Function (Only CS signal needs to be asserted at minimum rate)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAx
RAx
CAx
CAy
A0 - A9
DQM
DQ
Low
Hi-Z
tDPL
tRCD
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
PACKAGE DIMENSIONS (400mil; 44 lead; Thin Small Outline Package)
18.41 ± 0.13
Detail A
Lead #1
Seating Plane
0.10
+ 0.10
- 0.05
0.35
0.80 Basic
0.805 REF
Detail A
0.25 Basic
Gage Plane
0.05 Min
0.5 ± 0.1
NOTE: All dimensions are in millimeters; Package Diagrams are not drawn to scale.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
PACKAGE DIMENSIONS (400mil; 50 lead; Thin Small Outline Package)
20.95 ± 0.13
Detail A
+0.075
-0.005
0.125
Lead #1
Seating Plane
0.10
+ 0.10
- 0.05
0.35
0.80 Basic
0.875 REF
Detail A
0.25 Basic
1.00 ± 0.05
Gage Plane
+0.10
-0.00
0.5 ± 0.1
0.05
NOTE: All dimensions are in millimeters; Package Diagrams are not drawn to scale.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
PACKAGE DIMENSIONS (400mil; 44 lead; 2 High Stack; Thin Small Outline J Lead Package)
3.20 Max
0.75 Min
18.40 ± 0.28
Lead #1 Identifier (1.27)
Lead #1
Seating Plane
0.10
+ 0.13
- 0.04
+ 0.10
- 0.04
0.8
0.8
0.5
0.3
NOTE: All dimensions are in millimeters; Package Diagrams are not drawn to scale.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Revision Log
Revision
2/10/97
Contents Of Modification
Initial Release (Preliminary)
page 20
Correction to Auto-precharge description/diagram notes. (Page 23, 24)
Change tDPL from 8ns to 10ns for -10.
page 50
page 67
page 45
page 25
page 26
page 29
page 30
page 66
page 70
page 70
page 87
page 95
page 96
page 98
page 101
page 110
page 112
page 115
page 45
5/16/97
Correct CKE transition.
Correction of note regarding total stack current (CBR current).
Precharge Termination changed (now similar to burst stop).
Correct WE - Read Command.
Precharge Termination changed: precharge and subsequent commands 1 clock sooner.
Correct A10 - Precharge Command A.
Precharge Termination changed: last precharge 1 clock sooner.
Fix numbering of data - address Az.
7/14/97
Fix numbering of data - address Az.
Correct A10 - Read Command.
Correct A10 - first Write Command.
Correct A10 - Write and Read Commands.
Precharge Termination: number of data bits after command changed.
Precharge Termination: number of data bits after command changed.
Add note to ICC2NS.
8/21/97
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Revision Log
Remove -7, -8; Add -322, -90. Remove low power SR. Change max. data rate.
Remove VREF, remove part numbers.
Remove VREF
page 1
page 2
page 3
.
page 4
Change part number information.
page 5
Remove VREF. (Also, page 7 - page 9.)
Remove VREF in Power On description.
Change max. data rate.
page 6
page 10
page 14
page 43
page 44
page 45
page 46
page 48
page 49
page 50
page 51
page 55
page 1
10/08/97
Remove SSTL_3 Recommended DC Operating conditions.
Remove SSTL_3 Output Characteristics.
Change currents - different speed sorts.
Change currents - different speed sorts.
Remove -7, -8; Add -322, -90.
Change speed sorts.
Correct address (Page 55 also).
Remove x8 stack. Add Column address clarification. Add note to performance table.
Remove x8 stack.
page 3
Update ordering information.
Remove x8 stack.
page 5
page 9
Change diagrams.
page 22
page 26
page 28
page 30
page 31
Change/ add diagram.
Change diagram.
Change/ add diagram.
Change text (tDPL).
11/14/97
Change diagram/ text (tDPL).
page 32
Specify -322 ICC2P, ICC4 currents.
page 45
page 48
page 52
page 71
page 75
page 91
page 115
Change notes for AC Characteristics and Clock and Clock Enable Parameters tables (VIH, VIL, tT).
Correct/ clarify titles.
Add timing diagram: Random column read, CL=3, tRCD / tRP = 2.
Change diagram.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Revision Log
Update speed sort information: remove -90, add -80. Also, page 5, page 14, page 45, page 46, page
48 - page 51.
page 1
Update Auto-precharge description.
page 21
page 22
page 26
page 35
page 39
page 67
page 74
Add diagrams showing Auto-precharge Interrupt. Also, page 23, page 24.
Change -90 to -80 or add -80. Also, page 28, page 30.
Update Power Down Mode description. Also, page 37.
Update Read/Write with Auto-precharge notes.
1/05/98
Correct address inputs.
Add tDPL clarification. Also, page 75, page 90, page 91, page 115.
Change -322 to -360.
2/2/98
Change ICC2P (2mA->3mA), ICC4 (400µA->2 mA), for -360 sorts.
Add 1Mx16,-80.
2/23/98
page 45
page 5
Remove currents for -360 (x4, x16). Only x8 supported.
page 46
page 49
page 49
3/13/98
5/1/98
Update tHZ
.
Add clarification: tOH
.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Discontinued (12/98 - last order; 9/99 last ship)
International Business Machines Corp.1998
Printed in the United States of America
All rights reserved
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This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
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indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
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