IBM11D1320LC-70 [IBM]
Fast Page DRAM Module, 1MX32, 70ns, CMOS, SIMM-72;
| 型号： | IBM11D1320LC-70 |
| 厂家： | 
IBM |
| 描述： | Fast Page DRAM Module, 1MX32, 70ns, CMOS, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D2320BD2M
x 3210/10, 5.0V, Sn/Pb. IBM11E2320BD2M x 3210/10, 5.0V, Au.
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Features
• 72-Pin JEDEC Standard Single-In-Line
Memory Module
• Performance:
• High Performance CMOS process
• Single 5V, ± 0.5V Power Supply
• Low active current dissipation
• All inputs & outputs are fully TTL & CMOS
compatible
-60
-70
• Fast Page Mode access cycle
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
• 1024 refresh cycles distributed across 16ms
• 10/10 Addressing (Row/Column)
• Optimized for use in byte-write non-parity appli-
cations.
tRAC
tCAC
tAA
RAS Access Time
CAS Access Time
60ns 70ns
15ns 20ns
Access Time From Address 30ns 35ns
tRC
Cycle Time
110ns 130ns
• Only Tin/Lead versions available
• DRAMs in TSOP or SOJ packages
tPC
Fast Page Mode Cycle Time 40ns 45ns
Description
The IBM11D2320L is an 8MB industry standard
72-pin 4-byte single in-line memory module (SIMM).
The module is organized as a 2Mx32 high speed
memory array, and is configured as two 1Mx32
banks -each independently selectable via unique
RAS inputs. The assembly is intended for use in 16,
32 and 64 bit applications. It is manufactured with
four 1Mx16 devices, each in a 400mil TSOP or SOJ
package, and is compatible with the JEDEC 72-Pin
SIMM standard.
The IBM11D1320L is a 4MB half-populated version,
manufactured with two 1Mx16 devices in 400mil
TSOP or SOJ package .
The IBM 72-Pin SIMMs provide a high performance,
flexible 4-byte interface in a 4.25” long footprint.
Card Outline
1
36
37
72
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Pin Description
Pinout
RAS0, RAS2
RAS0 - RAS3
CAS0 - CAS3
WE
Row Address Strobe (4MB)
Row Address Strobe (8MB)
Column Address Strobe
Read/write Input
Pin # Name
Pin # Name
Pin # Name
VSS
1
2
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQ24
DQ7
DQ25
A7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ9
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
VCC
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
VCC
3
A0 - A9
Address Inputs
4
DQ0-7, 9-16, 18-25,
27-34
Data Input/output
5
NC
VCC
6
VCC
Power (+5V)
Ground
VSS
NC
7
A8
No Connect
Presence Detects
8
A9
PD1 - PD4
9
RAS3*
RAS2
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
A0
NC
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
A1
NC
A2
NC
VSS
A3
A4
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1*
NC
A5
A6
NC
PD1
DQ4
DQ22
DQ5
DQ23
DQ6
PD2
PD3
PD4
WE
NC
VSS
NC
1. DQ numbering is compatible with parity (x36) version.
2. * RAS1 and RAS3 are “NC” on 4MB SIMM.
Ordering Information
DRAM Die
Revison
1Mx16
Part Number
Organization
Speed
Addr. Leads
10/10 Sn/Pb
Dimensions
Notes
Packages
IBM11D1320LC-60
IBM11D1320LC-70
IBM11D1320LD-60J
IBM11D1320LD-70J
IBM11D2320LC-60
IBM11D2320LC-70
IBM11D2320LD-60J
IBM11D2320LD-70J
60ns
70ns
60ns
70ns
60ns
70ns
60ns
70ns
4.25” x 1” x .104”
D
E
D
E
TSOP
SOJ
1M x 32
2M x 32
1
1
4.25” x 1” x 205”
4.25” x 1” x .154”
4.25” x 1” x .360”
TSOP
SOJ
1
1
1. DRAM package designator appended to speed portion of part number on assemblies beginning with DRAM die rev E.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Block Diagram
Applies to both 4MB and 8MB SIMMs
DQ18 - DQ25 DQ27 - DQ34
DQ0 - DQ7
DQ9 - DQ16
DQ
DQ
DQ
DQ
A0 - A9
A0 - A9
A0 - A9
WE
WE
WE
RAS0
CAS0
CAS1
U1
U2
RAS
RAS
LCAS
LCAS
UCAS
OE
UCAS
OE
RAS2
CAS2
CAS3
Applies to 8MB SIMM only
DQ18 - DQ25 DQ27 - DQ34
DQ0 - DQ7
DQ9 - DQ16
DQ
DQ
DQ
DQ
A0 - A9
A0 - A9
A0 - A9
WE
WE
WE
U3
U4
RAS
RAS
RAS1
CAS0
CAS1
LCAS
LCAS
UCAS
OE
UCAS
OE
RAS3
CAS2
CAS3
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Truth Table
Row
Address
Column
Address
Function
RAS
CAS
WE
All DQ, PQ bits
H→X
Standby
Read
H
L
L
X
H
L
X
X
High Impedance
Valid Data Out
Valid Data In
L
L
Row
Row
Col
Col
Early-Write
Fast Page Mode - Read:
1st Cycle
H→L
H→L
H→L
L
L
L
H
H
L
Row
N/A
Col
Col
Col
Valid Data Out
Valid Data Out
Valid Data In
Subsequent Cycles
Fast Page Mode - Write:
1st Cycle
Row
H→L
Subsequent Cycles
RAS-Only Refresh
L
L
X
H
H
L
N/A
Row
X
Col
N/A
X
Valid Data In
High Impedance
High Impedance
Data Out
L
H
L
L
L
H→L
CAS-Before-RAS Refresh
L→H→L
L→H→L
Read
Write
Row
Row
Col
Col
Hidden Refresh
Data In
Presence Detect
1M x 32
2M x 32
Pin
-60
VSS
VSS
NC
NC
-70
VSS
VSS
VSS
NC
-60
-70
PD1
PD2
PD3
PD4
NC
NC
NC
NC
NC
NC
VSS
NC
1. NC= OPEN, V = GND
ss
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Absolute Maximum Ratings
Symbol
VCC
Parameter
Power Supply Voltage
Rating
-1.0 to +7.0
Units
V
Notes
1
1
VIN
-0.5 to min (VCC + 0.5, 7.0)
-0.5 to min (VCC + 0.5, 7.0)
0 to +70
Input Voltage
V
VOUT
TOPR
TSTG
PD
Output Voltage
V
1
°C
°C
W
Operating Temperature
Storage Temperature
Power Dissipation
1
-55 to +125
1
1.8 (4M) 3.6 (8M)
50
1, 2
1
IOUT
Short Circuit Output Current
mA
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect reliability.
2. Maximum power occurs when all banks are active (refresh cycle).
Recommended DC Operating Conditions (TA = 0 to 70°C)
Symbol
VCC
Parameter
Min
4.5
Typ
5.0
—
Max
5.5
Units
Notes
1
Supply Voltage
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
2.4
VCC + 0.5
0.8
1, 2
1, 2
-0.5
—
1. All voltages referenced to VSS
.
2. VIH may overshoot to VCC + 2.0V for pulse widths of ≤ 4.0ns (or VCC + 1.0V for ≤ 8.0ns). Additionally, VIL may undershoot to -2.0V
for pulse widths ≤ 4.0ns (or -1.0V for ≤ 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC refer-
ence.
Capacitance (TA = 0 to +70°C, VCC = 5.0V ± 0.5V)
1M x 32
Max
2M x 32
Max
Symbol
Parameter
Units
CI1
CI2
CI3
CI4
CI5
CI/O
Input Capacitance (A0-A9)
51
39
33
18
62
16
98
40
pF
pF
pF
pF
pF
pF
Input Capacitance (4MB: RAS0, 8MB: RAS0, 1)
Input Capacitance (4MB: RAS2, 8MB: RAS2, 3)
Input Capacitance (CAS)
40
51
Input Capacitance (WE)
103
29
Output Capacitance (DQ0-DQ34)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
DC Electrical Characteristics (TA = 0 to +70°C, VCC = 5.0V ± 0.5V)
Symbol
Parameter
1M x 32
2M x 32
Units Notes
-60
-70
—
330
280
—
334
284
Operating Current
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min)
ICC1
mA
mA
mA
1, 2, 3
—
—
—
—
Standby Current (TTL)
Power Supply Standby Current
(RAS = CAS ≥ VIH)
ICC2
4
8
-60
-70
-60
-70
—
—
—
—
330
280
180
160
—
—
—
—
334
284
184
164
RAS Only Refresh Current
Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS ≥ VIH: tRC = tRC min)
ICC3
1, 3, 4
1, 2, 3
Fast Page Mode Current
Average Power Supply Current, Fast Page Mode
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
ICC4
ICC5
ICC6
mA
mA
mA
Standby Current (CMOS)
Power Supply Standby Current
(RAS = CAS = VCC - 0.2V)
—
2
—
4
-60
-70
—
—
330
280
—
—
334
284
CAS Before RAS Refresh Current
Average Power Supply Current, CAS Before RAS Mode
(RAS, CAS, Cycling: tRC = tRC min)
1, 3, 4
RAS
CAS
-10
-10
-20
+10
+10
+20
-10
-20
-40
+10
+20
+40
Input Leakage Current
Input Leakage Current, any input
(0.0 ≤ VIN ≤ (VCC < 6.0V))
µA
II(L)
All Other Pins Not Under Test = 0V
All others
Output Leakage Current
µA
V
IO(L)
VOH
VOL
-10
2.4
—
+10
—
-20
2.4
—
+20
—
(DOUT is disabled, 0.0 ≤ VOUT ≤ VCC
)
Output High Level
Output "H" Level Voltage (IOUT = -5mA @ 2.4V)
Output Low Level
Output "L" Level Voltage (IOUT = +4.2mA @ 0.4V)
0.4
0.4
V
1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
2. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open.
3. Address can be changed once or less while RAS = VIL. In the case of ICC4, it can be changed once or less when CAS = VIH
4. Refresh current is specified for 1 bank active and 1 bank standby.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
AC Characteristics (TA = 0 to +70°C, VCC = 5.0V ± 0.5V)
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL.
2. An initial pause of 100µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
3. AC measurements assume tT = 5ns.
4. When CAS0 and CAS1, or CAS2 and CAS3 go low at the same time, all 16 bits of data are read/written into the DRAM. CAS0 and
CAS1, or CAS2 and CAS3 (CAS’s to the same DRAM) cannot be staggered within the same read/write cycle.
Read, Write, and Refresh Cycles (Common Parameters)
-60
-70
Symbol
Parameter
Units
Notes
Min
110
40
10
60
15
0
Max
—
Min
130
50
10
70
20
0
Max
—
tRC
tRP
Random Read or Write Cycle Time
RAS Precharge Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
tCP
CAS Precharge Time
—
—
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tDZC
tT
RAS Pulse Width
10K
10K
—
10K
10K
—
CAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
10
0
—
10
0
—
—
—
10
20
15
15
60
5
—
10
20
15
20
70
5
—
45
30
—
50
35
—
1
2
CAS Hold Time
—
—
CAS to RAS Precharge Time
CAS Delay Time from DIN
Transition Time (Rise and Fall)
Column Address Hold Time Referenced to RAS
—
—
0
—
0
—
3
30
—
3
50
—
tAR
—
—
3
1. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only: if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled by tCAC
2. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only: If tRAD
is greater than the specified tRAD (max) limit, then access time is controlled by tAA
3. This timing parameter is not applicable to this product, but applies to a related product in this family.
.
.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Write Cycle
-60
-70
Symbol
Parameter
Write Command Set Up Time
Units
Notes
Min
0
Max
—
Min
0
Max
—
tWCS
tWCH
tWP
ns
ns
ns
ns
ns
ns
ns
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
DIN Setup Time
15
15
—
—
0
—
15
15
—
—
0
—
—
—
tRWL
tCWL
tDS
—
—
1
1
—
—
—
—
tDH
DIN Hold Time
12
—
15
—
1. This timing parameter is not applicable to this product, but applies to a related product in this family.
Read Cycle
-60
-70
Symbol
Parameter
Units
Notes
Min
—
—
—
0
Max
60
15
30
—
Min
—
—
—
0
Max
70
20
35
—
tRAC
tCAC
tAA
Access Time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
1, 3
Access Time from CAS
Access Time from Address
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
CAS to Output in Low-Z
2, 3
tRCS
tRCH
tRRH
tRAL
tCAL
tCLZ
tOH
0
—
0
—
4
4
5
—
5
—
30
30
0
—
35
35
0
—
—
—
—
—
3
5
Output Data Hold Time
3
—
3
—
tCDD
tOFF
CAS to DIN Delay Time
15
—
—
15
—
—
Output Buffer Turn-off Delay
15
15
1. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled by tCAC.
2. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If tRAD
is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
3. Measured with the specified current load and 100pF.
4. Either tRCH or tRRH must be satisfied for a read cycle.
5. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Fast Page Mode Cycle
-60
-70
Symbol
Parameter
Fast Page Mode Cycle Time
Units
Notes
Min
40
60
35
—
Max
—
Min
45
70
40
—
Max
—
tPC
ns
ns
ns
ns
tRASP
tCPRH
tCPA
Fast Page Mode RAS Pulse Width
RAS Hold Time from CAS Precharge
Access Time from CAS Precharge
100K
—
100K
—
35
40
1, 2
1. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA
2. Access time assumes a load of 100pF.
.
Refresh Cycle
-60
-70
Symbol
Parameter
Units
Notes
Min
10
Max
—
Min
10
Max
—
CAS Hold Time
tCHR
tCSR
tWRP
tWRH
ns
ns
ns
ns
(CAS before RAS Refresh Cycle)
CAS Setup Time
(CAS before RAS Refresh Cycle)
5
—
—
—
5
—
—
—
WE Setup Time
(CAS before RAS Refresh Cycle)
10
10
10
10
WE Hold Time
(CAS before RAS Refresh Cycle)
tRPC
tREF
RAS Precharge to CAS Hold Time
Refresh Period
5
—
5
—
ns
—
16
—
16
ms
1
1. 1024 refreshes are required every 16ms.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
tCAS
CAS0, 2
CAS1, 3
VIL
tRAL
tRAD
tASC
tCAL
tASR
tAR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tRCH
tRCS
tRRH
VIH
VIL
WE
tAA
tDZC
tCDD
VIH
VIL
Hi-Z
DIN
tCAC
tOFF
tCLZ
VOH
VOL
Hi-Z
Hi-Z
DOUT
Valid Data Out
tOH
tRAC
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Write Cycle (Early Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
VIL
CAS0, 2
CAS1, 3
tCAS
tAR
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWCS
tWCH
VIH
VIL
tWP
WE
tDS
tDH
VIH
VIL
DIN
Valid Data In
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Fast Page Mode Read Cycle
tRASP
tRP
tCPRH
VIH
RAS
VIL
tPC
tCRP
tRSH
tCP
tRCD
tCP
VIH
VIL
tCAS
CAS0, 2
CAS1, 3
tCAS
tCAS
tCAL
tCSH
tRAL
tAR
tRAH
tASR
tASC tCAH
tCAH
tASC
tASC tCAH
Column N
VIH
VIL
Address
Column 1
Column 2
Row
tRAD
tRCS
tRCS
t
tRCH
RCS
tRCH
tRCH
VIH
VIL
WE
tRRH
tAA
tAA
tAA
tCPA
tCPA
tOH
tOH
tOH
t
t
DZC
tDZC
t
DZC
CDD
VIH
VIL
DIN
tCAC
tCAC
tCAC
tOFF
tOFF
tOFF
tRAC
tCLZ
tCLZ
tCLZ
VOH
VOL
DOUT
1
DOUT
2
DOUT N
DOUT
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Fast Page Mode Write Cycle
tRASP
tRP
VIH
RAS
VIL
tPC
tCRP
tRSH
tRCD
tCP
tCP
VIH
VIL
tCAS
tCAS
tCAS
CAS0, 2
CAS1, 3
tCSH
tCAH
tAR
tRAH
tASC tCAH
tASR
tASC tCAH
tASC
VIH
VIL
Address
Column 1
Column 2
Column N
tCWL
Row
tRAD
tWCR
tCWL
tCWL
tRWL
tWCH
tWCH
tWCH
tWCS
tWCS
tWCS
tWP
tWP
tWP
VIH
VIL
WE
tDHR
tDS
tDS tDH
tDS tDH
tDH
VIH
VIL
DIN
DIN
1
DIN
2
DIN N
VOH
VOL
DOUT
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
RAS Only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCRP
tRPC
VIH
CAS0, 2
CAS1, 3
VIL
tASR
tRAH
VIH
VIL
Address
Row
VOH
VOL
Hi-Z
DOUT
: “H” or “L”
Note: WE, DIN are “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
CAS Before RAS Refresh Cycle
tRC
tRAS
tRP
VIH
VIL
RAS
tRPC
tRPC
tCSR
tCSR
tCP
tCHR
VIH
VIL
CAS0, 2
CAS1, 3
tWRH
tWRH
tWRP
tWRP
VIH
VIL
WE
tCDD
VOH
VOL
DIN
Hi-Z
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: Address is “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Hidden Refresh Cycle (Read)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRCD
tRSH
tCRP
tCHR
VIH
VIL
CAS0, 2
CAS1, 3
tRAL
tWRH
tWRP
tRAD
tASC
tASR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tRRH
tRCS
VIH
VIL
WE
tAA
tDZC
tCDD
VIH
VIL
Hi-Z
DIN
tCAC
tCLZ
tOFF
VOH
VOL
DOUT
Valid Data Out
Hi-Z
Hi-Z
tRAC
tOH
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Hidden Refresh Cycle (Write)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRSH
tCRP
tRCD
tCHR
VIH
CAS0, 2
CAS1, 3
VIL
tASR
tASC
tRAH
tCAH
tWCH
tDH
VIH
VIL
Address
Row
Column
tWRP
tWRH
tWCS
VIH
VIL
tWP
WE
tDS
VIH
VIL
DIN
Valid Data
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Layout Drawing: IBM11D1320L (4MB) & IBM11D2320L (8MB) TSOP Versions
107.95
4.25
101.190
3.983
Front
(2X) 0
3.1877
.1255
6.35
.250
2.03
.08
1.27 PITCH
.050
44.45
1.75
1.00 WIDTH
.039
95.25
3.75 REF.
Side (4MB)
Side (8MB)
2.65
3.92
.104 MAX.
.154 MAX.
.1016
.1016
+
_
+
_
1.27
.050
1.27
.050
.0762
.0762
.004
+
_
.004
+
_
.003
.003
Millimeters
Inches
Note: All dimensions are typical unless otherwise stated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Layout Drawing: IBM11D1320L (4MB) & IBM11D2320L (8MB) SOJ Versions
107.95
4.25
101.190
3.983
Front
(2X) 0
3.1877
.1255
6.35
.250
2.03
.08
1.27 PITCH
.050
44.45
1.75
1.00 WIDTH
.039
95.25
3.75 REF.
Side (8MB)
Side (4MB)
5.20
9.14
.205 MAX.
.360 MAX.
.1016
.0762
.1016
+
_
+
_
1.27
.050
1.27
.050
.0762
.004
.004
+
_
+
_
.003
.003
Millimeters
Inches
Note: All dimensions are typical unless otherwise stated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
IBM11D1320L
IBM11D2320L
1M/2M x 32 DRAM Module
Revision Log
Rev
Contents of Modification
Initial release of combined spec for 1M x 32 TSOP, and 2M x 32 TSOP and SOJ versions
(originally released as spec #’s 03H7550 and 03H7551)
Lowered operating currents and max power
Removed Die Rev “C” offerings.
tRPC (min) changed from 0 to 5ns.
tCHR (min) changed from 20 to 10ns.
tRRH (min) changed from 5 to 0ns.
tCAH (min) changed from 15 to 10ns.
tCSR (min) changed from 5 to 10ns.
tDH changed from 15 to 12ns for -60ns part.
3/96
CBR timing diagram changed to allow CAS to remain low for back-to-back CBR cycles
Added package description to speed designation
Updated ordering information
6/96
8/96
Corrected typo’s
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7991
SA14-4334-02
Revised 8/96
Discontinuted (9/98 - last order; 3/99 last ship)
International Business Machines Corp.1996
Printed in the United States of America
All rights reserved
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This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
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