IBM25PPC440GP-3CC466CZ [IBM]
RISC Microprocessor, 32-Bit, 466MHz, CMOS, CBGA552, 25 X 25 MM, CERAMIC, BGA-552;
| 型号： | IBM25PPC440GP-3CC466CZ |
| 厂家： | 
IBM |
| 描述： | RISC Microprocessor, 32-Bit, 466MHz, CMOS, CBGA552, 25 X 25 MM, CERAMIC, BGA-552 时钟 外围集成电路 |
| 文件： | 总64页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PowerPC 440GP Embedded Processor Data Sheet
Features
• PowerPC 440 processor core operating up to
500MHz with 32KB I- and D-caches
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are
MII, RMII, and SMII.
• On-chip8 KB SRAM
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Selectable processor:bus clock ratios of 3:1,
4:1, 5:1, 5:2, 7:2
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) 32/64-bit interface operating up to
133MHz
• External Peripheral Bus for up to eight devices
with external mastering
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• DMA support for external peripherals, internal
UART and memory
• Internal Processor Local Bus (PLB) runs at
DDR SDRAM interface frequency
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI
V2.2
• PowerPC processor boot from PCI memory
Description
Designed specifically to address high-end
Technology: IBM CMOS SA-27E, 0.18µm
embedded applications, the PowerPC 440GP
(PPC440GP) provides a high-performance, low
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power
management features and lower power dissipation.
(0.11 Leff), 5-layer metal
Package: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA)
Power (estimated): Less than 4.0W. Less than
1.0 W in sleep mode
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,8KB
SRAM, PCI-X bus interface, Ethernet interfaces,
control for external ROM and peripherals, DMA with
scatter-gather support, serial ports, IIC interface,
and general purpose I/O.
Supply voltages required: 3.3V, 2.5V, 1.8V
Page 1 of 64
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PowerPC 440GP Embedded Processor Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 10
Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Heat Sink Mounting Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figures
PPC440GP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
25mm, 552-Ball CBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 14
Heat Sink Attached With Spring Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Heat Sink Attached With Adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DDR SDRAM Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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PowerPC 440GP Embedded Processor Data Sheet
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O Specifications—400, 466, and 500MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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PowerPC 440GP Embedded Processor Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local IBM sales office.
Product
Name
Processor
Frequency
Rev
Level
1
Package
PVR Value
JTAG ID
Order Part Number
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
Notes:
IBM25PPC440GP-3CC400C
IBM25PPC440GP-3CC400CZ
IBM25PPC440GP-3CC400E
IBM25PPC440GP-3CC400EZ
IBM25PPC440GP-3CC466C
IBM25PPC440GP-3CC466CZ
IBM25PPC440GP-3CC500C
IBM25PPC440GP-3CC500CZ
400MHz
400MHz
400MHz
400MHz
466MHz
466MHz
500MHz
500MHz
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
C
C
C
C
C
C
C
C
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x02052049
0x02052049
0x02052049
0x02052049
0x02052049
0x02052049
0x02052049
0x02052049
1. Z at the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) is software accessible and contains additional information about the
revision level of the part. Refer to the PPC440GP User’s Manual for details on the register content.
Order Part Number Key
IBM25PPC440GP-3CC500Ex
Shipping Package:
Blank = Tray
Z
= Tape and reel
Case Temperature Range
C = -40°C to +85°C
IBM Part Number
E = -40°C to +105°C
Grade 3 Reliability
Package (CBGA)
Processor Speed
Revision Level
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PowerPC 440GP Embedded Processor Data Sheet
PPC440GP Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
PPC440
UART
x2
IIC
x2
GP
Timers
GPIO
DCR Bus
Processor Core
45 internal
13 external
Trace
JTAG
On-chip Peripheral Bus (OPB)
Arb
32KB
32KB
D-Cache
I-Cache
DMA
Controller
(4-Channel)
OPB
Bridge
SRAM
8KB
Processor Local Bus (PLB)
External
Bus
Controller
External
Bus Master
Controller
Ethernet
x2
MAL
1 MII
or
2 RMII
or
66MHz max
DDR SDRAM
Controller
PCI-X
Bridge
32-bit addr
32-bit data
2 SMII
133MHz max
133MHz max
13-bit addr
32/64-bit data
The PPC440GP is designed using the IBM Microelectronics Blue Logic methodology in which major
functional blocks are integrated together to create an application-specific product (ASIC). This approach
provides a consistent way to create complex ASICs using IBM CoreConnect Bus Architecture.
Note: IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 133.33MHz, 2.1GB/s
• 32-bit OPB interfaces up to 66.66MHz, 266MB/s
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map.
This address map defines the possible contents of various address regions which the processor can access.
The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440GP processor through the use of mtdcr and mfdcr instructions.
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PowerPC 440GP Embedded Processor Data Sheet
System Memory Address Map
Function
Sub Function
Start Address
0 0000 0000
0 8000 0000
0 8000 2000
1 0000 0000
1 4000 0000
1 4000 0200
1 4000 0208
1 4000 0300
1 4000 0308
1 4000 0400
1 4000 0420
1 4000 0500
1 4000 0520
1 4000 0600
1 4000 0640
1 4000 0700
1 4000 0780
1 4000 0790
1 4000 0790
1 4000 0800
1 4000 0900
1 4000 0A00
1 4000 0B00
1 F000 0000
End Address
0 7FFF FFFF
0 8000 1FFF
0 FFFF FFFF
1 3FFF FFFF
1 4000 01FF
1 4000 0207
1 4000 02FF
1 4000 0307
1 4000 03FF
1 4000 041F
1 4000 04FF
1 4000 051F
1 4000 05FF
1 4000 063F
1 4000 06FF
1 4000 077F
1 4000 078F
1 4000 079F
1 4000 07FF
1 4000 08FF
1 4000 09FF
1 4000 0AFF
1 EFFF FFFF
1 FFDF FFFF
Size
2GB
8KB
DDR SDRAM
SRAM
1
Local Memory
Reserve
EBC
1GB
8B
Reserved
UART0
Reserved
UART1
8B
Reserved
IIC0
32B
32B
64B
Reserved
IIC1
Reserved
OPB Arbiter
Reserved
Internal Peripherals
GPIO Controller
Ethernet PHY ZMII
Ethernet PHY GMII
Reserved
128B
16B
16B
Ethernet 0 Controller
Ethernet 1 Controller
General Purpose Timer
Reserved
256B
256B
256B
2
254MB
2MB
Expansion ROM
2, 3
1 FFE0 0000
1 FFFF FFFF
Boot ROM
Reserved
2 0000 0000
2 0800 0000
2 0C00 0000
2 0EC0 0000
2 0EC0 0008
2 0EC8 0000
2 0EC8 0100
2 0ED0 0000
2 0EE0 0000
2 07FF FFFF
2 0BFF FFFF
2 0EBF FFFF
2 0EC0 0007
2 0EC7 FFFF
2 0EC8 00FF
2 0EC8 00FF
2 0EDF FFFF
F FFFF FFFF
PCI-X I/O
64MB
8B
Reserved
PCI-X External Configuration Registers
Reserved
PCI-X
PCI-X Bridge Core Configuration Registers
Reserved
256B
PCI-X Special Cycle
PCI-X Memory
1MB
55.76 GB
Notes:
1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.
2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While
locating volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.
3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 2 FFFE 0000 (128 KB).
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PowerPC 440GP Embedded Processor Data Sheet
DCR Address Map 4KB of Device Configuration Registers
Function
Start Address
End Address
Size
1
1
000
3FF
Total DCR Address Space
1KW (4KB)
By function:
Reserved
000
010
012
014
016
020
030
080
090
0A0
0A8
0B0
0B8
0C0
0D0
0E0
0F0
100
140
180
200
00F
011
013
015
01F
02F
07F
08F
09F
0A7
0AF
0B7
0BF
0CF
0DF
0EF
0FF
13F
17F
1FF
3FF
16W
2W
Memory Controller
External Bus Controller
External Bus Master I/F
PLB Performance Monitor
SRAM
2W
2W
10W
16W
80W
16W
16W
8W
Reserved
PLB
PLB to OPB Bridge Out
Reserved
OPB to PLB Bridge In
Power Management
Reserved
8W
8W
8W
Interrupt Controller 0
Interrupt Controller 1
Clock, Control, and Reset
Reserved
16W
16W
16W
16W
64W
64W
128W
512W
DMA Controller
Reserved
Ethernet MAL
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single
32-bit (word) register. One kiloword (1024W) equals 4KB (4096 bytes).
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PowerPC 440GP Embedded Processor Data Sheet
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, routers, switches,
printers, set-top boxes, etc. It is the first processor core to implement the new Book E PowerPC embedded
architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
• Up to 500MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• 3 execution pipelines
• Dynamic branch prediction
• Memory management unit
– 64-entry, full associative, unified TLB
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
• Debug facilities
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
• 24 DSP instructions
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
Internal Buses
The PowerPC 440GP features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-
Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high
bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the
PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR
provides a lower bandwidth path for passing status and control information between the processor core and
the other on-chip cores.
Features include:
• PLB
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 133MHz, maximum 4.2GB/s (simultaneous read and write)
– Processor:bus clock ratios of 3:1, 4:1, 5:1, 5:2, and 7:2
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PowerPC 440GP Embedded Processor Data Sheet
• OPB
– Dynamic bus sizing 32-, 16-, and 8-bit data path
– Separate and simultaneous read and write data paths
– 36-bit address
– 66.66MHz, maximum 266MB/s
• DCR
– 32-bit data path
– 10 bit address
On-Chip SRAM
Features include:
• One physical bank of 8KB
• Memory cycles supported:
– Single beat read and write, 1 to 16 bytes
– 32- and 64-byte burst transfers
– Guarded memory accesses
• Sustainable 2.1GB/s peak bandwidth at 133MHz
PCI-X Interface
The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local
memory. This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit
PCI-X buses. PCI 32/64-bit legacy mode, compatible with PCI Version 2.2, is also supported.
Reference Specifications:
• PowerPC CoreConnect Bus (PLB) version PLB4
• PCI Specification Version 2.2
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• PCI-X 1.0a
– Split transactions
– Frequency to 133MHz
– 32- and 64-bit bus
• PCI 2.2 backward compatibility
– Frequency to 66MHz
– 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with
an external arbiter
• Support for Message Signaled Interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI-X bus memory
• Error tracking/status
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4/1/03
PowerPC 440GP Embedded Processor Data Sheet
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs and
other discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global
memory timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
• Registered and non-registered industry standard DIMMs and other discrete devices
• 32- or 64-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 2.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• PC200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)
External Peripheral Bus Controller (EBC)
Features include:
• Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation (266MB/s)
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus
• 32-bit address, 4GB address space
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
• External master interface
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for own access and control
Page 10 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Ethernet Controller Interface
Ethernet support provided by the PPC440GP interfaces to the physical layer but the PHY is not included on
the chip:
• One or two interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s
– One full Media Independent Interface (MII) with 4-bit parallel data transfer
– Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer
– Two Serial Media Independent Interfaces (SMII)
DMA Controller
Features include:
• Supports the following transfers:
– Memory-to-memory transfers
– Buffered peripheral to memory transfers
– Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 64-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
Serial Port
Features include:
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with NS16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC Bus Interface
Features include:
Page 11 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
• Two IIC interfaces provided
• Support for Philips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the
processor core.
• 32-bit Time Base Counter driven by the OPB bus clock
• Five 32-bit compare timers
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses.
• 31 of the 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has
GPIO capabilities acts as a GPIO or is used for another purpose.
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
Universal Interrupt Controller (UIC)
TwoUniversal Interrupt Controllers (UIC) are available. They provide control, status, and communications
necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
• 13 external interrupts
• 45 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
Page 12 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
JTAG
Features include:
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)
Page 13 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
25mm, 552-Ball CBGA Package
Top View
A1 Corner
Chip
Capacitor
Note: All dimensions are in mm.
Bottom View
25.0 ± 0.2
23.0
1.95 MAX
1.65 MIN
AD
AB
Y
1.00 TYP
AC
AA
W
U
V
T
R
P
25.0 ± 0.2
N
8.04
M
K
H
F
L
J
G
E
D
B
C
A
1
3
5
7
9 11 13 15 17
8 10
19 21 23
0.8 TYP
3.80 MAX
6
12 14
16 18
4
22
20 24
2
0.8 ± 0.04 SOLDERBALL x 552
Page 14 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which
the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and
the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for
each signal name on the ball. The page number listed gives the page in “Signal Functional Description” on
page 40 where the signals in the indicated interface group begin. In cases where signals in the same
interface group (for example, Ethernet) have different names to distinguish variations in the mode of
operation, the names are separated by a comma with the primary name appearing first. These signals are
listed only once, and appear alphabetically by the primary name.
Signals Listed Alphabetically (Part 1 of 18)
Signal Name
Ball
Interface Group
Page
AGND
AGND
AGND
AMV
J01
J24
Power—Analog ground
46
AA11
AB11
Power—MemClkOut PLL analog voltage
Power—PCI-X PLL analog voltage
Power—SysClk PLL analog voltage
46
46
46
DD
APV
ASV
G01
DD
DD
G24
AA16
AD09
AB15
W14
AD11
AD05
F14
BA0
BA1
DDR SDRAM
41
BankSel0
BankSel1
BankSel2
BankSel3
DDR SDRAM
41
[BE0]PCIXC0
[BE1]PCIXC1
[BE2]PCIXC2
[BE3]PCIXC3
[BE4]PCIXC4
[BE5]PCIXC5
[BE6]PCIXC6
[BE7]PCIXC7
BusReq
CAS
E16
C19
F20
PCI-X
40
C08
C03
G09
F09
AA24
AB05
AD17
AB10
Y09
External Master Peripheral
DDR SDRAM
43
41
ClkEn0
ClkEn1
DDR SDRAM
41
ClkEn2
ClkEn3
W09
T16
DM0
DM1
AA18
AB14
P13
DM2
DM3
DM4
AA09
AA07
Y03
DDR SDRAM
41
DM5
DM6
DM7
V03
DM8
AC05
Page 15 of 64
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 2 of 18)
Signal Name
Ball
N05
P07
Interface Group
Page
DMAAck0
DMAAck1
DMAAck2
DMAAck3
DMAReq0
DMAReq1
DMAReq2
DMAReq3
DQS0
External Slave Peripheral
42
P06
P11
R03
M11
N11
P01
External Slave Peripheral
42
AC20
AC16
AC14
AB13
AC11
AC09
Y04
DQS1
DQS2
DQS3
DQS4
DDR SDRAM
41
DQS5
DQS6
DQS7
T01
DQS8
AA05
L07
DrvrInh1
DrvrInh2
ECC0
System
System
45
45
A05
AB07
AB06
AD06
W07
U09
AC03
AB04
AD04
J07
ECC1
ECC2
ECC3
DDR SDRAM
41
ECC4
ECC5
ECC6
ECC7
EMCCD, EMC1RxErr
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
41
41
41
41
41
EMCCrS, EMC0CrSDV
EMCMDClk
K07
J08
EMCMDIO
L05
EMCRxClk
J02
EMCRxD0, EMC0RxD0, EMC0RxD
EMCRxD1, EMC0RxD1, EMC1RxD
EMCRxD2, EMC1RxD0
EMCRxD3, EMC1RxD1
EMCRxDV, EMC1CrSDV
EMCRxErr, EMC0RxErr
EMCTxClk, EMCRefClk
EMCTxD0, EMC0TxD0, EMC0TxD
EMCTxD1, EMC0TxD1, EMC1TxD
EMCTxD2, EMC1TxD0
EMCTxD3, EMC1TxD1
EMCTxEn, EMC0TxEn, EMCSync
EMCTxErr, EMC1TxEn
G03
E01
Ethernet
41
A07
H09
K01
Ethernet
Ethernet
Ethernet
41
41
41
K03
J06
L09
K05
Ethernet
41
J04
J03
L06
Ethernet
Ethernet
41
41
C05
Page 16 of 64
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 3 of 18)
Signal Name
Ball
R16
P15
P16
M16
AA22
AB23
T17
B06
B10
B13
B17
B21
D04
D08
D12
D15
D19
D23
F02
F06
F10
F13
F17
F21
H04
H08
H12
H15
H19
H23
K02
K06
K10
K13
K17
K21
M04
M08
M12
M15
M19
M23
Interface Group
Page
EOT0/TC0
EOT1/TC1
EOT2/TC2
EOT3/TC3
ExtAck
ExtReq
ExtReset
GND
External Slave Peripheral
42
External Master Peripheral
External Master Peripheral
External Master Peripheral
43
43
43
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
46
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Page 17 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 4 of 18)
Signal Name
Ball
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N02
N06
N10
N13
N17
N21
R04
R08
R12
R15
R19
R23
U02
U06
U10
U13
U17
U21
Power
46
W04
W08
W12
W15
W19
W23
AA02
AA06
AA10
AA13
AA17
AA21
AC04
AC08
AC12
AC15
AC19
Page 18 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 5 of 18)
Signal Name
Ball
N18
L20
P20
L18
N14
M20
M14
P18
N20
P22
V18
P14
C18
J16
Interface Group
Page
[GPIO00]IRQ00
[GPIO01]IRQ01
[GPIO02]IRQ02
[GPIO03]IRQ03
[GPIO04]IRQ04
[GPIO05]IRQ05
[GPIO06]IRQ06
[GPIO07]IRQ07
[GPIO08]IRQ08
[GPIO09]IRQ09
[GPIO10]IRQ10
GPIO11
[GPIO12]UART1_Rx
[GPIO13]UART1_Tx
[GPIO14]UART1_DSR/CTS
[GPIO15]UART1_RTS/DTR
[GPIO16]IIC1SClk
[GPIO17]IIC1SDA
[GPIO18]TrcBS0
[GPIO19]TrcBS1
[GPIO20]TrcBS2
[GPIO21]TrcES0
[GPIO22]TrcES1
[GPIO23]TrcES2
[GPIO24]TrcES3
[GPIO25]TrcES4
[GPIO26]TrcTS0
[GPIO27]TrcTS1
[GPIO28]TrcTS2
[GPIO29]TrcTS3
[GPIO30]TrcTS4
[GPIO31]TrcTS5
Halt
G06
E05
H11
H14
N16
P17
T20
T21
P23
N09
P08
T05
T04
P03
R07
P09
R09
T06
V05
Y21
Y23
G11
G13
H11
H14
System
45
System
45
43
43
43
43
43
43
HoldAck
External Master Peripheral
External Master Peripheral
IIC Peripheral
HoldReq
IIC0SClk
IIC0SDA
IIC Peripheral
IIC1SClk[GPIO16]
IIC1SDA[GPIO17]
IIC Peripheral
IIC Peripheral
Page 19 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 6 of 18)
Signal Name
Ball
N18
L20
Interface Group
Page
IRQ00[GPIO00]
IRQ01[GPIO01]
IRQ02[GPIO02]
IRQ03[GPIO03]
IRQ04[GPIO04]
IRQ05[GPIO05]
IRQ06[GPIO06]
IRQ07[GPIO07]
IRQ08[GPIO08]
IRQ09[GPIO09]
IRQ10[GPIO10]
[IRQ11]PCIReq1
[IRQ12]PCIGnt1
MemAddr00
P20
L18
N14
M20
M14
P18
N20
P22
V18
E21
C22
Y19
AD20
Y20
AB20
AD18
AD16
AB18
Y14
V13
V11
W16
Y11
V10
V09
V08
Interrupts
44
MemAddr01
MemAddr02
MemAddr03
MemAddr04
MemAddr05
MemAddr06
DDR SDRAM
41
MemAddr07
MemAddr08
MemAddr09
MemAddr10
MemAddr11
MemAddr12
MemClkOut0
MemClkOut0
DDR SDRAM
41
Page 20 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 7 of 18)
Signal Name
Ball
AD21
AB21
AC22
AA20
U16
Interface Group
Page
MemData00
MemData01
MemData02
MemData03
MemData04
MemData05
MemData06
MemData07
MemData08
MemData09
MemData10
MemData11
MemData12
MemData13
MemData14
MemData15
MemData16
MemData17
MemData18
MemData19
MemData20
MemData21
MemData22
MemData23
MemData24
MemData25
MemData26
MemData27
MemData28
MemData29
MemData30
MemData31
V17
AD19
AB19
W18
V16
Y17
AB16
AC18
Y18
R14
AB17
AA14
AD15
T15
DDR SDRAM
41
V15
Y16
U14
T13
Y15
AD13
AD14
V14
Y13
P12
AB12
Y12
V12
Page 21 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 8 of 18)
Signal Name
Ball
W11
AD12
Y10
Interface Group
Page
MemData32
MemData33
MemData34
MemData35
MemData36
MemData37
MemData38
MemData39
MemData40
MemData41
MemData42
MemData43
MemData44
MemData45
MemData46
MemData47
MemData48
MemData49
MemData50
MemData51
MemData52
MemData53
MemData54
MemData55
MemData56
MemData57
MemData58
MemData59
MemData60
MemData61
MemData62
MemData63
MemVRef1
MemVRef2
T12
U11
T11
T10
AD10
AB08
AD08
R11
Y07
AC07
AB09
Y06
Y08
DDR SDRAM
41
AA01
AA03
AB02
Y01
AB03
Y02
V07
V01
T08
U07
W01
W03
V06
T07
W05
U05
T14
DDR SDRAM
41
T09
Page 22 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 9 of 18)
Signal Name
Ball
Interface Group
Page
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
A01
A02
A03
A22
A23
A24
B01
B02
B23
B24
C01
C24
A physical ball does not exist at these ball coordinates.
NA
AB01
AB24
AC01
AC02
AC23
AC24
AD01
AD02
AD03
AD22
AD23
AD24
Page 23 of 64
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 10 of 18)
Signal Name
Ball
B04
B12
B19
D02
D10
D17
F08
F15
F23
H06
H10
H13
H21
K04
K08
K19
M02
M17
N08
N23
R06
R17
R21
U04
U19
W02
Interface Group
Page
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Power
46
AA23
G08
D09
PCIX133Cap
PCIXAck64
PCI-X
PCI-X
40
40
Page 24 of 64
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 11 of 18)
Signal Name
Ball
C17
B09
G10
E10
C10
A10
F11
G12
G14
A15
C15
E15
G15
B16
C16
D16
E18
E19
F18
G18
D20
A20
A21
C21
F22
B22
G21
E23
C23
F24
D22
D24
Interface Group
Page
PCIXAD00
PCIXAD01
PCIXAD02
PCIXAD03
PCIXAD04
PCIXAD05
PCIXAD06
PCIXAD07
PCIXAD08
PCIXAD09
PCIXAD10
PCIXAD11
PCIXAD12
PCIXAD13
PCIXAD14
PCIXAD15
PCIXAD16
PCIXAD17
PCIXAD18
PCIXAD19
PCIXAD20
PCIXAD21
PCIXAD22
PCIXAD23
PCIXAD24
PCIXAD25
PCIXAD26
PCIXAD27
PCIXAD28
PCIXAD29
PCIXAD30
PCIXAD31
PCI-X
40
Page 25 of 64
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 12 of 18)
Signal Name
Ball
H03
H01
L08
F01
D01
J05
Interface Group
Page
PCIXAD32
PCIXAD33
PCIXAD34
PCIXAD35
PCIXAD36
PCIXAD37
PCIXAD38
PCIXAD39
PCIXAD40
PCIXAD41
PCIXAD42
PCIXAD43
PCIXAD44
PCIXAD45
PCIXAD46
PCIXAD47
PCIXAD48
PCIXAD49
PCIXAD50
PCIXAD51
PCIXAD52
PCIXAD53
PCIXAD54
PCIXAD55
PCIXAD56
PCIXAD57
PCIXAD58
PCIXAD59
PCIXAD60
PCIXAD61
PCIXAD62
PCIXAD63
H05
G02
E02
C02
A08
G05
F03
D03
B03
H07
G04
E04
C04
A04
F05
D05
B05
C09
E06
C06
A06
F07
E07
D07
B07
E08
F14
E16
C19
F20
C08
C03
G09
F09
L23
E03
E13
A11
PCI-X
40
PCIXC0[BE0]
PCIXC1[BE1]
PCIXC2[BE2]
PCIXC3[BE3]
PCIXC4[BE4]
PCIXC5[BE5]
PCIXC6[BE6]
PCIXC7[BE7]
PCIXCap
PCI-X
40
PCI-X
PCI-X
PCI-X
PCI-X
40
40
40
40
PCIXClk
PCIXDevSel
PCIXFrame
Page 26 of 64
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 13 of 18)
Signal Name
Ball
E22
C22
N22
M18
R22
P19
G07
M07
E12
A14
L04
F16
A17
E24
E21
E20
R20
G23
R18
E09
M24
A18
L12
C12
Interface Group
Page
PCIXGnt0
PCIXGnt1[IRQ12]
PCIXGnt2
PCI-X
40
PCIXGnt3
PCIXGnt4
PCIXGnt5
PCIXIDSel
PCIXINT
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
40
40
40
40
40
40
40
PCIXIRDY
PCIXM66En
PCIXParHigh
PCIXParLow
PCIXPErr
PCIXReq0
PCIXReq1[IRQ11]
PCIXReq2
PCIXReq3
PCIXReq4
PCIXReq5
PCIXReq64
PCIXReset
PCIXSErr
PCI-X
40
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
40
40
40
40
40
PCIXStop
PCIXTRDY
Page 27 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 14 of 18)
Signal Name
Ball
D11
C11
B11
A12
A19
D18
E11
M03
N01
E14
C20
A16
A13
B14
C14
D14
B20
L15
L21
L22
M22
M01
L24
P24
T19
R24
U22
U24
N03
V20
V23
V21
T18
V19
W22
W24
C07
U18
Interface Group
Page
PerAddr00
PerAddr01
PerAddr02
PerAddr03
PerAddr04
PerAddr05
PerAddr06
PerAddr07
PerAddr08
PerAddr09
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
PerWBE0
PerWBE1
PerWBE2
PerWBE3
PerBLast
External Slave Peripheral
42
Note: PerAddr00 is the most significant bit (msb) on this bus.
External Slave Peripheral
42
External Slave Peripheral
External Master Peripheral
42
43
PerClk
Page 28 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 15 of 18)
Signal Name
Ball
E17
L10
V04
T24
L03
T03
L13
U03
H24
H22
H20
G20
G19
H18
J23
J22
J21
J20
J19
J18
J17
J15
J14
J13
J12
J11
J10
J09
L14
K24
K22
K20
K18
K16
K14
K11
K09
L19
L17
L16
P21
M09
Interface Group
Page
PerCS0
PerCS1
PerCS2
PerCS3
External Slave Peripheral
42
PerCS4
PerCS5
PerCS6
PerCS7
PerData00
PerData01
PerData02
PerData03
PerData04
PerData05
PerData06
PerData07
PerData08
PerData09
PerData10
PerData11
PerData12
PerData13
PerData14
PerData15
PerData16
PerData17
PerData18
PerData19
PerData20
PerData21
PerData22
PerData23
PerData24
PerData25
PerData26
PerData27
PerData28
PerData29
PerData30
PerData31
PerErr
External Slave Peripheral
42
Note: PerData00 is the most significant bit (msb) on this bus.
External Master Peripheral
External Slave Peripheral
43
42
PerOE
Page 29 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 16 of 18)
Signal Name
Ball
T23
T22
W20
U20
P05
N07
P02
AD07
N07
L02
Interface Group
Page
PerPar0
PerPar1
PerPar2
PerPar3
PerR/W
External Slave Peripheral
42
External Slave Peripheral
External Slave Peripheral
External Slave Peripheral
DDR SDRAM
42
42
42
41
45
45
PerReady[RcvrInh]
PerWE
RAS
[RcvrInh]PerReady
RefVEn
System
System
Reserved
L01
Reserved
46
Reserved
P04
U12
SV
DD
SV
U15
W10
DD
SV
DD
SV
W17
DD
SV
AA08
AA15
AC06
AC13
Power
46
DD
SV
DD
SV
DD
SV
DD
SV
AC21
G22
T02
P10
V22
Y24
Y22
M05
U01
AB22
N16
P17
T20
R05
T21
P23
N09
P08
T05
T04
P03
R07
P09
R09
DD
SysClk
System
System
System
JTAG
45
45
45
45
45
45
45
45
45
SysErr
SysReset
TCK
TDI
JTAG
TDO
JTAG
TestEn
System
System
JTAG
TmrClk
TMS
TrcBS0[GPIO18]
TrcBS1[GPIO19]
TrcBS2[GPIO20]
TrcClk
Trace
Trace
46
46
TrcES0[GPIO21]
TrcES1[GPIO22]
TrcES2[GPIO23]
TrcES3[GPIO24]
TrcES4[GPIO25]
TrcTS0[GPIO26]
TrcTS1[GPIO27]
TrcTS2[GPIO28]
TrcTS3[GPIO29]
TrcTS4[GPIO30]
Trace
46
Trace
Trace
Trace
Trace
Trace
46
46
46
46
46
Page 30 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 17 of 18)
Signal Name
Ball
T06
R01
N24
C13
Interface Group
Page
46
TrcTS5[GPIO31]
Trace
TrcTS6
Trace
46
TRST
JTAG
45
UART0_CTS
UART Peripheral
43
UART Peripheral
UART0_DCD
UART0_DSR
V24
V02
43
43
Note: Used as initialization strapping input.
UART Peripheral
Note: Used as initialization strapping input.
UART0_DTR
B18
H16
G16
G17
L11
G06
E05
C18
J16
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
43
43
43
43
43
43
43
43
43
43
UART0_RI
UART0_RTS
UART0_Rx
UART0_Tx
UART1_DSR/CTS[GPIO14]
UART1_RTS/DTR[GPIO15]
UART1_Rx[GPIO12]
UART1_Tx[GPIO13]
UARTSerClk
A09
Page 31 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 18 of 18)
Signal Name
Ball
B08
B15
D06
D13
D21
F04
Interface Group
Page
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
F12
F19
H02
H17
K12
K15
K23
M06
M10
M13
M21
N04
N12
N15
N19
R02
R10
R13
U08
U23
W06
W13
W21
AA04
AA12
AA19
AC10
AC17
Y05
Power
46
WE
DDR SDRAM
41
Page 32 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or
multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed
on those pins, look up the primary signal name in “Signals Listed Alphabetically” on page 15.
Signals Listed by Ball Assignment (Part 1 of 6)
Ball
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
Signal Name
Ball
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
Signal Name
Ball
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
Signal Name
No ball
Ball
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
Signal Name
PCIXAD36
OV
No ball
No ball
No ball
No ball
PCIXAD41
PCIXC5 *
DD
No ball
PCIXAD46
PCIXAD45
GND
OV
PCIXAD51
DrvrInh2
PCIXAD50
EMCTxErr *
PCIXAD57
PerBLast
DD
PCIXAD54
GND
PCIXAD53
V
PCIXAD58
EMCRxD2 *
PCIXAD42
UARTSerClk
PCIXAD05
PCIXFrame
PerAddr03
DD
PCIXAD62
PCIXAD61
GND
V
PCIXC4 *
DD
PCIXAD01
GND
PCIXAD55
PCIXAD04
PerAddr01
PCIXTRDY
PCIXAck64
OV
DD
PerAddr02
PerAddr00
GND
OV
DD
V
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
PerAddr12
PCIXM66En
PCIXAD09
PerAddr11
PCIXPErr
PCIXSErr
PerAddr04
PCIXAD21
PCIXAD22
No ball
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GND
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
UART0_CTS
PerAddr14
PCIXAD10
PCIXAD14
PCIXAD00
UART1_Rx *
PCIXC2 *
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
DD
PerAddr13
PerAddr15
GND
V
DD
PCIXAD13
GND
PCIXAD15
OV
DD
UART0_DTR
PerAddr05
GND
OV
DD
PerAddr16
GND
PerAddr10
PCIXAD23
PCIXGnt1 *
PCIXAD28
No ball
PCIXAD20
V
DD
PCIXAD25
No ball
PCIXAD30
GND
No ball
No ball
No ball
PCIXAD31
Page 33 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment (Part 2 of 6)
Ball
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
Signal Name
Ball
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
Signal Name
Ball
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
Signal Name
Ball
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
Signal Name
PCIXAD33
APV for PCI PLL
EMCRxD1 *
PCIXAD35
DD
V
PCIXAD40
PCIXClk
GND
PCIXAD39
EMCRxD0 *
PCIXAD48
PCIXAD43
UART1_DSR/CTS *
PCIXIDSel
PCIX133Cap
PCIXC6 *
DD
PCIXAD44
PCIXAD32
GND
V
PCIXAD49
UART1_RTS/DTR *
PCIXAD56
PCIXAD60
PCIXAD63
PCIXReq64
PCIXAD03
PerAddr06
PCIXIRDY
PCIXDevSel
PerAdd09
DD
PCIXAD52
GND
PCIXAD38
OV
DD
PCIXAD59
PCIXAD47
GND
OV
DD
PCIXC7 *
GND
EMCRxD3 *
OV
PCIXAD02
IIC0SClk
DD
PCIXAD06
IIC1SClk *
GND
V
PCIXAD07
IIC0SDA
DD
OV
GND
DD
PCIXC0 *
PCIXAD08
PCIXAD12
UART0_RTS
UART0_Rx
PCIXAD19
PerData04
PerData03
PCIXAD26
SysClk
IIC1SDA *
GND
OV
PCIXAD11
PCIXC1 *
DD
PCIXParLow
GND
UART0_RI
V
PerCS0
DD
PCIXAD16
PCIXAD17
PCIXReq2
PCIXReq1 *
PCIXGnt0
PCIXAD27
PCIXAD18
PerData05
GND
V
DD
PCIXC3 *
GND
PerData02
OV
DD
PCIXAD24
PerData01
GND
OV
PCIXReq4
DD
ASV for SysClk
PLL
DD
E24
PCIXReq0
F24
PCIXAD29
G24
H24
PerData00
Page 34 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment (Part 3 of 6)
Ball
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
Signal Name
Ball
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
Signal Name
Ball
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
Signal Name
Reserved
Ball
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
Signal Name
PerAddr21
OV
AGND
EMCRxDV *
EMCRxClk
EMCTxD3 *
EMCTxD2 *
PCIXAD37
EMCTxClk *
EMCCD *
EMCMDClk
PerData19
PerData18
PerData17
PerData16
PerData15
PerData14
PerData13
UART1_Tx *
PerData12
PerData11
PerData10
PerData9
GND
RefVEn
DD
EMCRxErr *
PerCS4
PerAddr07
GND
OV
PCIXParHigh
EMCMDIO
EMCTxEn *
DrvrInh1
DD
EMCTxD1 *
GND
TestEn
V
DD
EMCCrS *
PCIXINT
GND
OV
PCIXAD34
EMCTxD0 *
PerCS1
DD
PerData28
GND
PerOE
V
DD
PerData27
UART0_Tx
PCIXStop
PerCS6
DMAReq1
GND
V
DD
V
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
GND
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
DD
PerData26
PerData20
PerAddr17
PerData31
PerData30
IRQ03 *
IRQ06 *
GND
V
DD
PerData25
GND
EOT3/TC3
OV
DD
PerData24
PCIXGnt3
GND
OV
PerData29
IRQ01 *
DD
PerData23
GND
IRQ05 *
V
PerData8
PerAddr18
PerAddr19
PCIXCap
PerAddr22
DD
PerData7
PerData22
PerAddr20
GND
V
PerData6
DD
AGND
PerData21
PCIXReset
Page 35 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment (Part 4 of 6)
Ball
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
Signal Name
Ball
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
Signal Name
Ball
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
Signal Name
TrcTS6
Ball
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
Signal Name
DQS7
PerAddr08
DMAReq3
V
GND
PerWE
SysErr
DD
PerAddr28
TrcTS1 *
Reserved
PerR/W
DMAReq0
GND
PerCS5
V
TrcTS0 *
DD
DMAAck0
GND
TrcClk
TrcES4 *
TrcTS5 *
OV
DMAAck2
DMAAck1
TrcES3 *
TrcTS3 *
SysReset
DMAAck3
MemData28
DM3
DD
PerReady *
TrcTS2 *
GND
MemData61
MemData56
MemVRef2
MemData38
MemData37
MemData35
MemData22
MemVRef1
MemData18
DM0
OV
DD
TrcES2 *
GND
TrcTS4 *
V
DD
DMAReq2
MemData42
GND
V
DD
V
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
GND
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
DD
IRQ04 *
GPIO11
MemData14
GND
V
EOT1/TC1
EOT2/TC2
TrcBS1 *
IRQ07 *
DD
TrcBS0 *
GND
EOT0/TC0
OV
ExtReset
PerWBE0
PerAddr24
TrcBS2 *
TrcES0 *
PerPar1
DD
IRQ00 *
PCIXReq5
GND
V
PCIXGnt5
IRQ02 *
DD
IRQ08 *
GND
PCIXReq3
OV
PerErr
DD
PCIXGnt2
IRQ09 *
PCIXGnt4
GND
OV
TrcES1 *
PerAddr23
PerPar0
DD
TRST
PerAddr25
PerCS3
Page 36 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment (Part 5 of 6)
Ball
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
Signal Name
Ball
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
Signal Name
Ball
W01 MemData58
OV
Signal Name
Ball
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Signal Name
MemData51
TmrClk
MemData55
GND
UART0_DSR
DM7
W02
MemData53
DM6
DD
PerCS7
W03 MemData59
W04 GND
OV
PerCS2
DQS6
DD
MemData63
GND
Halt
W05 MemData62
WE
V
MemData60
MemData54
MemClkOut0
MemClkOut0
MemAddr12
MemAddr9
MemData31
MemAddr8
MemData26
MemData19
MemData09
MemData05
IRQ10 *
W06
MemData46
MemData43
MemData47
ClkEn2
DD
MemData57
W07 ECC3
W08 GND
W09 ClkEn3
V
DD
ECC4
SV
GND
W10
MemData34
MemAddr11
MemData30
MemData27
MemAddr7
MemData23
MemData20
MemData10
MemData13
MemAddr00
MemAddr02
HoldAck
DD
MemData36
W11 MemData32
W12 GND
SV
DD
V
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
GND
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
W13
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
DD
MemData21
W14 BankSel1
W15 GND
SV
DD
MemData04
GND
W16 MemAddr10
SV
W17
DD
PerClk
W18 MemData08
W19 GND
OV
PerWBE1
PerAddr29
PerAddr31
TCK
DD
PerPar3
GND
W20 PerPar2
V
W21
DD
PerAddr26
W22 PerWBE2
W23 GND
TDO
V
PerAddr30
UART0_DCD
HoldReq
DD
PerAddr27
W24 PerWBE3
TDI
Page 37 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment (Part 6 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
AA01 MemData48
AA02 GND
AB01 No ball
AC01 No ball
AC02 No ball
AC03 ECC5
AC04 GND
AC05 DM8
AD01 No ball
AD02 No ball
AD03 No ball
AD04 ECC7
AB02 MemData50
AB03 MemData52
AB04 ECC6
AA03 MemData49
V
AA04
DD
AA05 DQS8
AA06 GND
AA07 DM5
AB05 CAS
AD05 BankSel3
AD06 ECC2
SV
AB06 ECC1
AC06
DD
AB07 ECC0
AC07 MemData44
AC08 GND
AD07 RAS
SV
AA08
AB08 MemData40
AB09 MemData45
AB10 ClkEn1
AD08 MemData41
AD09 BA1
DD
AA09 DM4
AA10 GND
AC09 DQS5
V
AC10
AD10 MemData39
DD
AMV for MemClk
PLL
DD
AA11 AGND
AB11
AC11 DQS4
AC12 GND
AD11 BankSel2
V
AA12
AB12 MemData29
AB13 DQS3
AD12 MemData33
AD13 MemData24
AD14 MemData25
AD15 MemData17
AD16 MemAddr5
AD17 ClkEn0
DD
SV
AA13 GND
AC13
DD
AA14 MemData16
AB14 DM2
AC14 DQS2
AC15 GND
AC16 DQS1
SV
AA15
AB15 BankSel0
AB16 MemData11
AB17 MemData15
AB18 MemAddr6
AB19 MemData07
AB20 MemAddr3
AB21 MemData01
AB22 TMS
DD
AA16 BA0
AA17 GND
AA18 DM1
V
AC17
DD
AC18 MemData12
AC19 GND
AD18 MemAddr4
AD19 MemData06
AD20 MemAddr01
AD21 MemData00
AD22 No ball
V
AA19
DD
AA20 MemData03
AA21 GND
AC20 DQS0
SV
AC21
DD
AA22 ExtAck
AC22 MemData02
AC23 No ball
OV
AA23
AB23 ExtReq
AD23 No ball
DD
AA24 BusReq
AB24 No ball
AC24 No ball
AD24 No ball
Page 38 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Description
The PPC440GP embedded controller is packaged in a 552-ball ceramic ball grid array (CBGA). The following
tables describes the package level pinout.
Pin Summary
Group
No. of Pins
Signal pins, non-multiplexed
Signal pins, multiplexed
Total Signal Pins
347
57
404
3
AxV
DD
AGnd
3
OV
27
DD
SV
9
DD
V
34
70
DD
Gnd
Total Power Pins
Reserved
146
2
Total Pins
552
In the table “Signal Functional Description” on page 40, each I/O signal is listed along with a short description
of its function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed
Alphabetically” on page 15 for the pin (ball) number to which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most
cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed
on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the
name in “Signals Listed Alphabetically” on page 15. It is expected that in any single application a particular
pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip
to offer a richer pin selection than would otherwise be possible.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller
address pins (PerAddr00:31) are used as outputs by the PPC440GP to broadcast an address to external
slave devices when the PPC440GP has control of the external bus. When during the course of normal chip
operation an external master gains ownership of the external bus, these same pins are used as inputs which
are driven by the external master and received by the EBC in the PPC440GP. In this example, the pins are
also bidirectional, serving both as inputs and outputs.
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When
a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are
shown.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Strapping” on page 61). Note
that these are not multiplexed pins since the function of the pins is not programmable.
Page 39 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 1 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
PCI-X Interface
Description
I/O
Type
Notes
PCIXAD00:63
Address/Data bus (bidirectional).
PCI-X Command[Byte Enables].
I/O
I/O
3.3V PCI
3.3V PCI
PCIXC0:7[BE0:7]
5V tolerant
3.3V LVTTL
PCIXCap
Capable of PCI-X operation.
I
5
PCIX133Cap
PCIXClk
PCI-X devices are 133 MHz capable.
I
I
3.3V PCI
3.3V PCI
Provides timing to the PCI interface for PCI transactions.
Indicates the driving device has decoded its address as
the target of the current access.
PCIXDevSel
PCIXFrame
PCIXGnt0
I/O
I/O
I/O
I/O
O
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Driven by the current master to indicate beginning and
duration of an access.
Indicates that the specified agent is granted access to
the bus.
Indicates that the specified agent is granted access to
the bus.
PCIXGnt1
Indicates that the specified agent is granted access to
the bus.
PCIXGnt2:5
Used as a chip select during configuration read and
write transactions.
PCIXIDSel
PCIXINT
I
3.3V PCI
3.3V PCI
3.3V PCI
Level sensitive PCI interrupt.
O
Indicates initiating agent’s ability to complete the current
data phase of the transaction.
PCIXIRDY
I/O
5V tolerant
3.3V LVTTL
PCIXM66En
Capable of 66MHz operation.
I
PCIXParHigh
PCIXParLow
Even parity across PCIAD32:63 and PCIXC0:3[BE4:7].
Even parity across PCIAD0:31 and PCIXC0:3[BE0:3].
I/O
I/O
3.3V PCI
3.3V PCI
Reports data parity errors during all PCI transactions
except a Special Cycle.
PCIXPErr
I/O
I/O
I
3.3V PCI
3.3V PCI
3.3V PCI
An indication to the PCI-X arbiter that the specified
agent wishes to use the bus.
PCIXReq0
PCIXReq1:5
An indication to the PCI-X arbiter that the specified
agent wishes to use the bus.
Asserted by the current bus master, indicating a 64-bit
transfer.
PCIXReq64
PCIXAck64
PCIXReset
I/O
I/O
O
3.3V PCI
3.3V PCI
3.3V PCI
Indicates the target can transfer data using 64 bits.
Brings PCI device registers and logic to a consistent
state.
Page 40 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 2 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system
errors.
PCIXSErr
I/O
3.3V PCI
Indicates the current target is requesting the master to
stop the current transaction.
PCIXStop
I/O
I/O
3.3V PCI
3.3V PCI
Indicates the target agent’s ability to complete the
current data phase of the transaction.
PCIXTRDY
DDR SDRAM Interface
BA0:1
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
O
O
O
O
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
BankSel0:3
CAS
ClkEn0:3
Clock Enable. One for each bank.
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
DM0:8
O
2.5V SSTL_2
2.5V SSTL_2
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane.
DQS0:8
I/O
ECC0:7
ECC check bits 0:7.
Memory address bus.
I/O
O
2.5V SSTL_2
2.5V SSTL_2
MemAddr00:12
MemClkOut0
MemClkOut0
Subsystem clock.
Memory data bus.
O
I/O
I
2.5V SSTL_2
2.5V SSTL_2
MemData00:63
MemVRef1:2
Voltage Ref
Receiver
Memory reference voltage (SV
) input.
REF
RAS
Row Address Strobe.
Write Enable.
O
O
2.5V SSTL_2
2.5V SSTL_2
WE
Ethernet Interface
EMCCD,
EMC1RxErr
MII: Collision detection
RMII 1: Receive error
5V tolerant
3.3V LVTTL
I/O
I/O
O
EMCCrS,
EMC0CrSDV
MII: Carrier sense
RMII 0: Carrier sense data valid
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
EMCMDClk
EMCMDIO
MII and RMII: Management data clock
MII and RMII: Transfer command and status information
between MII and PHY
5V tolerant
3.3V LVTTL
I/O
EMCRxD0:3,
EMC0RxD0:1,
EMC1RxD0:1,
EMC0RxD,
MII: Receive data
RMII 0: Receive data
RMII 1: Receive data
SMII 0: Receive data
SMII 1: Receive data
5V tolerant
3.3V LVTTL
I/O
EMC1RxD
Page 41 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 3 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
EMCRxDV,
Description
MII: Receive data valid
I/O
Type
Notes
5V tolerant
3.3V LVTTL
I
EMC1CrSDV
RMII 1: Carrier sense data valid
5V tolerant
3.3V LVTTL
EMCRxClk
MII: Receive clock
I
I
I
EMCRxErr,
EMC0RxErr
MII: Receive error
RMII 0: Receive error
5V tolerant
3.3V LVTTL
EMCTxClk,
EMCRefClk
MII: Transmit clock
RMII and SMII: Transmit clock
5V tolerant
3.3V LVTTL
EMCTxD0:3,
EMC0TxD0:1,
EMC1TxD0:1,
EMC0TxD,
MII: Transmit data
RMII 0: Transmit data
RMII 1: Transmit data
SMII 0: Transmit data
SMII 1: Transmit data
5V tolerant
3.3V LVTTL
O
EMC1TxD
EMCTxEn,
EMC0TxEn,
EMCSync
MII: Transmit data enabled
RMII 0: Transmit data enabled
SMII: Sync signal
5V tolerant
3.3V LVTTL
O
O
EMCTxErr,
EMC1TxEn
MII: Transmit error:
RMII : Transmit data enabled
5V tolerant
3.3V LVTTL
External Slave Peripheral Interface
Used by the PPC440GP to indicate that data transfers
have occurred.
5V tolerant
3.3V LVTTL
DMAAck0:3
O
I
Used by slave peripherals to indicate they are prepared
to transfer data.
5V tolerant
3.3V LVTTL
DMAReq0:3
1, 5
1, 5
5V tolerant
3.3V LVTTL
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
Peripheral address bus used by PPC440GP when not in
external master mode, otherwise used by external
master.
5V tolerant
3.3V LVTTL
PerAddr00:31
I/O
1
Note: PerAddr00 is the most significant bit (msb) on this
bus.
5V tolerant
3.3V LVTTL
PerWBE0:3
PerBLast
External peripheral data bus byte enables.
I/O
I/O
O
1, 2
1, 4
2
Used by either the peripheral controller, DMA controller,
or external master to indicates the last transfer of a
memory access.
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
PerCS0:7
External peripheral device select.
Peripheral data bus used by PPC440GP when not in
external master mode, otherwise used by external
master.
5V tolerant
3.3V LVTTL
PerData00:31
I/O
1
Note: PerData00 is the most significant bit (msb) on this
bus.
Page 42 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 4 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440GP is the bus master, it enables the selected
DDR SDRAMs to drive the bus.
5V tolerant
3.3V LVTTL
PerOE
O
2
5V tolerant
3.3V LVTTL
PerPar0:3
PerReady
External peripheral data bus byte parity.
I/O
I
1
Used by a peripheral slave to indicate it is ready to
transfer data.
5V tolerant
3.3V LVTTL
Used by the PPC440GP when not in external master
mode, as output by either the peripheral controller or
DMA controller depending upon the type of transfer
involved. High indicates a read from memory, low
indicates a write to memory.
5V tolerant
3.3V LVTTL
PerR/W
PerWE
I/O
1, 2
Otherwise, it used by the external master as an input to
indicate the direction of transfer.
Write Enable. Low when any of the four PerWBE0:3
signals are low.
5V tolerant
3.3V LVTTL
O
O
2
External Master Peripheral Interface
Bus Request. Used when the PPC440GP needs to
regain control of peripheral interface from an external
master.
5V tolerant
3.3V LVTTL
BusReq
External Acknowledgement. Used by the PPC440GP to
indicate that a data transfer occurred.
5V tolerant
3.3V LVTTL
ExtAck
O
I
External Request. Used by an external master to
indicate it is prepared to transfer data.
5V tolerant
3.3V LVTTL
ExtReq
ExtReset
HoldAck
HoldReq
PerClk
1, 4
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
O
O
I
Hold Acknowledge. Used by the PPC440GP to transfer
ownership of peripheral bus to an external master.
5V tolerant
3.3V LVTTL
Hold Request. Used by an external master to request
ownership of the peripheral bus.
5V tolerant
3.3V LVTTL
1, 5
1, 5
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
O
I/O
External Error. Used as an input used to record external
master errors and external slave peripheral errors.
5V tolerant
3.3V LVTTL
PerErr
UART Peripheral Interface
Serial clock input that provides an alternative to the
internally generated serial clock. Used in cases where
the allowable internally generated clock rates are not
satisfactory. This input can be individually connected to
either or both UART0 and UART1.
5V tolerant
3.3V LVTTL
UARTSerClk
UART0_Rx
I
I
1, 4
1, 4
5V tolerant
3.3V LVTTL
UART0 Receive data.
Page 43 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 5 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
UART0 Transmit data.
I/O
Type
Notes
5V tolerant
3.3V LVTTL
UART0_Tx
O
4
5V tolerant
3.3V LVTTL
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
I
I
6
5V tolerant
3.3V LVTTL
6
5V tolerant
3.3V LVTTL
I
1, 4
4
5V tolerant
3.3V LVTTL
O
O
I
5V tolerant
3.3V LVTTL
4
5V tolerant
3.3V LVTTL
1, 4
1, 4
1, 4
1, 4
1, 4
5V tolerant
3.3V LVTTL
UART1_Rx
UART1 Receive data.
I/O
I/O
I/O
I/O
5V tolerant
3.3V LVTTL
UART1_Tx
UART1 Transmit data.
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
UART1_DSR/CTS
UART1 Request To Send or Data Terminal Ready. The
choice is determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
UART1_RTS/DTR
IIC Peripheral Interface
IIC0SClk
5V tolerant
3.3V LVTTL
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
I/O
I/O
I/O
I/O
1, 2
1, 2
1, 2
1, 2
5V tolerant
3.3V LVTTL
IIC0SDA
IIC1SClk
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
IIC1SDA
Interrupts Interface
IRQ00:10
5V tolerant
3.3V LVTTL
External interrupt Requests 0 through 10.
External interrupt Requests 11 through 12.
I
I
1, 5
IRQ11:12
3.3V PCI
Page 44 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 6 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
JTAG Interface
Description
I/O
Type
Notes
3.3V CMOS
w/pull-up
TCK
Test Clock.
I
1
4
3.3V CMOS
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V CMOS
w/pull-up
1
5
3.3V CMOS
w/pull-up
TRST
Test Reset.
I
System Interface
SysClk
5V tolerant
3.3V LVTTL
Main system clock input.
Clock
O
5V tolerant
3.3V LVTTL
SysErr
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this
bidirectional pin low (minimum of 16 cycles) to initiate a
system reset. A system reset can also be initiated by
software. Implemented as an open-drain output (two
states; 0 or open circuit).
5V tolerant
3.3V LVTTL
SysReset
I/O
1, 2
5V tolerant
3.3V LVTTL
TmrClk
Halt
Processor timer external input clock.
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
I
1, 4
General purpose I/O 0 through 10. To access these
functions, software must set DCR register bits.
5V tolerant
3.3V LVTTL
GPIO00:31
TestEn
I/O
1.8V CMOS
w/pull-down
Test Enable.
I
I
I
I
3
5V tolerant
3.3V LVTTL
RcvrInh
RefVEn
DrvrInh1:2
Receiver Inhibit. Active only when TestEn is active.
Reference Voltage Enable. Used for wafer testing. Do
not connect for normal operation.
1.8V CMOS
w/pull-down
Driver Inhibit. Used for test purposes only. Tie up for
normal operation
5V tolerant
3.3V LVTTL
2
Page 45 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 7 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Trace Interface
Description
I/O
Type
Notes
5V tolerant
3.3V LVTTL
TrcBS0:2
TrcClk
Trace branch execution status.
I/O
O
Trace data capture clock, runs at 1/4 the frequency of
the processor.
5V tolerant
3.3V LVTTL
Trace Execution Status is presented every fourth
processor clock cycle.
5V tolerant
3.3V LVTTL
TrcES0:4
TrcTS0:6
I/O
I/O
Additional information on trace execution and branch
status.
5V tolerant
3.3V LVTTL
Power Pins
AGND
PLL (analog) voltage ground.
Ground.
n/a
n/a
n/a
n/a
GND
1.8V—Filtered voltages input for PLLs (analog circuits)
AxV
n/a
n/a
Note: A separate filter for each of the three voltages is
DD
recommended.
OV
3.3V supply—I/O (except DDR SDRAM)
2.5V supply—DDR SDRAM
n/a
n/a
n/a
n/a
n/a
n/a
DD
SV
DD
V
1.8V supply—Logic voltage.
DD
Reserved Pins
Do not connect signals, voltage, or ground to these
balls.
Reserved
n/a
n/a
Page 46 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed
when operating at these maximum ratings.
Characteristic
Supply Voltage (Internal Logic)
Supply Voltage (I/O Interface, except DDR SDRAM)
PLL Supply Voltages
Symbol
Value
Unit
Notes
V
0 to +1.95
0 to +3.6
0 to +1.95
0 to +2.7
0 to +3.6
0 to +5.5
-55 to +150
-40 to +120
V
1
1
2
DD
OV
V
DD
AxV
V
DD
SV
Supply Voltage (DDR SDRAM Logic)
Input Voltage (3.3V LVTTL receivers)
Input Voltage (5.0V LVTTL receivers)
Storage Temperature Range
Case temperature under bias
Notes:
V
DD
V
V
IN
V
V
IN
T
°C
°C
STG
T
C
1. If OV ≤ 0.4V it is required that V ≤ 0.4V. Supply excursions not meeting this criteria must be limited to less than 25ms
DD
DD
duration during each power up or power down event.
2. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440GP. A separate filter, as shown below, is recommended for each voltage :
AxV
V
DD
DD
L
L – SMT ferrite bead chip, Murata BLM31A700S
C
C – 0.1µF ceramic
Package Thermal Specifications
Thermal resistance values for the CBGA package in a convection environment are as follows:
Airflow
ft/min (m/sec)
Parameter
Symbol
Unit
Notes
0 (0)
100 (0.51)
200 (1.02)
Junction-to-case thermal resistance
θJC
θCA
<0.1
<0.1
17.7
<0.1
°C/W
°C/W
Case-to-ambient thermal resistance (w/o heat sink)
18.9
16.3
Notes:
1. Case temperature, T , is measured at top center of case surface with device soldered to circuit board.
C
2. T = T - P×θCA, where T is ambient temperature and P is power consumption.
A
C
A
3. TCMax = TJMax - P×θJC, where TJMax is maximum junction temperature and P is power consumption.
4. The preceding equations assume that the chip is mounted on a card with at least one signal and two power planes.
Page 47 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Heat Sink Mounting Information
Proper thermal design is primarily dependent upon multiple system-level effects; that is, the effects of the
heat sink, the air flow, and the thermal interface material. To reduce the die-junction temperature, heat sinks
may be attached to the package by several methods: adhesive, spring clips to the printed-circuit board or
package, or a mounting clip and screw assembly. When attaching heat sinks, it is important to avoid placing
excessive mechanical stress on bonding of the chip to the substrate and the package to the board.
Heat Sink Attached With Spring Clip
Heat sink
Heat sink
Heat sink clip
Heat sink clip
Thermal grease
Thermal grease
CBGA
CBGA
package
package
Printed
circuit
board
Printed
circuit
board
Spring clip to package
Spring clip to board
1
Static compression (spring force)—2.27kg maximum
Static compression (spring force)—2.27kg maximum
Note 1: Force is limited by allowable compression on the die.
Allowable package compression force is 4.4kg.
Heat Sink Attached With Adhesive
Heat sink
Adhesive
Printed
circuit
board
CBGA
CBGA
package
package
Adhesive
Printed
circuit
board
Heat sink
Weight
force
Weight
force
Heat sink weight force—60g maximum
Important: All of the guidelines indicated in the above diagrams must be evaluated and adjusted to account
for the shock and vibration effects of any particular application.
Page 48 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
+1.7
Typical
+1.8
Maximum
+1.9
Unit
V
Notes
2, 4
2, 4
2, 4
3
V
Logic Supply Voltage
I/O Supply Voltage
DD
OV
+3.0
+3.3
+3.6
V
DD
SV
DDR SDRAM Supply Voltage
+2.3
+2.5
+2.7
V
DD
AxV
PLL Supply Voltages
+1.65
+1.15
+1.8
+1.95
+1.35
V
DD
SV
DDR SDRAM Reference Voltage
+1.25
V
3
REF
SV
+0.18
SV +0.3
Input Logic High (2.5V SSTL)
V
REF
DD
0.5OV
OV +0.5
Input Logic High (3.3V PCI-X)
V
1
1
1
1
DD
DD
V
IH
Input Logic High (3.3V LVTTL, 5V tolerant receiver)
Input Logic Low (2.5V SSTL)
+2.0
-0.3
+5.5
V
SV
-0.18
V
REF
0.35OV
Input Logic Low (3.3V PCI-X)
-0.5
V
DD
V
IL
Input Logic Low (3.3V LVTTL, 5V tolerant receiver)
Output Logic High (2.5V SSTL)
0
+0.8
SV
V
+1.95
0.9OV
V
DD
DD
DD
OV
OV
Output Logic High (3.3V PCI-X)
V
DD
V
OH
Output Logic High (3.3V LVTTL, 5V tolerant receiver)
Output Logic Low (2.5V SSTL)
+2.4
0
V
0.55
V
0.1OV
Output Logic Low (3.3V PCI-X)
V
DD
V
I
OL
Output Logic Low (3.3V LVTTL, 5V tolerant receiver)
Input Leakage Current (No pull-up or pull-down)
0
0
+0.4
0
V
µA
IL1
IL2
IL3
I
I
Input Leakage Current for Pull-Down
Input Leakage Current for Pull-Up
0 (LPDL)
-150 (LPDL)
200 (MPUL)
0 (MPUL)
µA
µA
Input Max Allowable Overshoot (3.3V LVTTL,
5V tolerant receiver)
V
+5.5
V
V
V
V
IMAO
IMAU
Input Max Allowable Undershoot (3.3V LVTTL,
5V tolerant receiver)
V
-0.6
Output Max Allowable Overshoot (3.3V LVTTL,
5V tolerant receiver)
V
+5.5
OMAO
Output Max Allowable Undershoot (3.3V LVTTL,
5V tolerant receiver)
V
-0.6
OMAU3
T
C Case Temperature (up to 500MHz)
-40
-40
+85
°C
°C
C
T
E Case Temperature (400MHz only)
Notes:
+105
C
1. PCI-X drivers meet PCI-X specifications.
2. SV
= SV /2
DD
REF
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440GP. See “Absolute Maximum Ratings” on page 47.
4. Startup sequencing of the power supply voltages is not required.
Page 49 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Input Capacitance
Parameter
Symbol
Maximum
Unit
pF
Notes
C
Group 1 (2.5V SSTL I/O)
Group 2 (5V tolerant LVTTL I/O)
Group 3 (PCI-X I/O)
12
12
12
9
IN1
C
pF
IN2
C
pF
IN3
C
Group 4 (Receivers)
pF
IN4
DC Power Supply Loads
Parameter
Symbol
Minimum
Typical
915
Maximum
Unit
mA
mA
mA
V
(1.8V) active operating current
I
DD
DD
OV (3.3V) active operating current
I
125
DD
ODD
SV (2.5V) active operating current
I
560
DD
SDD
1
I
33
mA
AxV (1.8 V) input current
ADD
DD
Notes:
1. See “Absolute Maximum Ratings” on page 47 for filter recommendations.
Test Conditions
Output
Pin
Clock timing and switching characteristics are specified in accordance with
operating conditions shown in the table “Recommended DC Operating
Conditions.” AC specifications are characterized with VDD = 1.8V, TC = rated
50pF
temperature and a 50pF test load as shown in the figure to the right.
Page 50 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Clocking Specifications
Symbol
Parameter
Min
Max
Units
SysClk Input
F
Frequency
Period
33.33
66.66
30
MHz
ns
C
T
15
C
T
Edge stability
High time
Low time
–
0.15
ns
CS
T
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
CH
T
ns
CL
Note: Input slew rate ≥ 1V/ns
MemClkOut
F
T
Frequency
Period
100
7.5
133.33
10
MHz
ns
C
C
T
High time
35% of nominal period
65% of nominal period
ns
CH
PLL VCO
F
Frequency
Period
500
1
1000
2
MHz
ns
C
T
C
Processor Clock
F
Frequency
Period
–
2
500
–
MHz
ns
C
T
C
Timing Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
Page 51 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440GP. This
controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG
is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew
there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When
using an SSCG with the PPC440GP the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC440GP with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board PPC440GP peripherals impose more stringent requirements.
• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks
the modulation.
• Use the DDR SDRAM MemClkOut since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes
that the connected device is running at precise baud rates.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Important: It is up to the system designer to ensure that any SSCG used with the PPC440GP meets the
above requirements and does not adversely affect other aspects of the system.
Page 52 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
–
Max
133.33
–
Units
MHz
ns
Notes
2
PCIXClk input frequency (asynchronous mode)
PCIXClk period (asynchronous mode)
PCIXClk input high time
7.5
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
PCIXClk input low time
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII(RMII)
EMCTxClk period MII(RMII)
EMCTxClk input high time
160
–
ns
160
–
ns
2.5(5)
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
–
ns
EMCTxClk input low time
35% of nominal period
–
ns
EMCRxClk input frequency MII(RMII)
EMCRxClk period MII(RMII)
EMCRxClk input high time
2.5(5)
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
–
–
ns
EMCRxClk input low time
35% of nominal period
ns
PerClk output frequency (for ext. master or sync. slaves)
PerClk period
–
66.66
–
MHz
ns
15
PerClk output high time
50% of nominal period 66% of nominal period
ns
PerClk output low time
33% of nominal period 50% of nominal period
ns
1
UARTSerClk input frequency)
UARTSerClk period
–
MHz
ns
1
1
1
1
1000/(2T
+2ns)
OPB
2T
T
+2
–
OPB
+1
UARTSerClk input high time
–
–
ns
OPB
T
+1
UARTSerClk input low time
TmrClk input frequency
TmrClk period
ns
MHz
ns
OPB
–
100
10
–
TmrClk input high time
TmrClk input low time
Notes:
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
ns
1. T
is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The
OPB
maximum OPB clock frequency is 66.66 MHz.
2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk is 66.66MHz.
Page 53 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Input Setup and Hold Waveform
Clock
T
min
IS
T
min
IH
Inputs
Valid
Output Delay and Float Timing Waveform
Clock
max
min
max
min
max
min
T
T
T
OV
OV
OV
T
T
T
Outputs
OH
OH
OH
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
Page 54 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—All Speeds (Part 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz
and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
PCI-X Interface
PCIXAD31:00
PCIXC3:0[BE3:0]
PCIXParLow
PCIParHigh
PCIXFrame
PCIXINT
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
n/a
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
n/a
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
dc
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
dc
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
n/a
0.5
0.5
n/a
n/a
0.5
0.5
n/a
n/a
n/a
n/a
0.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
n/a
1.5
1.5
n/a
n/a
1.5
1.5
n/a
n/a
n/a
n/a
1.5
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
2
2
2
2
2
async
PCIXIRDY
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
dc
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
dc
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
n/a
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
n/a
2
PCIXTRDY
PCIXStop
2
2
PCIXDevSel
PCIXIDSel
2
2
2
PCIXPErr
3.8 (6)
3.8 (6)
n/a
0.7 (Note 2)
0.7 (Note 2)
n/a
PCIXSErr
2
PCIXClk
async
PCIXReset
PCIXReq64
PCIXAck64
PCIXCap
n/a
n/a
n/a
n/a
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
n/a)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
n/a
3.8 (6)
3.8 (6)
n/a
0.7 (Note 2)
0.7 (Note 2)
n/a
2
2
2
2
2
2
2
PCIX133Cap
PCIXM66En
PCIXReq0:5
PCIXGnt0:5
Ethernet MII Interface
EMCRxD0:3
EMCRxDV
n/a
n/a
n/a
n/a
n/a
n/a
3.8 (6)
0.7 (Note 2)
4
1
n/a
n/a
n/a
n/a
15
n/a
n/a
n/a
n/a
2
n/a
n/a
n/a
n/a
n/a
n/a
7.1
7.1
n/a
7.1
n/a
n/a
7.1
7.1
EMCRxClk
EMCRxClk
1
4
1
1
EMCRxClk
n/a
4
n/a
1
n/a
1, async
EMCRxErr
n/a
EMCRxClk
EMCTxClk
EMCTxClk
1
EMCTxD0:3
EMCTxEn
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10.3
10.3
n/a
1
1
15
2
EMCTxClk
n/a
15
n/a
2
1, async
1
EMCTxErr
10.3
n/a
EMCTxClk
EMCMDClk
EMCCrS
n/a
n/a
n/a
n/a
1, async
1, async
1
EMCCD
n/a
EMCMDIO
10.3
10.3
EMCMDClk
Ethernet RMII Interface
EMC0RxD0:1
EMC0RxErr
EMC0CrSDV
EMC0TxD0:1
EMC0:1TxEn
n/a
n/a
n/a
n/a
1, async
2
2
1
1
n/a
n/a
n/a
11
n/a
n/a
n/a
2
n/a
n/a
n/a
n/a
n/a
7.1
7.1
EMCRxClk
EMCRxClk
EMCRxClk
EMCTxClk
EMCTxClk
n/a
n/a
n/a
n/a
n/a
10.3
10.3
11
2
Page 55 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—All Speeds (Part 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz
and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
EMC1RxD0:1
EMC1RxErr
n/a
n/a
n/a
11
n/a
n/a
n/a
2
10.3
n/a
7.1
n/a
n/a
7.1
7.1
EMCRxClk
EMCRxClk
EMCRxClk
EMCTxClk
EMC1CrSDV
EMC1TxD0:1
EMCRefClk
n/a
n/a
n/a
n/a
n/a
10.3
10.3
n/a
n/a
async
Ethernet SMII Interface
EMC0:1RxD
0.8
n/a
0.8
n/a
n/a
6.2
na/
2
10.3
10.3
7.1
7.1
EMCTxClk
EMCTxClk
EMC0:1TxD
Internal Peripheral Interface
IICxSClk
n/a
n/a
n/a
n/a
n/a
n/a
15.3
15.3
n/a
10.2
10.2
n/a
n/a
7.1
n/a
n/a
n/a
7.1
n/a
7.1
n/a
7.1
n/a
7.1
IICxSDA
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RI
UART0_RTS
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_RTS/DTR
Interrupts Interface
IRQ00:12
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10.3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10.3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10.3
n/a
10.3
n/a
10.3
n/a
n/a
JTAG Interface
TDI
n/a
n/a
n/a
n/a
async
async
async
async
async
TMS
TDO
15.3
n/a
10.2
n/a
TCK
TRST
n/a
n/a
System Interface
SysClk
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
7.1
n/a
n/a
7.1
TmrClk
async
async
async
async
async
SysReset
n/a
Halt
n/a
n/a
n/a
SysErr
n/a
n/a
10.3
n/a
TestEn
n/a
n/a
n/a
n/a
DrvrInh1:2
GPIO00:31
n/a
10.3
Page 56 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—All Speeds (Part 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz
and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
Trace Interface
TrcClk
n/a
n/a
10.3
10.3
10.3
10.3
7.1
7.1
7.1
7.1
TrcBS0:2
TrcES0:4
TrcTS0:6
Page 57 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—400, 466, and 500MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
External Slave Peripheral Interface
PerData00:31
PerAddr00:31
PerPar0:3
3
1
1
9
7.6
8.4
6.5
6
0
0
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
n/a
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
n/a
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
3
4
1
0
PerWBE0:3
PerCS0:7
2.5
n/a
n/a
n/a
2.5
5
1
0
n/a
n/a
n/a
1
0
PerOE
6
0
PerWE
7
0
PerBLast
5
n/a
n/a
n/a
n/a
0
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerReady[RcvrInh]
PerR/W
1
n/a
5.6
n/a
7
2.5
dc
n/a
dc
1
15.3
n/a
10.2
n/a
DMAReq0:3
DMAAck0:3
EOT0:3/TC0:3
dc
n/a
dc
15.3
15.3
10.2
10.2
6.8
0
External Master Peripheral Interface
PerClk
n/a
n/a
3.5
n/a
2.5
n/a
n/a
4.5
n/a
n/a
1
n/a
6.2
n/a
6.4
n/a
6.2
6.2
n/a
n/a
0
15.3
15.3
n/a
10.2
10.2
n/a
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
n/a
0
n/a
1
15.3
n/a
10.2
n/a
n/a
0
n/a
n/a
1
15.3
15.3
15.3
10.2
10.2
10.2
BusReq
PerErr
0
n/a
Page 58 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
DDR SDRAM
The DDR SDRAM controller times its operation with internal PLB and 2xPLB clock signals and generates
MemClkOut from the PLB clock. MemClkOut is the same frequency as the PLB clock signal. The alignment of
MemClkOut with the PLB clock signal is delayed a maximum of 3ns by driver circuits.
Note: MemClkOut may be advanced or delayed with respect to the PLB clock by means of the
SDRAM0_CFGn programming registers. Users might need to advance MemClkOut for their
applications. This depends on the specific application and requires a thorough understanding of the
memory system in general (refer to the DDR SDRAM controller chapter in the PowerPC 440GP User’s
Manual).
I/O Specifications—DDR SDRAM
Notes:
1. 3.225 + 1/4 TCYC where TCYC = 7.5ns for a 133.33MHz clock.
2. Worst case propagation delay of signal through logic block.
3. Byte lane skew from MemClkOut0. The first number is the earliest that any bit in the byte arrives at the package pin and
the second number is the latest that any bit in that byte arrives at the package pin.
4. Delay of MemClkOut0 in relation to PLB clock.
Input (ns)
Output (ns)
Valid Delay Hold Time
(maximum) (minimum)
Output Current (mA)
Signal Path
Clock
Notes
Setup Time Hold Time
(minimum) (minimum)
I/O H I/O L
(maximum) (minimum)
50pF load
50pF load
Read Data
Flip-Flops
0.2
0.2
0.2
0.2
Transparent Latch
RDSL Mux
ECC Logic
Write Data
MemData00:07
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
0.2
3.5
2
2
2.91:2.97
2.88:2.94
2.86:2.96
2.87:2.91
2.85:2.93
2.84:2.94
2.83:2.90
2.83:2.93
2.84:2.92
3
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
2xPLB3
3
3
3
3
3
3
3
2xPLB3
2xPLB
PLB4
DM0:8
MemClkOut0
MemAddr00:12
BA0:1
2.6
RAS
CAS
3.8
5.1
15.2
15.2
15.2
15.2
PLB
WE
BankSel0:3
ClkEn0:3
DQS0:8
2xPLB1
Page 59 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
DDR SDRAM Write Cycle Timing
MemClkOut
PLB clk
2xPLB clk
DQS
D2
D1
MemData
DDR SDRAM Read Cycle Timing
MemClkOut
PLB clk
2xPLB clk
DQS
D2
D1
MemData
For DDR SDRAM read operations, MemData must be valid by no later than 1/4 TCYC - 0.5ns (1.375 ns at
133.33MHz) from the rising edge of DQS, and must be held valid until 1/4TCYC + 0.4ns (2.275ns at
133.33 MHz) from the rising DQS at the chip pins. Data D2 must have the same relationship to falling DQS. In
addition, there is a setup time with respect to the PLB clock of 2.375ns, unless the read data clock has been
delayed by programming the SDRAM0_CFGn register. The latches found in the read data path stages have a
setup time of 200ps and a hold time of 100ps.
Page 60 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Initialization
The PPC440GP provides the option for setting initial parameters based on default values or by reading them
from a slave PROM attached to the IIC0 bus (see “EEPROM” below). Some of the default values can be
altered by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain
default initial conditions prior to PPC440GP start-up. The actual capture instant is the nearest reference clock
edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-
down (logical 0) resistors to select the desired default conditions. These pins are used for strap functions only
during reset. Following reset they are used for normal functions. The signal names assigned to the pins for
normal operation follow the pin number.
The following table lists the strapping pins along with their functions and strapping options:
Strapping Pin Assignments
Function
Option
Ball Strapping
V24
UART0_DCD
Bootstrap controller
Disabled
Enabled
0
1
V02
UART0_DSR
IIC0 slave address that will respond with boot data
0x54
0x50
0
1
EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM
device connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the
PPC440GP sequentially reads 16 bytes from the ROM device on the IIC0 port and uses the first 8 bytes to set
the SYS0 and SYS1 registers accordingly. Otherwise, the default values set in the STRP0 and STRP1
registers are used for initialization.
The initialization settings and their default values are covered in detail in the PowerPC 440GP User’s Manual.
Page 61 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Revision Log
Date
Contents of Modification
08/07/2002
08/30/2002
09/11/2002
10/22/2002
11/20/2002
01/07/2003
01/22/2003
03/25/2003
Add revision log.
Change EMC0:1TxD0:1 and EMC0:1TxEn T from 15 to 11 ns.
OV
Update for 466 and 500 MHz parts
Add heat sink mounting information and additional part numbers for E temperature range.
Update I/O timing data.
Update PCI-X I/O voltage specification.
Correct description of SysReset signal.
Update DDR SDRAM timing.
Page 62 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
Inside of back cover
Page 63 of 64
4/1/03
PowerPC 440GP Embedded Processor Data Sheet
(c) Copyright International Business Machines Corporation 1999, 2003
All Rights Reserved
Printed in the United States of America, April 1, 2003
The following are trademarks of International Business Machines Corporation in the
United States, or other countries, or both:
Blue Logic
IBM
PowerPC
CoreConnect
IBM Logo
Other company, product, and service names may be trademarks or service marks of
others.
All information contained in this document is subject to change without notice. The
products described in this document are NOT intended for use in implantation, life
support, or other hazardous uses where malfunction could result in death, bodily
injury, or catastrophic property damage. The information contained in this document
does not affect or change IBM product specifications or warranties. Nothing in this
document shall operate as an express or implied license or indemnity under the
intellectual property rights of IBM or third parties. All information contained in this
document was obtained in specific environments, and is presented as an illustration.
The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS
IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly
from any use of the information contained in this document.
IBM Microelectronics Division
1580 Route 52
Hopewell Junction, NY 12533-6351
The IBM home page is www. ibm.com.
The IBM Microelectronics Division home page is www.chips.ibm.com.
SA14-2561-15
64
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