IC-OC [ICHAUS]
INTEGRATING LIGHT-VOLTAGE CONVERTER; 集成的光 - 电压转换器
| 型号： | IC-OC |
| 厂家： | 
IC-HAUS GMBH |
| 描述： | INTEGRATING LIGHT-VOLTAGE CONVERTER |
| 文件： | 总9页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 1/9
FEATURES
APPLICATIONS
♦ Two photosensors with integrating amplifiers
♦ Integration time can be set externally
♦ Internal shift register for chain connection
♦ Detection of low supply voltage
♦ Optical line sensors
♦ CCD substitute
♦ TTL/CMOS-compatible logic inputs and outputs
♦ 5 V supply voltage
♦ Low power consumption
♦ Photosensors with 1 mm pitch;
active area ca. 0.97 mm x 0.47 mm (0.44 mm²)
CHIP
D1
D2
1.7 mm x 1.2 mm
BLOCK DIAGRAM
VDD − 1.2V
VDD
SC1
+5V
iC−OC
D1
R1
1kΩ
SOUT1
INTEGRATOR 1
AOUT
VOUT
SOUT2
VDD − 1.2V
SC2
D2
ANALOGUE OUTPUT
INTEGRATOR 2
DOUT
GND
D
Q4
C
DIN
D
Q1
D
Q2
D
Q3
BUFFER
R
C
C
C
CLK
R
R
R
LOW VOLTAGE
INPUT
SHIFT REGISTER
Copyright © 2010 iC-Haus
http://www.ichaus.com
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 2/9
DESCRIPTION
iC-OC is an optical sensor with two photodiodes, two The control logic output supplies a CMOS compatible
integrating amplifiers and a control logic which en- signal and in chain connection it can be directly linked
ables several iC-OCs to be connected in a chain.
to the digital input of the next device. Logic inputs are
configured as Schmitt triggers and are TTL/CMOS-
Furthermore, the control logic, consisting of a two- compatible.
stage shift register, determines when the integration
time starts and ends and switches the integrators All the registers in the device are reset with low
in sequence to the analogue output. The analogue voltage (power-down reset). All pins are protected
output is a source follower and in its deactivated against ESD.
state has a high impedance and can thus be used
in buses.
CHIP LAYOUT
PIN CONFIGURATION Chip
PIN FUNCTIONS
No. Name Function
DIN
Input
GND AOUT VDD
CLK Clock Input
DOUT Data Output
VDD +5 V Supply Voltage
AOUT Analogue Output
GND Ground
D1
D2
DIN CLK DOUT
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 3/9
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
-0.3
-20
Max.
G001 VDD
G002 Ic()
Supply Voltage
6.5
20
V
Clamping Current in DIN, CLK, DOUT,
AOUT
mA
G003 I()
Current in DOUT
-10
10
mA
mA
G004 Ilu()
Pulse Current in all Pins (Latch-up
strength)
Pulse width ≤ 10 µs
-100
100
G005 Vd()
G006 Tj
ESD Susceptibility, at all Pins
Junction Temperature
HBM, 100 pF discharged through 1.5 kΩ
2
kV
°C
-40
150
G007 Ts
Storage Temperature
See package specification
THERMAL DATA
Operating Conditions: VDD = 5 V ±10 %
Item Symbol
No.
Parameter
Conditions
Unit
Min. Typ. Max.
T01 Ta
Operating Ambient Temperature Range See package specification
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 4/9
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5 V ±10 %, RL(VDD/AOUT) = 1 kΩ, Tj = 0...85 °C unless otherwise noted
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
001 VDD
Permissible Supply Voltage
Range
4.5
5.5
V
002 I(VDD)
003 Vc()hi
Supply Current in VDD
100
0.3
700
1.5
µA
V
Clamp Voltage hi at DIN, CLK,
DOUT, AOUT
Vc()hi = V() − VDD, I() = 10 mA,
other pins open
004 Vc()lo
Clamp Voltage lo at DIN, CLK,
DOUT, AOUT
I() = -10 mA, other pins open
-1.5
-0.3
950
V
005 Aph()
Radiant Sensitive Area
ca. 0.97 x 0.47
mm²
nm
006 λar
Spectral Application Range
S(λar) = 0.25 x S(λ)max
300
Analogue Output AOUT
201 V0()
Output Voltage at no illuminance V0() = VDD − V(AOUT)max,
0.7
-10
1.4
10
V
AOUT active (* see below)
202 ∆Vd()
Variation of Output Voltage at no ∆Vd() = V(AOUT)t1 − V(AOUT)t2,
mV
illuminance
∆t = t2 − t1 = 1 ms
Tenfold illuminance
VDD = 4.5 V
VDD = 5 V
203
Vs()
Saturation Voltage
1.4
1.45
1.5
V
V
V
VDD = 5.5 V
204 ∆V()
Repeatability (standard deviation 20 measurements at constant LED illuminance,
at repeated measurement)
Vav(AOUT) ≈ 2.91 V, ∆t = 25 µs
15
mV
205 Vlin()
Output Voltage Linearity Range Vlin() = VDD − V0() − V(AOUT)
1.7
V
206
K
Transfer Factor
BMST assembly incl. sealing;
λLED = 628 nm, ∆λ = ±23 nm
λLED = 880 nm, ∆λ = ±40 nm
output voltage vs. light power
0.22
0.13
0.27
0.16
0.32 V/pWS
0.19 V/pWS
207 ∆klin
Transfer Factor Deviation within
linearity range
-5
5
%
208 I()
Leakage Current
V(AOUT) = 0...VDD,
-2
2
µA
AOUT high impedance (* see below)
Shift-Register DIN, CLK, DOUT
301 Vt()hi
302 Vt()lo
303 Vt()hys
304 Ii()
Threshold Voltage hi at DIN, CLK
2.2
V
V
Threshold Voltage lo at DIN, CLK
Hysteresis at DIN, CLK
0.8
250
-1
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDD
1300
1
mV
µA
MHz
ns
Input Current in DIN, CLK
305 f()
Permissible Frequency at CLK
Permis. Pulse Width hi at CLK
Permis. Pulse Width lo at CLK
10
306 tw()hi
307 tw()lo
308 tplh
20
20
ns
Propagation Delay: CLK hi → lo CL(DOUT) = 50 pF (see Fig. 2)
40
40
ns
until DOUT lo → hi
309 tphl
310 tpon
311 tpoff
Propagation Delay: CLK hi → lo CL(DOUT) = 50 pF (see Fig. 2)
until DOUT hi → lo
ns
ns
ns
Propagation Delay: CLK lo → hi CL(VDD/AOUT) = 1 nF (see Fig. 2)
800
100
until AOUT active
Propagation Delay: CLK lo → hi CL(VDD/AOUT) = 1 nF (see Fig. 2)
until AOUT high impedance
312 Vs()hi
313 Vs()lo
Saturation Voltage hi at DOUT
Saturation Voltage lo at DOUT
Vs()hi = VDD − V(), I() = -1 mA
I() = 1 mA
0.4
0.4
V
V
Low Voltage Detection
401 VDDon
402 VDDoff
403 VDDhys
Turn-on Threshold VDD
Increasing voltage at VDD
Decreasing voltage at VDD
VDDhys = VDDon − VDDoff
2.1
1.0
0.5
3.8
2.1
2
V
V
V
Undervoltage Threshold VDD
Hysteresis
(*)
AOUT active: SOUT1 or SOUT2 closed; AOUT high impedance: SOUT1 and SOUT2 open.
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 5/9
ELECTRICAL CHARACTERISTICS: Diagrams
100
100
%
%
90
90
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
Figure 2: Relative Spectral Sensitivity with BMST as-
sembly
Figure 1: Relative Spectral Sensitivity
OPERATING REQUIREMENTS: Logic
Operating Conditions: VDD = 5 V ±10 %, Ta = 0...85 °C,
input levels lo = 0...0.45 V, hi = 2.4 V...VDD, see Fig. 3 for reference levels
Item Symbol
No.
Parameter
Conditions
Fig.
3
Unit
ns
Min.
Max.
I001 tset
Setup time:
10
DIN stable before CLK lo → hi
Hold time:
I002 thold
3
5
ns
DIN stable after CLK lo → hi
V
Input/Output
2.4V
2.0V
0.8V
0.45V
t
1
0
Figure 3: Reference levels
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 6/9
clock cycle 1
1
clock cycle 4
4
CLK
2
3
5
6
7
8
9
10
DIN1
DOUT1= DIN2
DOUT2
Reset
Reset
Reset
Integrator1
Integrator2
Reset
Reset
Reset
Reset
Integrator3
Reset
V0()1
Reset
Integrator4
5V
V0()2
Int2
V0()3
Int3
V0()4
Int4
integration time not determined
V(AOUT)
Int1
Int2
Int3
Int4
Int1
Int1
Int2
Figure 4: Timing characteristics after power on (assumption: V0()1 = V0()2 = V0(), VDD = 5 V)
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 7/9
DESCRIPTION OF FUNCTIONS
iC-OC is an integrating light-voltage converter with two second clock cycle switches the analogue output from
separate photodiodes and two integrators. The inte- integrator 1 to integrator 2 (SOUT1 opens, SOUT2
gration time starts when the supply voltage is applied. closes). A non-reproducible voltage value is again
To obtain a specified integration time a hi pulse must present at AOUT (see above). At the same time the
first be available at the digital input DIN and clocked by integration capacity of integrator 1 is short-circuited by
the device. This process sequentially resets the inte- switch SC1 (reset).
grators to their initial value and restarts the integration
time with the next clock pulse.
Flip-flop Q4 is set in the second clock cycle with the
negative clock edge (DOUT1) and thus the DIN signal
for the next device in the chain is produced.
Flip-flops Q1 to Q3 sequentially accept the signal at
DIN with the positive CLK edge. Flip-flop Q4, which
controls the DOUT output signal, reacts to the nega-
tive CLK edge. The switching states in the IC always During the third clock cycle integrator 2 is discon-
remain for the duration of a clock cycle. The process nected from AOUT (SOUT2 opens) and reset (SC2
depicted in Fig. 2 is initiated when a hi pulse is applied closes). Simultaneously, the integration time for inte-
to DIN.
grator 1 starts anew (SC1 opens). If several iC-OCs
are connected in a chain, then the hi signal from DOUT
During the first clock cycle integrator 1 is switched to is shifted into the first flip-flop of the next device with
the analogue output AOUT (switch SOUT1 closes). the third clock cycle. During the fourth clock cycle
AOUT initially supplies a voltage value which cannot switch SC2 opens and starts the integration time for
be reproduced as the integration time is unknown. The integrator 2.
APPLICATIONS INFORMATION
VDD
Only when the DOUT2 output has a hi level can the
next hi signal be applied to DIN1. The first hi signal
AOUT
clocked by the device implements a sequential reset of
GND
AOUT
VDD
GND
AOUT
VDD
the integrators, followed by the integration time starting
in sequence. The second hi signal shifted through the
register determines the end of the integration time and
restarts the integration time after a reset. The integra-
tors can be read out with the aid of a sample and hold
circuit, as the device itself has no hold mode. Besides
the clock a periodic signal at DIN is also necessary for
the continuous operation of the device.
iC−OC
iC−OC
DOUT
DIN
CLK
DIN
CLK
DOUT
DIN1
CLK
DOUT1= DIN2
DOUT2
Figure 5: Example of a chain connection for two de-
vices
With operation of the device at low level illumination
the output voltage V(AOUT) decreases by V0(AOUT).
When calibrating, this drop in voltage must be deter-
mined for each of the photosensors.
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 8/9
Taktzyklus 1
1
Taktzyklus 4
4
CLK
2
3
5
6
7
8
9
10
DIN1
DOUT1= DIN2
DOUT2
Reset
Reset
Reset
Integrator1
Integrator2
Reset
Reset
Reset
Reset
Integrator3
Integrator4
Reset
V0()1
Reset
V0()2
Int2
V0()3
Int3
V0()4
Int4
5V
Bereich unbestimmter Integrationszeit
V(AOUT)
Int1
Int2
Int3
Int4
Int1
Int1
Int2
Figure 6: Time sequence for the chain connection in Fig. 5 after the device has been switched on
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in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of
merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which
information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or
areas of applications of the product.
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mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
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We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 9/9
ORDERING INFORMATION
Type
Package
Order Designation
iC-OC samples
iC-OC
CDIP16
-
iC-OC CDIP16
iC-OC chip
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Tel.: +49 (61 35) 92 92-0
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners
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