X25020 [ICMIC]
SPI Serial E2PROM with Block LockTM Protection; SPI串行E2PROM带座LockTM保护
| 型号： | X25020 |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | SPI Serial E2PROM with Block LockTM Protection |
| 文件： | 总14页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
ICmic
256 x 8 Bit
This X25020 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
2K
X25020
SPI Serial E2PROM with Block LockTM Protection
FEATURES
DESCRIPTION
The X25020 is a CMOS 2048-bit serial E2PROM, internally
organized as 256 x 8. The X25020 features a serial
•1MHz Clock Rate
•SPI Modes (0,0 & 1,1)
•256 X 8 Bits
—4 Byte Page Mode
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
•Low Power CMOS
—10µA Standby Current
—3mA Active Write Current
•2.7V To 5.5V Power Supply
(CS) input, allowing any number of devices to share the
same bus.
•Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
•Built-in Inadvertent Write Protection
The X25020 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25020 will ignore transitions on its
inputs, thus allowing the host to service higher priority
—Power-Up/Power-Down protection circuitry
—Write Latch
interrupts. The WP input can be used as a hardwire input to
the X25020 disabling all write attempts, thus providing a
mechanism for limiting end user capability of altering the
memory.
—Write Protect Pin
•Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
•High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
The X25020 utilizes Xicor’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
—ESD protection: 2000V on all pins
•8-Lead PDlP Package
•8-Lead SOIC Package
FUNCTIONAL DIAGRAM
WRITE
PROTECT
LOGIC
STATUS
REGISTER
X DECODE
LOGIC
256 BYTE
ARRAY
16
16
32
16 X 32
16 X 32
32 X 32
SO
SI
SCK
COMMAND
DECODE
AND
CONTROL
LOGIC
CS
HOLD
WRITE
CONTROL
AND
TIMING
LOGIC
WP
4
8
Y DECODE
DATA REGISTER
3834 FHD F01
™ ™
Direct Write and Block Lock Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3834-1.8 6/10/96 T3/C1/D0 NS
Characteristics subject to change without notice
1
X25020
PIN DESCRIPTIONS
Serial Output (SO)
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device.Oncethepartisselectedandaserialsequenceis
underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serialsequence. Topause, HOLD mustbebroughtLOW
while SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause
feature is not used, HOLD should be held HIGH at all
times.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte ad-
dresses, and data to be written to the memory are input
onthispin. Dataislatchedbytherisingedgeoftheserial
clock.
PIN CONFIGURATION
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
DIP/SOIC
CS
SO
WP
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
X25020
V
Chip Select (CS)
SS
WhenCS isHIGH, theX25020isdeselectedandtheSO
output pin is at high impedance and unless an internal
write operation is underway, the X25020 will be in the
standby power mode. CS LOW enables the X25020,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
3834 FHD F02.1
PIN NAMES
Symbol
CS
SO
Description
Chip Select Input
Serial Output
Serial Input
Write Protect (WP)
SI
When WP is LOW, nonvolatile writes to the X25020 are
disabled, but the part otherwise functions normally.
WhenWP isheldHIGH, allfunctions, includingnonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25020. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
SCK
WP
VSS
Serial Clock Input
Write Protect Input
Ground
VCC
HOLD
Supply Voltage
Hold Input
3834 PGM T01.1
2
X25020
PRINCIPLES OF OPERATION
Status Register
The X25020 is a 256 x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The X25020 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
therisingSCK. CS mustbeLOWandtheHOLD andWP
inputs must be HIGH during the entire operation.
7
6
5
4
3
2
1
0
X
X
X
X
BP1 BP0
WEL
WIP
3834 PGM T02
BP0 and BP1 are set by the WRSR instruction. WEL
and WIP are read-only and automatically set by other
operations.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25020 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.
DatainputissampledonthefirstrisingedgeofSCKafter
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
usercanasserttheHOLD inputtoplacetheX25020into
a“PAUSE”condition.AfterreleasingHOLD,theX25020
will resume operation from the point when HOLD was
first asserted.
The Write Enable Latch (WEL) bit indicates the status of
the“writeenable”latch.Whensettoa“1”,thelatchisset,
when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25020 is divided into four 512-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unabletoalter(write)datawithintheselectedsegments.
The partitioning is controlled as illustrated below.
Write Enable Latch
The X25020 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.
Status Register Bits
Array Addresses
Protected
BP1
BP0
0
0
1
1
0
1
0
1
None
$C0–$FF
$80–$FF
$00–$FF
3834 PGM T03
Table 1. Instruction Set
Instruction Name
WREN
Instruction Format*
0000 0110
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
WRDI
0000 0100
RDSR
0000 0101
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected address
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
WRITE
0000 0010
3834 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25020
Clock and Data Timing
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a thirty-
two clock operation. CS must go LOW and remain LOW
for the duration of the operation. The host may continue
to write up to 4 bytes of data to the X25020. The only
restriction is that the 4 bytes must reside on the same
page. Iftheaddresscounterreachestheendofthepage
and the clock continues, the counter will “roll over” to the
firstaddressofthepageandoverwriteanydatathatmay
have been written.
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instructionistransmittedtotheX25020, followedbythe
8-bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequentially
by continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached ($FF) the address counter rolls
over to address $00 allowing the read cycle to be
continued indefinitely. The read operation is termi-
nated by taking CS HIGH. Refer to the read E2PROM
array operation sequence illustrated in Figure 1.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
databyteNisclockedin.IfitisbroughtHIGHatanyother
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5, 6
and 7 must be “0”. Figure 6 illustrates this sequence.
To read the status register CS line is first pulled LOW
to select the device followed by the 8-bit RDSR instruc-
tion. After the read status register opcode is sent, the
contents of the status register are shifted out on the SO
line. Figure 2 illustrates the read status register se-
quence.
While the write is in progress following a status register
or E2PROM write sequence, the status register may be
readtochecktheWIPbit.DuringthistimetheWIPbitwill
be HIGH.
Hold Operation
Write Sequence
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
canbepulledLOWtosuspendthetransferuntilitcanbe
resumed. The only restriction is the SCK input must be
LOWwhenHOLDisfirstpulledLOWandSCKmustalso
be LOW when HOLD is released.
Prior to any attempt to write data into the X25020 the
“write enable” latch must first be set by issuing the
WRENinstruction(SeeFigure3). CS isfirsttakenLOW,
then the WREN instruction is clocked into the X25020.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
4
X25020
Operational Notes
Data Protection
The X25020 powers-up in the following state:
• The device is in the low power standby state.
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• A WREN instruction must be issued to set the “write
enable” latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
• The “write enable” latch is reset.
Figure 1. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15 16 17 18 19 20 21 22
SCK
SI
INSTRUCTION
BYTE ADDRESS
5
4
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3834 FHD F04.1
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3834 ILL F13
5
X25020
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
3834 ILL F05
Figure 4. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
BYTE ADDRESS
DATA BYTE
5
4
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3834 FHD F14.1
6
X25020
Figure 5. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
BYTE ADDRESS
DATA BYTE 1
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CS
SCK
SI
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE 4
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
3834 FHD F07.1
Figure 6. Write Status Register Operation Sequence
CS
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
7
9
6
SCK
SI
INSTRUCTION
DATA BYTE
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3834 ILL F15.1
7
X25020
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
Voltage on any Pin with Respect to V ......... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
X25020
Limits
5V ±10%
Temp
Min.
0°C
Max.
Commercial
Industrial
+70°C
X25020–3
3V to 5.5V
2.7V to 5.5V
–40°C
+85°C
3834 PGM T05.2
X25020–2.7
3834 PGM T06.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCK = V x 0.1/V x 0.9 @ 1MHz,
SO = Open
I
V
V
Supply Current (Active)
3
mA
CC
CC
CC
CC
CC
I
Supply Current
10
µA
CS = V , V = V or V
– 0.3V
CC
SB
CC
IN
SS
(Standby)
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
(1)
V
V
V
V
–0.5
V
x 0.3
IL
CC
(1)
V
x 0.7 V
+ 0.5
V
IH
CC
CC
0.4
V
I
I
= 2mA
OL
OL
OH
V
– 0.8
V
= –1mA
OH
CC
3834 PGM T07.5
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Units
(2)
t
Power-up to Read Operation
Power-up to Write Operation
1
5
ms
PUR
(2)
t
ms
PUW
3834 PGM T08
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V.
A
CC
Symbol
Test
Max.
Units
Conditions
= 0V
(2)
C
C
Output Capacitance (SO)
8
6
pF
pF
V
OUT
OUT
(2)
Input Capacitance (SCK, SI, CS, WP, HOLD)
V
IN
= 0V
3834 PGM T09.1
IN
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
8
X25020
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
InputPulseLevels
V
CC
x0.1toV x0.9
CC
5V
InputRiseandFallTimes
InputandOutputTimingLevel
10ns
V
CC
x0.5
2.16KΩ
3834 PGM T10
OUTPUT
3.07KΩ
100pF
3834 FHD F12.1
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
Parameter
Clock Frequency
Cycle Time
Min.
0
Max.
Units
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
SCK
CYC
LEAD
LAG
WH
WL
SU
1000
500
500
400
400
100
100
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Write Cycle Time
ns
ns
ns
ns
H
2
2
µs
RI
µs
FI
200
200
500
ns
HD
CD
CS
ns
ns
(3)
10
ms
3834 PGM T11.2
WC
Data Output Timing
Symbol
Parameter
Min.
Max.
Units
f
t
t
t
t
t
t
t
Clock Frequency
0
1
MHz
ns
SCK
DIS
V
Output Disable Time
500
360
Output Valid from Clock LOW
Output Hold Time
ns
0
ns
HO
RO
FO
LZ
Output Rise Time
300
300
ns
Output Fall Time
ns
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
100
100
ns
ns
HZ
3834 PGM T12.1
Notes: (3) t
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
WC
9
X25020
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
tHO
tWL
tDIS
SO
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
SI
3834 FHD F09.1
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
3834 FHD F10
10
X25020
Hold Timing
CS
SCK
SO
tHD
tCD
tCD
tHD
tHZ
tLZ
SI
HOLD
3834 FHD F11
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
11
X25020
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
12
X25020
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X25020
ORDERING INFORMATION
X25020
P
T
G
-V
VCC Limits
Blank = 5V 10%
3 = 3V to 5.5V
2.7 = 2.7V to 5.5V
Device
RoHS Compliant Lead Free package
Blank – Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
Part Mark Convention
G = RoHS compliant lead free
X25020
X G
X
Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
Blank = 5V 10%, 0°C to +70°C
I = 5V 10%, -40°C to +85°C
D = 3V to 5.5V, 0°C to +70°C
E = 3V to 5.5V, -40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, -40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no
warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without
notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402;
4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
14
相关型号：
©2020 ICPDF网 联系我们和版权申明