X25057S-2.7
更新时间：2024-09-18 05:32:29
品牌：ICMIC
描述：5MHz Low Power SPI Serial E2PROM with IDLock⑩ Memory
概述
规格参数
数据手册X25057S-2.7 概述
5MHz Low Power SPI Serial E2PROM with IDLock⑩ Memory 5MHz的低功耗SPI串行E2PROM与IDLock⑩记忆 EEPROM
X25057S-2.7 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | SOP, SOP8,.25 |
| 针数： | 8 | Reach Compliance Code： | unknown |
| ECCN代码： | EAR99 | HTS代码： | 8542.32.00.51 |
| 风险等级： | 5.91 | 最大时钟频率 (fCLK)： | 5 MHz |
| 数据保留时间-最小值： | 100 | 耐久性： | 100000 Write/Erase Cycles |
| JESD-30 代码： | R-PDSO-G8 | JESD-609代码： | e0 |
| 长度： | 4.9 mm | 内存密度： | 4096 bit |
| 内存集成电路类型： | EEPROM | 内存宽度： | 8 |
| 湿度敏感等级： | 3 | 功能数量： | 1 |
| 端子数量： | 8 | 字数： | 512 words |
| 字数代码： | 512 | 工作模式： | SYNCHRONOUS |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 组织： | 512X8 | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP8,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 并行/串行： | SERIAL | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 3/5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.75 mm | 串行总线类型： | SPI |
| 最大待机电流： | 0.000001 A | 子类别： | EEPROMs |
| 最大压摆率： | 0.003 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 2.7 V | 标称供电电压 (Vsup)： | 3.3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 3.9 mm | 最长写入周期时间 (tWC)： | 10 ms |
| 写保护： | HARDWARE/SOFTWARE | Base Number Matches： | 1 |
X25057S-2.7 数据手册
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This X25057 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
512 x 8 Bit
IC MICROSYSTEMS
4K
X25057
5MHz Low Power SPI Serial E2PROM with IDLock™ Memory
DESCRIPTION
FEATURES
The X25057 is a CMOS 4K-bit serial E2PROM, internally
organized as 512 x 8. The X25057 features a Serial
•5MHz Clock Rate
•IDLock™ Memory
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus. The bus
—IDLock First or Last Page, Any 1/4 or Lower 1/2 of
E2PROM Array
•Low Power CMOS
—<1∝A Standby Current
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
—<3mA Active Current during Write —
<400∝A Active Current during Read
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
•1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
•Built-in Inadvertent Write Protection
IDLock is a programmable locking mechanism which
allows the user to lock system ID and parametric data in
different portions of the E2PROM memory space, ranging
from as little as one page to as much as 1/2 of
—Power-Up/Power-Down Protection Circuitry —
Write Enable Latch
—Write Protect Pin
•SPI Modes (0,0 & 1,1)
•512 x 8 Bits
the total array. The X25057 also features a WP pin that can
be used for hardwire protection of the part, disabling
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
—16 Byte Page Mode
•Self-Timed Write Cycle
The X25057 utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles
—5ms Write Cycle Time (Typical)
•High Reliability
per byte and a minimum data retention of 100 years.
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
•8-Lead MSOP Package •8-
Lead TSSOP Package
•8-Lead SOIC Package
•8-Lead PDIP Package
FUNCTIONAL DIAGRAM
DATA REGISTER
Y DECODE LOGIC
SI
SO
16
8
COMMAND
DECODE
X
32
SCK
DECODE
LOGIC
AND
CONTROL
LOGIC
4K E2PROM
ARRAY
(512 x 8)
CS
HIGH VOLTAGE
CONTROL
WP
WRITE CONTROL LOGIC
7033 FRM F01
©Xicor, Inc. 1994 – 1997 Patents
Characteristics subject to change without notice
1
Pending 7033-1.1 5/8/97 T1/C0/D0 SH
X25057
PIN DESCRIPTIONS
PIN CONFIGURATION
Not to scale
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
8 Lead SOIC/PDIP
1
2
3
4
8
7
6
5
V
CS
SO
CC
NC
Serial Input (SI)
*0.197"
X25057
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this
pin. Data is latched by the rising edge of the serial clock.
SCK
WP
V
SI
SS
7033 FRM F02
*0.244"
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input
and output. Opcodes, addresses, or data present
8 Lead MSOP
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
V
1
2
8
7
6
5
SO
CS
CC
NC
0.120"
X25057
SI
V
3
SS
SCK
4
WP
Chip Select (CS)
When CS is HIGH, the X25057 is deselected and the SO
output pin is at high impedance and unless an internal
7033 FRM F02.1
0.193"
write operation is underway, the X25057 will be in the
standby power mode. CS LOW enables the X25057,
8 Lead TSSOP
placing it in the active power mode. It should be noted that
after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
NC
1
2
3
4
8
SCK
SI
7
6
5
V
CC
CS
0.122"
X25057
V
SS
WP
SO
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25057 are
disabled, but the part otherwise functions normally. When
7033 FRM F02.2
0.252"
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is still
*SOIC Measurement
LOW will interrupt a write to the X25057. If the internal
write cycle has already been initiated, WP going low will
have no affect on this write.
PRINCIPLES OF OPERATION
PIN NAMES
The X25057 is a 512 x 8 E2PROM designed to interface
directly with the synchronous Serial Peripheral Interface
(SPI) of many popular microcontroller families.
Symbol
Description
Chip Select Input
CS
SO
SI
Serial Output
Serial Input
The X25057 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW and the WP
input must be HIGH during the entire operation. Table 1
SCK
WP
Serial Clock Input
Write Protect Input
Ground
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB first.
V
SS
V
Supply Voltage
No Connect
CC
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then start it again to resume opera- tions
where left off.
NC
7033 FRM T01
2
X25057
Read Status Operation
If there is not a nonvolatile write in progress, the Read
Status instruction returns the ID Lock byte from the Sta-
Write Enable Latch
The X25057 contains a “Write Enable” latch. This latch
must be SET before a write operation is initiated.
tus Register which contains the ID Lock bits IDL2-IDL0
(Figure 1). The ID Lock bits define the ID Lock condition
The WREN instruction will set the latch and the WRDI
instruc- tion will reset the latch (Figure 4). This latch is
Automatically reset upon a power-up condition
(Figure 1/Table1). The other bits are reserved and will
return ’0’ when read. See Figure 3.
and after the completion of a byte or page write cycle.
If a nonvolatile write is in progress, the Read Status
Instruction returns a HIGH on SO. When the nonvolatile
IDLock Memory
Xicor’s IDLock Memory provides a flexible mechanism to
store and lock system ID and parametric information.
write cycle is completed, the status register data is read
out.
There are seven distinct IDLock Memory areas within the
array which vary in size from one page to as much as half
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is clocked,
of the entire array. These areas and associated address
ranges are IDLocked by writing the appropriate two byte
the pointer to the status register is also clocked, even
though the SO pin shows the status of the nonvolatile
write operation (See Figure 3).
IDLock instruction to the device as described in Table 1 and
Figure 7. Once an IDLock instruction has been com-
pleted, that IDLock setup is held in a nonvolatile Status
Register (Figure 1) until the next IDLock instruction
Write Sequence
Prior to any attempt to write data into the X25057, the
“Write Enable” latch must first be set by issuing the
is
issued. The sections of the memory array that are
IDLocked can be read but not written until IDLock is
removed or changed.
WREN instruction (See Table 1 and Figure 4). CS is first
taken LOW. Then the WREN instruction is clocked into
Figure 1. Status Register/IDLock Protection Byte
the X25057. After all eight bits of the instruction are
transmitted, CS must then be taken HIGH. If the user
7
0
6
0
5
0
4
0
3
0
2
1
0
continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation
will be ignored.
IDL2 IDL1 IDL0
Note: Bits [7:3] specified to be “0’s”
7038 FRM T02.1
To write data to the E2PROM memory array, the user then
issues the WRITE instruction, followed by the 16 bit
Clock and Data Timing
address and the data to be written. Only the last 9 bits of the
address are used and bits [15:9] are specified to be
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
zeroes. This is minimally a thirty-two clock operation. CS
must go LOW and remain LOW for the duration of
the operation. The host may continue to wrote up to 16
bytes of data to the X25057. The only restriction is the 16
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
bytes
must reside on the same page. If the address counter
reaches the end of the page and the clock continues, the
counter will “roll over” to the first address of the page
and overwrite any data that may have been previously
written.
instruction is transmitted to the X25057, followed by the
16-bit address, of which the last 9 bits are used
(bits
[15:9] specified to be zeroes). After the READ opcode
and address are sent, the data stored in the memory at
For a byte or page write operation to be completed, CS can
only be brought HIGH after bit 0 of the last data byte
the selected address is shifted out on the SO line. The
data stored in memory at the next address can be read
to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed.
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
Refer to Figures 5 and 6 for detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
address after each byte of data is shifted out. When the
highest address is reached (01FFh), the address counter
rolls over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is
terminated
by taking CS HIGH. Refer to the Read Operation
Sequence illustrated in Figure 2.
3
X25057
Operational Notes
The X25057 powers up in the following state:
IDLock Operation
Prior to any attempt to perform an IDLock Operation, the
WREN instruction must first be issued. This
instruction
•The device is in the low power, standby state.
•A HIGH to LOW transition on CS is required to enter
sets the “Write Enable” latch and allows the part to
respond to an IDLock sequence (Figure 7). The IDLock
an active state and receive an instruction.
•SO pin is at high impedance.
•The “Write Enable” latch is reset.
instruction follows and consists of one command byte fol-
lowed by one IDLock byte (See Figure 1). This byte con-
tains the IDLock bits IDL2-IDL0. The rest of the bits [7:3] are
unused and must be written as zeroes. Bringing CS
Data Protection
The following circuitry has been included to prevent inad-
vertant writes:
HIGH after the two byte IDLock instruction initiates a
nonvolatile write to the Status Register. Writing more
than one byte to the Status Register will overwrite the
previously written IDLock byte. See Table 1.
•The “Write Enable” latch is reset upon power-up. •A
WREN instruction must be issued to set the “Write
Enable” latch.
•CS must come HIGH at the proper clock count in order
to start a write cycle.
Table 1. Instruction Set and Block Lock Protection Byte Definition
Instruction Format*
0000 0110
Instruction Name and Operation
WREN: Set the Write Enable Latch (Write Enable Operation)
WRDI: Reset the Write Enable Latch (Write Disable Operation)
0000 0100
0000 0001
IDLock Instruction—followed by:
IDLock Byte: (See Figure 1)
0000 0000 --->NO IDLock: 00h-00h ---------->None of the Array
0000 0001 --->IDLock Q1: 00h-7Fh ---------->Lower Quadrant (Q1)
0000 0010 --->IDLock Q2: 80h-FFh----------->Q2
0000 0011 --->IDLock Q3: 100h-17Fh-------->Q3
0000 0100 --->IDLock Q4: 180h-1FFh-------->Upper Quadrant (Q4)
0000 0101 --->IDLock H1: 00h-FFh----------->Lower Half of the Array (H1)
0000 0110 --->IDLock P0: 0h-Fh-------------->Lower Page (P0)
0000 0111 --->IDLock Pn: 1F0h-1FFh-------->Upper Page (Pn)
0000 0101
0000 0010
0000 0011
READ STATUS: Reads IDLock & write in progress status on SO Pin
WRITE: Write operation followed by address and data
READ: Read operation followed by address
7033 FRM T03
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
4
X25057
Figure 2. Read Operation Sequence
CS
20 21 22 23 24 25 26 27 28 29 30
0
1
2
3
4
5
6
7
8
9
SCK
SI
BYTE ADDRESS (2 BYTE)
DATA OUT
READ INSTRUCTION
(1 BYTE)
3
2
1
0
15 14
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
7033 FRM F03.1
Figure 3. Read Status Operation Sequence
CS
0
1
2
3
4
5
6
7
...
SCK
SI
READ STATUS
INSTRUCTION
...
NONVOLATILE WRITE IN PROGRESS
I
I
I
D
L
1
D
L
0
D
L
...
SO
2
SO = STATUS REG BIT
WHEN NO NONVOLATILE
WRITE CYCLE
SO HIGH DURING
NONVOLATILE
WRITE CYCLE
7033 FRM F04.2
5
X25057
Figure 4. WREN/WRDI Sequence
CS
0
1
2
3
4
5
6
7
SCK
INSTRUCTION
(1 BYTE)
SI
HIGH IMPEDANCE
SO
7033 FRM F05.1
Figure 5. Byte Write Operation Sequence
CS
20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
SCK
SI
BYTE ADDRESS (2 BYTE)
15 14
DATA BYTE
WRITE INSTRUCTION
(1 BYTE)
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
7033 FRM F06
6
X25057
Figure 6. Page Write Operation Sequence
CS
20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
BYTEADDRESS
(2 BYTE)
PROGRAM
INSTRUCTION
DATA BYTE 1
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
CS
SCK
SI
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE 16
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7033 FRM F07.3
Figure 7. IDLock Operation Sequence
CS
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
SCK
IDLock
INSTRUCTION
IDLock
BYTE
I
I
I
D
L
D
L
D
L
0
0
0
0
0
SI
2
1
0
HIGH IMPEDANCE
SO
7033 FRM F08.2
7
X25057
ABSOLUTE MAXIMUM RATINGS*
–65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
*COMMENT
Temperature under Bias ...................
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
Voltage on any Pin with
Respect to V
................................... –1V to +7V
D.C. Output Current..............................................5mA
SS
the device at these or any other conditions above those
indicated in the operational sections of this specification
Lead Temperature
(Soldering, 10 seconds) ..............................
is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
X25057
Limits
Temperature
Commercial
Industrial
Min.
0°C
Max.
4.5V to 5.5V
2.7V to 5.5V
1.8V to 3.6V
+70°C
+85°C
X25057-2.7
X25057-1.8
–40°C
7033 FRM T04
7033 FRM T05
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCK = V
x 0.1/V
x 0.9 @ 5MHz, SO =
I
V
V
Supply Current (Write)
CC
CC
3
mA
CC1
CC
CC
Open, CS = V
SS
∝A
∝A
SCK = V
x 0.1/V
x 0.9 @ 5MHz, SO =
I
I
Supply Current (Read )
CC
CC
400
1
CC2
SB
Open, CS = V
SS
CS = V , V = V or V
CC
CC
IN
SS
V Supply Current
CC
(Standby)
∝A
∝A
I
I
V
= V to V
IN SS CC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output HIGH Voltage
10
10
LI
V
OUT
= V to V
SS CC
LO
(1)
(1)
V
V
x 0.3
V
V
V
–0.5
V
V
V
V
V
V
V
V
CC
IL
V
x 0.7
+ 0.5
CC
CC
IH
V
> 3.3V, I = 2.1mA
OL
0.4
OL1
OL2
OL3
OH1
OH2
OH3
CC
V
V
V
V
V
2V < V = 3.3V, I
CC
OL
0.4
0.4
= 1mA
V
V
= 2V, I
= 0.5mA
= -1.0mA
OH
CC
OL
V
V
V
– 0.8
– 0.4
– 0.2
> 3.3V, I
CC
CC
CC
CC
2V < V = 3.3V, I
CC
= -0.4mA
OH
V
= 2V, I
OH
= -0.25mA
CC
7033 FRM T06
POWER-UP TIMING
Symbol
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min.
Max.
Units
(2)
t
t
1
5
ms
PUR
PUW
(2)
ms
7033 FRM T07
Notes: (1)V Min. and V Max. are for reference only and are not 100% tested.
IL IH
(2)t
PUR
and t
PUW
are the delays required from the time V
is stable until the specified operation can be initiated. These parameters
CC
are periodically sampled and not 100% tested.
8
X25057
CAPACITANCE T = +25°C, f = 1MHz, V = 5.0V.
CC
A
Symbol
Parameter
Max.
Units
pF
Conditions
= 0V
(3)
OUT
V
C
C
Output Capacitance (SO)
8
6
OUT
(3)
IN
V
IN
= 0V
Input Capacitance (SCK, SI, CS, WP)
pF
7033 FRM T08
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
V
Input Pulse Levels
CC
x 0.1 to
5V
3.3V
2V
V
CC
x 0.9
10ns
Input Rise and Fall
Times
2061Ο
2696Ο
2800Ο
OUTPUT
3025Ο
OUTPUT
5288Ο
OUTPUT
5600Ο
V
X 0.5
Input and Output
Timing Level
CC
30pF
30pF
30pF
7033 FRM T09
7033 FRM F09.1
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Data
Input Timing
Symbol
Parameter
Clock Frequency
Voltage
Min.
Max.
Units
f
t
t
t
t
t
0
5
MHz
SCK
2.7V–5.5V
1.8V–3.6V
3.3
Cycle Time
200
300
ns
ns
ns
ns
ns
ns
CYC
LEAD
LAG
WH
2.7V–5.5V
1.8V–3.6V
CS Lead Time
CS Lag Time
100
150
2.7V–5.5V
1.8V–3.6V
100
150
2.7V–5.5V
1.8V–3.6V
Clock HIGH Time
Clock LOW Time
80
2.7V–5.5V
1.8V–3.6V
130
80
WL
2.7V–5.5V
1.8V–3.6V
130
t
t
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
CS Deselect Time
Write Cycle Time
20
20
SU
ns
H
(3)
∝s
t
t
t
t
2
2
RI
(3)
∝s
FI
100
ns
CS
(4)
WC
10
ms
7033 FRM T10
Notes: (3)This parameter is periodically sampled and not 100% tested.
(4)tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
9
X25057
Data Output Timing
Symbol
Parameter
Voltage
Min.
Max.
Units
f
t
t
Clock Frequency
0
5
MHz
SCK
DIS
V
2.7V–5.5V
1.8V–3.6V
3.3
Output Disable Time
100
150
ns
ns
2.7V–5.5V
1.8V–3.6V
Output Valid from Clock LOW
80
2.7V–5.5V
1.8V–3.6V
130
t
t
t
Output Hold Time
Output Rise Time
Output Fall Time
0
ns
ns
HO
(5)
50
50
RO
(5)
FO
ns
7033FRM T11
Notes: (5)This parameter is periodically sampled and not 100% tested.
Figure 8. Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tHO
tWL
tV
tDIS
SO
SI
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
7033 FRM F10
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Changing:
State Not
Known
Don’t Care:
Changes
Allowed
N/A
Center Line
is High
Impedance
10
X25057
Figure 9. Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tH
tSU
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
7033 FRM F11
11
X25057
PACKAGING INFORMATION
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 0.002
(3.00 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) TYP
R 0.014 (0.36)
0.118 0.002
(3.00 0.05)
0.030 (0.76)
0.0216 (0.55)
7° TYP
0.036 (0.91)
0.032 (0.81)
0.040 0.002
(1.02 0.05)
0.008 (0.20)
0.004 (0.10)
0.150 (3.81)
0.007 (0.18)
0.005 (0.13)
REF.
0.193 (4.90)
REF.
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3003 FRM 01
12
X25057
PACKAGING INFORMATION
8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.114 (2.9)
.122 (3.1)
.047 (1.20)
.002 (.05)
.006 (.15)
.0075 (.19)
.0118 (.30)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X25057
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.050" TYPICAL
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FRM F22.1
14
X25057
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
0.060 (1.52)
0.020 (0.51)
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP
0.010 (0.25)
.
NOTE:
1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.
PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
15
X25057
ORDERING INFORMATION
X25057
P
T
G –V
V
CC
Limits
Blank = 4.5V to 5.5V
2.7 = 2.7V to 5.5V
1.8 = 1.8V to 3.6V
Device
G=RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
M = 8-Lead MSOP
V = 8-Lead TSSOP
S = 8-Lead SOIC
P = 8-Lead PDIP
Part Mark Convention
8-Lead MSOP
8-Lead TSSOP
8-Lead SOIC/PDIP
Blank = 8-Lead SOIC
EYWW
5057XX
EYWW
XXX
X25057 G
XXX
P = 8-Lead PDIP
G = RoHS compliant
leadfree
AG = 1.8 to 3.6V, 0 to +70°C
AH = 1.8 to 3.6V, -40 to +85°C
F = 2.7 to 5.5V, 0 to +70°C
G = 2.7 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
AAA = 1.8 to 3.6V, 0 to +70°C
AAC = 1.8 to 3.6V, -40 to +85°C
AAO = 2.7 to 5.5V, 0 to +70°C
AAP = 2.7 to 5.5V, -40 to +85°C
AAF = 4.5 to 5.5V, 0 to +70°C
AAG = 4.5 to 5.5V, -40 to +85°C
AG = 1.8 to 3.6V, 0 to +70°C
AH = 1.8 to 3.6V, -40 to +85°C
F = 2.7 to 5.5V, 0 to +70°C
G = 2.7 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production
and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign
patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
16
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