X25170 [ICMIC]
SPI Serial E 2 PROM with Block Lock ⑩ Protection; SPI串行ê 2 PROM与块锁保护⑩
| 型号： | X25170 |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | SPI Serial E 2 PROM with Block Lock ⑩ Protection |
| 文件： | 总15页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
ICmic
2K x 8 Bit
This X25170 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
16K
X25170
SPI Serial E 2PROM with Block Lock ™ Protection
FEATURES
DESCRIPTION
The X25170 is a CMOS 16384-bit serial E2PROM,
internally organized as 2K x 8. The X25170 features a
•5MHz Clock Rate
•SPI Modes (0,0 & 1,1)
•2K X 8 Bits
Serial Peripheral Interface (SPI) and software protocol,
allowing operation on a simple three-wire bus. The bus
—32 byte page mode
•Low Power CMOS
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
—<1µA standby current
—<5mA active current
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
•2.5V To 5.5V Power Supply
•Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM array
The X25170 also features two additional inputs that
provide the end user with added flexibility. By asserting
•Built-In Inadvertent Write Protection
—Power-up/power-down protection circuitry
the HOLD input, the X25170 will ignore transitions on its
inputs, thus allowing the host to service higher prior-
—Write enable latch
—Write protect pin
•Self-Timed Write Cycle
ity interrupts. The WP input can be used as a hardwire input
to the X25170 (disabling all write attempts to the
status register), thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
—5ms write cycle time (typical)
•High Reliability
—Endurance: 100,000 cycles
—Data retention: 100 Years
The X25170 utilizes Xicor’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
—ESD protection: 2000V on all pins
•8-Lead PDlP Package
•8-Lead SOIC Package
•14-Lead TSSOP Package
BLOCK DIAGRAM
Write
Protect
Logic
Status
Register
X Decode
2K Byte
Logic
Array
16
16
16 X 256
SO
SI
Command
Decode
and
Control
Logic
SCK
CS
16 X 256
32 X 256
HOLD
32
Write
Control
and
Timing
Logic
WP
32
8
Y Decode
Data Register
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©
Xicor, Inc. 2000 Patents Pending
Characteristics subject to change without notice. 1 of 15
9900-5004.9 5/26/00 EP
X25170
PIN DESCRIPTIONS
Serial Output (SO)
Pin Names
Symbol
CS
Description
Chip Select Input
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
SO
Serial Output
Serial Input
SI
SCK
WP
Serial Clock Input
Write Protect Input
Ground
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
V
SS
V
Supply Voltage
Hold Input
CC
HOLD
NC
No Connect
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
PIN CONFIGURATION
DIP/SOIC
1
2
8
7
6
5
CS
SO
V
CC
HOLD
SCK
SI
X25170
WP
3
4
Chip Select (CS)
V
SS
It should be noted that after power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
TSSOP
X25170
1
CS
SO
14
13
V
When CS is HIGH, the X25170 is deselected and the
SO output pin is at high impedance; unless an internal
write operation is underway, the X25170 will be in the
standby power mode. CS LOW enables the X25170,
placing it in the active power mode.
CC
2
3
HOLD
NC
12
11
10
9
NC
NC
NC
WP
4
NC
NC
5
6
7
SCK
SI
V
SS
8
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25170 status register are dis-
abled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25170 status reg-
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no effect on a write.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25170 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Characteristics subject to change without notice. 2 of 15
X25170
PRINCIPLES OF OPERATION
Status Register
The X25170 is a 2K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The X25170 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising SCK. CS must be LOW and the HOLD
and WP inputs must be HIGH during the entire opera-
tion.The WP input is “don’t care” if WPEN is set “0”.
7
6
5
4
3
2
1
0
WPEN
X
X
X
BL1
BL0
WEL
WIP
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25170 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25170 into a “PAUSE” condition. After releasing
HOLD, the X25170 will resume operation from the
point when HOLD was first asserted.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25170 is divided into four 4096-bit seg-
ments. One, two, or all four of the segments may be
protected. That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated in
the following table.
Write Enable Latch
The X25170 contains a “write enable” latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Status Register Bits
Array Addresses
BP1
BP0
Protected
0
0
1
1
0
1
0
1
None
$0600–$07FF
$0400–$07FF
$0000–$07FF
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
RDSR
WRSR
READ
WRITE
Write status register
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address (1 to 32 Bytes)
Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Characteristics subject to change without notice. 3 of 15
X25170
Write-Protect Enable
WPEN bit is “0”. When the chip is hardware write pro-
tected, nonvolatile writes are disabled to the Status
Register, including the Block Protect bits and the
WPEN bit itself, as well as the block-protected sections
in the memory array. Only the sections of the memory
array that are not block-protected can be written.
The Write-Protect-Enable (WPEN) bit is available for
the X25170 as a nonvolatile enable bit for the WP pin.
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register con-
trol the programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
LOW, and the WPEN bit is “1”. Hardware write protec-
tion is disabled when either the WP pin is HIGH or the
Note: Since the WPEN bit is write protected, it cannot
be changed back to a “0”, as long as the WP pin is held
LOW.
WPEN
WP
X
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
X
Protected
Writable
LOW
LOW
HIGH
HIGH
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
Clock and Data Timing
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($07FF), the
address counter rolls over to address $0000, allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
read E2PROM array operation sequence illustrated in
Figure 1.
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25170, followed by the
16-bit address of which the last 11 are used. After the
READ opcode and address are sent, the data stored in
the memory at the selected address is shifted out on the
SO line. The data stored in memory at the next address
can be read sequentially by continuing to provide clock
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the con-
tents of the status register are shifted out on the SO
line. The read status register sequence is illustrated in
Figure 2.
Characteristics subject to change without notice. 4 of 15
X25170
Figure 1. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
Instruction
Data Out
High Impedance
7
MSB
6
5
4
3
2
1
0
SO
Write Sequence
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 32 bytes of data to the
X25170. The only restriction is the 32 bytes must reside
on the same page. If the address counter reaches the
end of the page and the clock continues, the counter will
“roll over” to the first address of the page and overwrite
any data that may have been written.
Prior to any attempt to write data into the X25170, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25170. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
Characteristics subject to change without notice. 5 of 15
X25170
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Figure 4. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16 Bit Address
15 14 13
Data Byte
3
2
1
0
7
6
5
4
3
2
1
0
High Impedance
SO
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”.This sequence is shown in Figure 6.
Hold Operation
The HOLD input should be HIGH (at V ) under normal
IH
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW, and SCK
must also be LOW when HOLD is released.
While the write is in progress following a status register
or E2PROM write sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be HIGH.
The HOLD input may be tied HIGH either directly to
V
or tied to V through a resistor.
CC
CC
Characteristics subject to change without notice. 6 of 15
X25170
Figure 5. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
13
Data Byte 1
7
6
5
4
3
2
1
0
3
2
1
0
SI
15
14
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Figure 6. Write Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
Instruction
Data Byte
SI
7
6
5
4
3
2
1
0
High Impedance
SO
Operational Notes
Data Protection
The X25170 powers-up in the following state:
The following circuitry has been included to prevent
inadvertent writes:
– The device is in the low power standby state.
– The “write enable” latch is reset upon power-up.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– A WREN instruction must be issued to set the “write
enable” latch.
– SO pin is high impedance.
– CS must come HIGH at the proper clock count in order
to start a write cycle.
– The “write enable” latch is reset.
Characteristics subject to change without notice. 7 of 15
X25170
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ........................–65 to +135°C
Storage temperature .............................–65 to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
Voltage on any pin with respect to V .......–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
X25170
Limits
5V ±10%
–40°C
–55°C
X25170-2.5
2.5V to 5.5V
Military
D.C. OPERATING CHARACTERISTICS(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCK = V x 0.1/V x 0.9 @ 2MHz,
I
V
supply current (active)
5
mA
CC
CC
CC
CC
SO = Open, CS = V
SS
SS
SO = Open, CS = V
SO = Open, CS = V
SS
I
V
supply current (standby)
1
µA
µA
µA
V
CS = V , V = V or V
CC IN SS CC
SB
CC
I
Input leakage current
Output leakage current
Input LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(1)
V
–1
V
x 0.3
IL
CC
(1)
V
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
Output LOW voltage
Output HIGH voltage
V
x 0.7
V
+ 0.5
V
IH
CC
CC
V
0.4
V
V
V
V
V
= 5V, I = 3mA
OL
OL1
CC
CC
CC
CC
V
V
–0.8
–0.3
V
= 5V, I
= -1.6mA
OH1
CC
OH
V
0.4
V
= 2.70V, I = 1.5mA
OL
OL2
V
V
V
= 2.70V, I
= -0.4mA
OH2
CC
OH
POWER-UP TIMING
Symbol
Parameter
Power-up to read operation
Power-up to write operation
Min.
Max.
Units
ms
(3)
PUR
T
1
1
(3)
PUW
T
ms
Characteristics subject to change without notice. 8 of 15
X25170
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
pF
Test Conditions
= 0V
(2)
C
Output capacitance (SO)
8
6
V
OUT
OUT
(2)
IN
C
Input capacitance (SCK, SI, CS, WP, HOLD)
pF
V
= 0V
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
(3) t and t are the delays required from the time V
is stable until the specified operation can be initiated. These parameters
CC
PUR
PUW
are periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
3V
Input rise and fall times
Input and output timing levels
10ns
1.44KΩ
Output
1.95KΩ
1.64KΩ
Output
4.63KΩ
V
X 0.5
CC
100pF
100pF
A.C. CHARACTERISTICS (Over recommended operationg conditions, unless otherwise specified.)
Data Input Timing
Symbol
Parameter
Min.
0
Max.
Units
MHz
ns
f
Clock frequency
Cycle time
5
SCK
CYC
t
200
100
100
80
t
CS lead time
ns
LEAD
t
CS lag time
ns
LAG
t
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Data in rise time
Data in fall time
HOLD setup time
HOLD hold time
CS deselect time
Write cycle time
ns
WH
t
80
ns
WL
t
20
ns
SU
t
20
ns
H
(4)
t
t
2
2
µs
RI
(4)
µs
FI
t
40
40
ns
HD
CD
t
ns
t
100
ns
CS
(5)
WC
t
10
ms
Characteristics subject to change without notice. 9 of 15
X25170
Data Output Timing
Symbol
Parameter
Min.
Max.
5
Units
MHz
ns
f
Clock frequency
0
SCK
t
Output disable time
100
80
DIS
t
Output valid from clock LOW
Output hold time
ns
V
t
0
ns
HO
(4)
t
t
Output rise time
50
50
ns
RO
(4)
Output fall time
ns
FO
(4)
t
HOLD HIGH to output in low Z
HOLD LOW to output in high Z
50
50
ns
LZ
(4)
HZ
t
ns
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
t
t
t
t
DIS
WL
V
HO
SO
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
Serial Input Timing
t
CS
CS
t
t
LEAD
LAG
SCK
t
t
t
t
FI
SU
H
RI
SI
MSB IN
LSB IN
High Impedance
SO
Characteristics subject to change without notice. 10 of 15
X25170
Hold Timing
CS
SCK
SO
t
t
t
CD
HD
CD
t
HD
t
t
LZ
HZ
SI
HOLD
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 11 of 15
X25170
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 12 of 15
X25170
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050"Typical
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 13 of 15
X25170
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 15
X25170
Ordering Information
T
X25170
P
G -V
VCC Limits
Blank = 5V 10%
2.5 = 2.5V to 5.5V
Device
G = RoHS Compliant Lead-Free package
Blank = Standard package. Non lead-free
Temperature Range
Blank = Commercial = 0° C to +70° C
I = Industrial = –40° C to +85° C
Package
S8 = 8-Lead SOIC
Part Mark Convention
X25170
XG
X
G = RoHS compliant lead free
Blank = 8-Lead SOIC
Blank = 5V 10%, 0°C to +70°C
I = 5V 10%, –40°C to +85°C
AE = 2.5V to 5.5V, 0°C to +70°C
AF = 2.5V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory,
implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of
merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others
belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706;
4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927;
5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction,
redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 15 of 15
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