X25642SM [ICMIC]
Advanced SPI Serial E2PROM with Block Lock Protection; 先进的SPI串行E2PROM与块锁保护
| 型号： | X25642SM |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | Advanced SPI Serial E2PROM with Block Lock Protection |
| 文件： | 总16页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
ICmic
8K x 8 Bit
This X25642 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
64K
X25642
2
TM
Advanced SPI Serial E PROM with Block Lock Protection
FEATURES
DESCRIPTION
The X25642 is a CMOS 65,536-bit serial E2PROM,
internally organized as 8K x 8. The X25642 features a
•2MHz Clock Rate
•Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
•2.7V To 5.5V Power Supply
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
•SPI Modes (0,0 & 1,1)
•8K X 8 Bits
—32 Byte Page Mode
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
•Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
•Built-in Inadvertent Write Protection
—Power-Up/Down protection circuitry
—Write Enable Latch
The X25642 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25642 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as a
hardwire input to the X25642 disabling all write
—Write Protect Pin
•Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
•High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
•Packages
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25642 utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
—8-Lead PDIP
—8-Lead SOIC
—14-Lead SOIC
—20-Lead TSSOP
FUNCTIONAL DIAGRAM
WRITE
PROTECT
LOGIC
STATUS
REGISTER
X DECODE
LOGIC
8K BYTE
ARRAY
64
64
64 X 256
64 X 256
SO
SI
COMMAND
DECODE
SCK
AND
CONTROL
LOGIC
CS
HOLD
128
128 X 256
WRITE
CONTROL
AND
TIMING
LOGIC
WP
32
8
Y DECODE
DATA REGISTER
3132 ILL F01.1
Direct WriteTM and Block Lock ProtectionTM is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
1
Characteristics subject to change without notice
3132-1.0 1/17/97 T5/C0/D1 SH
X25642
X25642 status register. If the internal write cycle has
already been initiated, WP going LOW will have no
affect on a write.
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25642 in a system with WP pin grounded and still
be able to write to the status register.The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
PIN CONFIGURATION
Not to Scale
SOIC/DIP
CS
SO
WP
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
Chip Select (CS)
.197"
SOIC
Only
X25642
When CS is HIGH, the X25642 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25642 will be
in the standby power mode. CS LOW enables the
X25642, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
V
SS
.244"
SOIC
NC
CS*
CS*
SO
1
2
3
4
5
6
7
14
13
12
NC
NC
Write Protect (WP)
V
CC
.345"
X25642 11
HOLD
SCK
SI
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25642 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including
nonvolatile writes operate normally. WP going LOW
while CS is still LOW will interrupt a write to the
WP
10
9
V
SS
NC
8
NC
.244"
TSSOP
PIN NAMES
20
NC
NC
CS
NC
SO
NC
NC
WP
1
Symbol
CS
Description
Chip Select Input
2
19
V
CC
3
18
NC
4
17
SO
Serial Output
Serial Input
HOLD
NC
5
16
SI
.300"
X25642
6
15
NC
SCK
WP
Serial Clock Input
Write Protect Input
Ground
7
14
SCK
SI
8
13
V
SS
NC
NC
VSS
9
12
NC
VCC
HOLD
NC
Supply Voltage
Hold Input
10
11
NC
.252"
No Connect
3132 ILL F02.5
7037 FRM T01
* Pin 2 and Pin 3 are internally connected. Only one CS needs to
be connected externally.
2
X25642
Status Register
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is
formatted as follows:
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
WIP
PRINCIPLES OF OPERATION
7037 FRM T02
The X25642 is a 8K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral inter-
face (SPI) of many popular microcontroller families.
WPEN, BP0 and BP1 are set by the WRSR instruc-
tion. WEL and WIP are read-only and automatically set
by other operations.
The X25642 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and
WP inputs must be HIGH during the entire operation.
The Write-In-Process (WIP) bit indicates whether the
X25642 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25642 into a “PAUSE” condition. After releasing
HOLD, the X25642 will resume operation from the
point when HOLD was first asserted.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of
protection. The X25642 is divided into four 16384-bit
segments. One, two, or all four of the segments may
be protected. That is, the user may read the segments
but will be unable to alter (write) data within the
selected segments. The partitioning is controlled as
illustrated below.
Write Enable Latch
Status Register Bits
Array Addresses
Protected
The X25642 contains a “write enable” latch. This latch
must be SET before a write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status
register write cycle.
BP1
BP0
0
0
1
1
0
1
0
1
None
$1800–$1FFF
$1000–$1FFF
$0000–$1FFF
7037 FRM T03
Table 1. Instruction Set
Instruction Name
WREN
Instruction Format*
0000 0110
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
WRDI
0000 0100
RDSR
0000 0101
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected address
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address (1 to 32
Bytes)
7037 FRM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25642
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Figure 2 illustrates the read status register sequence.
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the
X25642 as a nonvolatile enable bit for the WP pin.
Protected Unprotected Status
WPEN
WEL Blocks
Blocks
Protected Protected Protected
Protected Writable Writable
Protected Protected Protected
Protected Writable Protected
Protected Protected Protected
Register
WP
X
Write Sequence
0
0
1
1
X
X
0
1
0
1
0
1
Prior to any attempt to write data into the X25642, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25642. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation
will be ignored.
X
LOW
LOW
HIGH
HIGH
Protected
Writable
Writable
7037 FRM T05
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when WP
pin is LOW, and the WPEN bit is “1”. Hardware write
protection is disabled when either the WP pin is HIGH
or the WPEN bit is “0”. When the chip is hardware write
protected, nonvolatile writes are disabled to the Status
Register, including the Block Protect bits and the
WPEN bit itself, as well as the block-protected sections
in the memory array. Only the sections of the memory
array that are not block-protected can be written.
2
To write data to the E PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 32 bytes of data to the
X25642.The only restriction is the 32 bytes must reside
on the same page. If the address counter reaches the
end of the page and the clock continues, the counter
will “roll over” to the first address of the page and over-
write any data that may have been written.
Note: Since the WPEN bit is write protected, it cannot
be changed back to a “0”, as long as the WP pin
is held LOW.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustra-
tion of the write sequences and time frames in which
CS going HIGH are valid.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. Figure 6 illustrates this sequence.
Read Sequence
2
When reading from the E PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25642, followed by
the 16-bit address of which the last 13 are used. After
the READ opcode and address are sent, the data
stored in the memory at the selected address is
shifted out on the SO line. The data stored in memory
at the next address can be read sequentially by
continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached ($1FFF) the address counter rolls
over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is termi-
While the write is in progress following a status
2
register or E PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.
2
nated by taking CS HIGH. Refer to the read E PROM
array operation sequence illustrated in Figure 1.
The HOLD input may be tied HIGH either directly to
VCC or tied to VCC through a resistor.
4
X25642
Data Protection
Operational Notes
The following circuitry has been included to prevent in-
advertent writes:
The X25642 powers-up in the following state:
• The device is in the low power standby state.
• The “write enable” latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• A WREN instruction must be issued to set the “write
enable” latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in or-
der to start a write cycle.
• The “write enable” latch is reset.
2
Figure 1. Read E PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3132 ILL F03.1
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
SO
3132 ILL F04
5
X25642
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
3132 ILL F05
Figure 4. Byte Write Operation Sequence
CS
20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
INSTRUCTION
16 BIT ADDRESS
DATA BYTE
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3132 ILL F06.1
6
X25642
Figure 5. Page Write Operation Sequence
CS
20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
DATA BYTE 1
3
2
1
0
7
6
5
4
3
2
1
0
CS
SCK
SI
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
3132 ILL F07
Figure 6. Write Status Register Operation Sequence
CS
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
7
9
6
SCK
SI
INSTRUCTION
DATA BYTE
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3132 ILL F08.1
7
X25642
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias....................–65°C to +135°C
Storage Temperature ........................–65°C to +150°C
Voltage on any Pin with Respect
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
to V .........................................................–1V to +7V
SS
D.C. Output Current ............................................. 5mA
(Soldering, 10 seconds) ..............................300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Min.
0°C
Max.
+70°C
Supply Voltage
Limits
5V ±10%
X25642
Industrial
Military
–40°C
–55°C
+85°C
X25642-2.7
2.7V to 5.5V
+125°C
7037 FRM T07
7037 FRM T06
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
ICC
Parameter
VCC Supply Current (Active)
VCC Supply Current (Standby)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Units
mA SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
µA CS = VCC, VIN = V or VCC – 0.3V
Test Conditions
Min.
Max.
5
ISB
1
10
SS
ILI
µA VIN = V to VCC
SS
ILO
10
µA VOUT = V to VCC
SS
(1)
VIL
–1
VCC x 0.3
V
V
(1)
VIH
Input HIGH Voltage
VCC x 0.7 VCC + 0.5
VOL1
VOH1
VOL2
VOH2
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
0.4
VCC–0.8
V
V
V
V
IOL = 3mA, VCC = 5V
IOH = –1.6mA, VCC = 5V
IOL = 1.5mA, VCC = 3V
IOH = –0.4mA, VCC = 3V
0.4
VCC–0.3
7037 FRM T08
POWER-UPTIMING
Symbol
Parameter
Min.
Max.
Units
ms
(3)
TPUR
Power-up to Read Operation
Power-up to Write Operation
1
1
(3)
TPUW
ms
7037 FRM T09
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
Test Conditions
(3)
CI/O
Output Capacitance (SO)
8
6
pF
pF
VI/O = 0V
(3)
CIN
Input Capacitance (SCK, SI, CS, WP, HOLD)
VIN = 0V
7037 FRM T10
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
(3) t and t are the delays required from the time V is stable until the specified operation can be initiated. These
PUR
PUW
CC
parameters are periodically sampled and not 100% tested.
8
X25642
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
10ns
5V
3V
Input Rise and Fall Times
Input and OutputTiming Levels
1.44KΩ
OUTPUT
1.95KΩ
1.64KΩ
OUTPUT
4.63KΩ
VCC X 0.5
7037 FRM T11
100pF
100pF
3132 ILL F09.2
A.C. OPERATING CHARACTERISTICS
Data Input Timing
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
Parameter
Clock Frequency
Min.
0
Max.
Units
MHz
ns
2
Cycle Time
500
250
250
200
200
50
CS Lead Time
ns
CS Lag Time
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Write Cycle Time
ns
tWL
ns
tSU
ns
tH
50
ns
(4)
tRI
2
2
µs
(4)
tFI
µs
tHD
tCD
tCS
100
100
2.0
ns
ns
µs
(5)
tWC
10
ms
7037 FRM T12
Data Output Timing
Symbol
fSCK
tDIS
Parameter
Min.
Max.
2
Units
MHz
ns
Clock Frequency
0
Output Disable Time
250
200
tV
Output Valid from Clock LOW
Output Hold Time
ns
tHO
0
ns
(4)
tRO
Output Rise Time
100
100
ns
(4)
tFO
Output Fall Time
ns
(4)
tLZ
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
100
100
ns
(4)
tHZ
ns
7037 FRM T13
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle.
9
X25642
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
tHO
tWL
tDIS
SO
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
SI
3132 ILL F10.1
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
3132 ILL F11
10
X25642
Hold Timing
CS
SCK
SO
tHD
tCD
tCD
tHD
tHZ
tLZ
SI
HOLD
3132 ILL F12.1
11
X25642
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
12
X25642
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
13
X25642
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULLWING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0° – 8°
0.050" Typical
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.41)
0.037 (0.937)
0.030" Typical
14 Places
FOOTPRINT
NOTE:ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F10
14
X25642
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.300 (6.6)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F45
15
X25642
ORDERING INFORMATION
X25642
P
T
G -V
Vcc Limits
Blank = 5V 10%
2.7 = 2.7 to 5.5V
Device
G = RoHS Compliant Lead-Free package
Blank = Standard package. Non lead-free
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°
Package
P = 8-Lead Plastic DIP
S = 14-Lead SOIC
S8 = 8-Lead SOIC
V = 20-Lead TSSOP
Part Mark Convention
X25642
X G
P = 8-Lead Plastic DIP
S = 14-Lead SOIC
Blank = 8 Lead SOIC
V = 20-Lead TSSOP
G = RoHS compliant lead free
X
Blank = 5V 10%, 0°C to +70°C
I = 5V 10%, –40°C to +85°C
M = 5V 10%, –55°C to +125°C
F = 2.7V to 5.5V, 0°C to 70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor,Inc. reserves the right to discontinue production and
change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses
are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign
patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
16
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