X76F640H-2.7 [ICMIC]
Secure Serial Flash; 安全串行闪存
| 型号： | X76F640H-2.7 |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | Secure Serial Flash |
| 文件： | 总17页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This X76F640 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
64K
8Kx8+32x8
X76F640
Secure Serial Flash
FEATURES
DESCRIPTION
•64-bit Password Security
—Five 64-bit Passwords for Read, Program
The X76F640 is a Password Access Security Supervisor,
containing one 65536-bit Secure Serial Flash array and
and Reset
•8192 Byte+32 Byte Password Protected Arrays
one 256-bit Secure Serial Flash array. Access to each
memory array is controlled by two 64-bit passwords.
—Seperate Read Passwords
—Seperate Write Passwords
These passwords protect read and write operations of
the memory array. A separate RESET password is used
—Reset Password
•Programmable Passwords
•Retry Counter Register
to reset the passwords and clear the memory arrays in the
event the read and write passwords are lost.
The X76F640 features a serial interface and software
protocol allowing operation on a popular two wire bus.
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
The bus signals are a clock Input (SCL) and a bidirectional
data input and output (SDA). Access to the device
•32-bit Response to Reset (RST Input)
•32 byte Sector Program
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
•400kHz Clock Rate
•2 wire Serial Interface
•Low Power CMOS
The X76F640 also features a synchronous response to reset
providing an automatic output of a hard-wired 32-bit
—2.7 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
data stream conforming to the industry standard for
memory cards.
•High Reliability Endurance:
—100,000 Write Cycles
The X76F640 utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles
•Data Retention: 100 years
•Available in:
and a minimum data retention of 100 years.
—8 lead SOIC
—SmartCard Module
Functional Diagram
CS
CHIP ENABLE
8K BYTE
SerialFlash ARRAY
ARRAY 0
DATA TRANSFER
SCL
(PASSWORD PROTECTED)
SDA
ARRAY ACCESS
ENABLE
INTERFACE
LOGIC
32 BYTE
SerialFlash ARRAY
ARRAY 1
PASSWORD ARRAY
AND PASSWORD
(PASSWORD PROTECTED)
VERIFICATION LOGIC
RST
RETRY COUNTER
RESET
RESPONSE REGISTER
7025 FM 01
Characteristics subject to change without notice
∧Xicor, Inc. 1994, 1995, 1996 Patents
Pending 7025-1.4 3/24/97 T2/C0/D1 SH
1
X76F640
PIN DESCRIPTIONS
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
If the X76F640 is in a nonvolatile write cycle a “no A
CK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
mode.
Serial Data (SDA)
SDA is a true three state serial data input/output pin. Dur- ing a
read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
The basic sequence is illustrated in Figure 1.
Chip Enable (CS)
When CS is high, the X76F640 is deselected and the
SDA pin is at high impedance and unless an internal
PIN NAMES
Symbol
CS
Description
Chip Select Input
write operation is underway, the X76F640 will be in
standby mode. CS low enables the X76F640, placing it in
the active mode.
SDA
SCL
RST
Vcc
Vss
NC
Serial Data Input/Output
Serial Clock Input
Reset Input
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F640 will output 32 bits of fixed
Supply Voltage
Ground
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
No Connect
7025 FM T01
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
PIN CONFIGURATION
Smart Card
DEVICE OPERATION
SOIC
There are two primary modes of operation for the
X76F640; Protected READ and protected WRITE.
VSS
VCC
1
2
8
7
6
5
Protected operations must be performed with one of four
8-byte passwords.
RST
CS
SDA
NC
3
4
SCL
NC
The basic method of communication for the device is
established by first enabling the device (CS LOW), gen-
GND
CS
VCC
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
RST
shipped from the factory with all passwords equal to ‘0’. The
user must perform ACK Polling to determine the
SCL
NC
SDA
NC
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed, can
the data transfer occur.
7025 FM 02
To ensure the correct communication, RST must remain LOW
under all conditions except when running a
“Response to Reset sequence”.
After each transaction is completed, the X76F640 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
2
X76F640
Figure 1. X76F640 Device Operation
Start Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
LOAD COMMAND BYTE
HIGH. The X76F640 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
any command until this condition is met.
LOAD 8-BYTE
PASSWORD
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
not be generated while the part is outputting data. Starts are
inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop condition.
The stop condition is a LOW to HIGH transition of
LOAD 2 BYTE ADDRESS
SDA when SCL is HIGH. The stop condition is also used to
reset the device during a command or data input
READ/WRITE
DATA BYTES
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
Twc OR DATA ACK POLLING
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
7025 FM 03
Retry Counter
The X76F640 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data.
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
The X76F640 will respond with an acknowledge after
recognition of a start condition and its slave address. If
flows, all memory areas are cleared and the device is
locked by preventing any read or write array password
both the device and a write condition have been
selected, the X76F640 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
matches. The passwords are unaffected. If a correct
password is received prior to retry counter overflow, the
retry counter is reset and access is granted. In order to reset
the operation of a locked up device, a special reset
command must be used with a RESET password.
Reset Device Command
The reset device command is used to clear the retry
counter and reactivate the device. When the reset device
Device Protocol
The X76F640 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
command is used prior to the retry counter overflow, the
retry counter is reset and no arrays or passwords are
affected. If the retry counter has overflowed, all memory
areas are cleared and all commands are blocked and the
onto the bus as a transmitter and the receiving device as a
receiver. The device controlling the transfer is a master
retry counter is disabled. Issuing a valid reset device
command (with reset password) to the device resets and
and the device being controlled is the slave. The master will
always initiate data transfers and provide the clock for
re-enables the retry counter and re-enables the other
commands. Again, the passwords are not affected.
both transmit and receive operations. Therefore, the
X76F640 will be considered a slave in all applications.
Reset Password Command
A reset password command will clear both arrays and set all
passwords to all zero.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
3
X76F640
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
7025 FM 04
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
7025 FM 05
Table 1. X76F640 Instruction Set
1st Byte
after
Password
2nd Byte
after
Password
1st Byte
after Start
Password
used
Command Description
Read (Array 0)
1000 0000 High Address Low address
1000 1000 High Address Low address
1001 0000 High Address Low address
1001 1000 High Address Low address
Read 0
Read 1
Write 0
Write 1
Read 0
Read 1
Write 0
Write 1
Reset
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
1010 0000
1010 1000
1011 0000
1011 1000
1100 0000
1110 0000
1110 1000
1111 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
Reset Password Command
Reset Device Command
ACK Polling command (Ends Password operation)
Reserved
Reset
not used
not used
Reset
not used
not used
None
All the rest
7025 FM T04
Notes:Illegal command codes will be disregarded. The part will respond with a “no-A
CK” to the illegal byte and then return to the standby mode.
All write/read operations require a password.
4
X76F640
PROGRAM OPERATIONS
Sector Programming
The sector program mode requires issuing the 8-bit write
command followed by the password, password Ack com-
mand, the address and then the data bytes transferred as
illustrated in figure 4. Up to 32 bytes may be trans-
ferred. After the last byte to be transferred is acknowl-
edged a stop condition is issued which starts the
nonvolatile write cycle.
Figure 4. Sector Programming
Write
Password
Write
Password
0
COMMAND
7
Wait tWC OR
Repeated
ACK Polling
Command
SDA
S
If ACK, Then
Password Matches
ACK POLLING
COMMAND
Data 0
. . .
S
Data 31
Wait tWC Data
ACK Polling
S
7025 FM 07
5
X76F640
requires the master to perform an ACK polling with the
specific code of F0h. As with regular Acknowledge polling
ACK Polling
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F640 initiates the internal
the user can either time out for 10ms, and then issue the ACK
polling once, or continuously loop as described in the
flow.
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin
immediately. This involves issuing the start condition
followed by the new command code of 8 bits (1st byte of
Password ACK Polling Sequence
the protocol.) If the X76F640 is still busy with the
nonvolatile write operation, it will issue a “no-A
PASSWORD LOAD
COMPLETED
CK” in response. If the nonvolatile write operation has
completed, an “ACK” will be returned and the host can
ENTER ACK POLLING
ISSUE START
then proceed with the rest of the protocol.
Data ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ISSUE
PASSWORD
ENTER ACK POLLING
ACK COMMAND
ISSUE START
NO
ACK
RETURNED?
ISSUE NEW
COMMAND
YES
CODE
PROCEED
NO
ACK
RETURNED?
7025 FM 09
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle is over,
YES
PROCEED
in response to the ACK polling cycle immediately following
it.
7025 FM 08
If the password that was inserted was incorrect, then a “no
ACK” will be returned even if the nonvolatile cycle is over.
After the password sequence, there is always a nonvola-
tile write cycle. This is done to discourage random
Therefore, the user cannot be certain that the password is
incorrect until the 10ms write cycle time has elapsed.
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F640
6
X76F640
Figure 5. Acknowledge Polling
SCL
SDA
8th clk.
of 8th
pwd. byte
8th
clk
‘ACK’
clk
‘ACK’
clk
8th bit
‘ACK’
ACK or
no ACK
START
condition
7025 FM 10
READ OPERATIONS
Sequential Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
Read operations are initiated in the same manner as write
operations but with a different command code.
sequential, with the data from address n followed by the
data from n+1. The address counter for read operations
Random Read
The master issues the start condition and a Read instruction
and password, performs a Password Ack Polling, then
increments all address bits, allowing the entire memory
array contents to be serially read during one operation. At
the end of the address space (address 1FFFh for array 0, 1Fh
for array 1), the counter “rolls o
issues the word address. Once the password has been
acknowledged and first byte has been read, another start
ver” to address 0 and
the X76F640 continues to output data for each acknowl- edge
received. Refer to figure 7 for the address, acknowl-
can be issued followed by a new 8-bit address. Random
reads are allowed, but only the low order 8 bits can
edge and data transfer sequence. An acknowledge must
follow each 8-bit data transfer. After the last bit has been
change. This limits random reads to a 256 byte block.
Therefore, with a single password cycle only a 256 byte
block of array 0 may be accessed randomly. To randomly
access another block of array 0, a stop must be issued fol-
read, a stop condition is generated without a preceding
acknowledge.
lowed by a new command/address/password sequence. A
random read of the array 1 can access all locations with-
out another password command sequence.
Figure 6. Random Read
Read
Password
Read
Password
7
COMMAND
0
Wait tWC OR
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
S
S
Data Y
Data X
7025 FM 11
7
X76F640
Figure 7. Sequential Read
Read
Password
7
Read
Password
0
Wait t
WC
OR
COMMAND
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
S
Data X
Data 0
7025 FM 12
PASSWORDS
After this time, it cannot be determined if the password has
been loaded correctly, without trying the new pass-
The sequence in Figure 8 shows how to change (pro-
gram) the passwords. The programming of passwords is
word. To determine if the new password has been loaded
correctly the data ACK polling command is issued imme-
done twice prior to the nonvolatile write cycle in order to verify
that the new password is consistent. After the eight
diately following the stop bit. If it returns an ACK, then the two
passes of the new password entry do not match. If it
bytes are entered in the second pass, a comparison takes
place. A mismatch will cause the part to reset and
enter into the standby mode.
returns a "no ACK" then the passwords match and a high
voltage cycle is in progress. The high voltage cycle is
complete when a subsequent data ACK command
returns an "ACK".
Data ACK polling can be used to determine if a password has
been loaded correctly, however the data ACK com-
mand must be issued less than 2ms after the stop bit.
There is no way to read any of the passwords.
Figure 8. Change Passwords
Old
Password
Old
Password
COMMAND
7
Wait tWC OR
0
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
New
Password
7
ACK POLLING
COMMAND
Two bytes of “0”
S
Data ACK
Polling
New
Password
7
New
Password
0
Password
0
If immediate ACK,
then New Password error
S
If immediate NACK,
followed by ACK after ~5ms
then New Password OK
7025 FM 13
8
X76F640
Figure 9. Reset Password
Wait t
WC
If ACK, then
Device reset
ReOpeRated
ACK Polling
Command
Reset
Password
0
Reset
Password
7
ACK POLLING
COMMAND
Reset Password
COMMAND
SDA
S
S
S
7025 FM 14
Figure 10. Reset Device
Wait t
WC
If ACK, then
Device reset
ReOpeRated
ACK Polling
Command
Reset
Password
0
Reset
Password
7
ACK POLLING
COMMAND
Reset Device
COMMAND
SDA
S
S
S
7025 FM 15
Figure 11. Response to RESET (RST)
CS
RST
SCK
3322222
1098765
2
4
2222111
3210987
1
6
111111
543210
9
8
7654321
0
SO
7025 FM 16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias.....................–. 65°C to +135°C
Storage Temperature..........................–.65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the
device at these or any other conditions above those
Respect to V
....................................–..1V to +7V
D.C. Output Curren.t..............................................5..m. A
SS
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Lead Temperature (Soldering,
10 seconds)
.................................
300°C
9
X76F640
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Extended
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X76F640
Limits
4.5V to 5.5V
2.7V to 3.6V
–20°C
X76F640 – 2.7
7025 FM T05
7025 FM T06
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA =
Open
VCC Supply Current
(Read)
ICC1
1
mA
RST = CS = VSS
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA =
Open
VCC Supply Current
(Write)
(3)
ICC2
3
mA
RST = CS = VSS
VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL
400 KHz, fSDA = 400 KHz
=
VCC Supply Current
(Standby)
(1)
∝A
∝A
ISB1
50
1
VSDA = VSCC = VCC Other =
GND or VCC–0.3V
VCC Supply Current
(Standby)
(1)
ISB2
∝A
∝A
ILI
VIN = VSS to VCC
VOUT = VSS to VCC
VCC = 5.5V
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
ILO
(2)
VCC x 0.3
VIL1
–0.5
V
V
V
V
V
(2)
VCC x 0.7VCC + 0.5
VCC x 0.1
VCC = 5.5V
VCC = 3.0V
VCC = 3.0V
IOL = 3mA
VIH1
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
(2)
VIL2
–0.5
(2)
VCC x 0.9VCC + 0.5
0.4
VIH2
VOL
7002 FM T07
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Test
Max.
Units
Conditions
(3)
VI/O = 0V
COUT
Output Capacitance (SDA)
8
6
pF
(3)
VIN = 0V
CIN
Input Capacitance (RST, SCL, CS)
pF
7002 FM T08
NOTES:
(1) Must perform a stop command after a read command prior to measurement
(2) VIL min. and VIH max. are for reference only and are not tested.
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
VCC x 0.1 to VCC x 0.9
Input Pulse Levels
5V
3V
Input Rise and Fall Times
Input and Output Timing Level
Output Load
10ns
1533Ο
1.3KΟ
VCC x 0.5
OUTPUT
OUTPUT
100pF
100pF
100pF
7002 FM T09
7025 FM 17
10
X76F640
AC CHARACTERISTICS
AC Specifications (Over the recommended operating conditions)
(1)
Symbol
fSCL
Parameter
SCL Clock Frequency
Min
Typ
Max
Units
0
400
KHz
Pulse width of spikes which must be suppressed by the
input filter
(1)
tIN
50
0.1
1.3
100
ns
∝s
tAA
SCL LOW to SDA Data Out Valid
0.3
0.9
Time the bus must be free before a new transmit can
start
∝s
tBUF
∝s
∝s
∝s
∝s
tLOW
Clock LOW Time
1.3
tHIGH
Clock HIGH Time
0.6
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
ns
∝s
Data In Hold Time
0
0.6
∝s
ns
ns
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
50
300
(2)
(2)
tR
tF
20 + 0.1 x Cb
300
300
SDA and SCL Fall Time
CS Setup Time
20 + 0.1 x Cb
200
ns
ns
tSU:CS
tHD:CS
CS Hold Time
100
ns
fSCL_RST
SCL Clock Frequency during Response to Reset
Device Select to RST active
400
kHz
ns
200
tSR
tNOL
RST to SCL Non-Overlap
500
2.25
1.25
1.25
1.25
0
ns
∝s
tRST
RST High Time
∝s
∝s
∝s
tSU:RST
tLOW_RST
tHIGH_RST
tRDV
Response to Reset Setup Time
Clock LOW during Response to Reset
Clock HIGH during Response to Reset
RST LOW to SDA Valid During Response to Reset
CLK LOW to SDA Valid During Response to Reset
Device Deselect to SDA high impedance
Typical values are for TA = 25˚C and VCC = 5.0V
500
500
500
ns
ns
tCDV
0
tDHZ
0
ns
7025 FM T14
Notes:1.
Notes:2. Cb = Total Capacitance of one bus line in pf.
11
X76F640
RESET AC SPECIFICATIONS
Power Up Timing
(2)
Symbol
Parameter
Min.
Typ
Max.
Units
(1)
tPUR
Time from Power Up to Read
Time from Power Up to Write
1
mS
(1)
tPUW
5
mS
7025 FM T11
Notes:1.
Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not
100% tested.
2. Typical values are for TA = 25˚C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
Parameter
Write Cycle Time
Min.
Typ.(1)
Max.
Units
(1)
tWC
5
10
mS
7025 FM T12
Notes:1.
tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
TIMING DIAGRAMS
Bus Timing
tR
tF
tHIGH
tLOW
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA
tDH
tBUF
SDA OUT
7025 FM 18
Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
tWC
Stop
Condition
Start
Condition
7025 FM 19
12
X76F640
CS Timing Diagram (Selecting/Deselecting the Part)
SCL
tHD:CS
tSU:CS
CS
from
master
7025 FM 20
RST Timing Diagram – Response to a Synchronous Reset
tSR
CS
RST
tRST
tHIGH_RST
tNOL
tNOL
1st
clk
pulse
2nd
clk
pulse
3rd
clk
pulse
CLK
I/O
tLOW_RST
tSU:RST
tCDV
tRDV
DATA BIT (2)
DATA BIT (1)
CS
RST
CLK
tDHZ
I/O
(N+2)
DATA BIT (N+1)
DATA BIT (N)
7025 FM 21
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
V
CCMAX
------------------------=-- 1.8KΟ
OLMIN
80
R
=
MIN
I
R
MAX
60
40
20
t
R
----------------
R
-
=
MAX
C
BUS
R
MIN
20
40 60 80 100
tR = maximum allowable SDA rise time
Bus capacitance in pF
7025 FM 22
13
X76F640
8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE
GULLWING PACKAGE TYP “A” (EIAJ SOIC)
0.020 (.508)
0.012 (.305)
.213
(5.41) .205
(5.21)
.330
(8.38) .300
(7.62)
PIN 1 ID
.050 (1.27) BSC
.212
(5.38) .203
(5.16)
.080
(2.03) .070
(1.78)
.013
(.330) .004
(.102)
0
8
REF
.010
(.254) .007
(.178)
.035
(.889) .020
(.508)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN P
ARENTHESES IN MILLIMETERS) 2.
PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
7025 FM 24
14
X76F640
8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
0.465 0.002
(11.81 0.05)
0.088 (2.24) MIN EPOXY
FREE AREA (TYP.)
0.285 (7.24) MAX.
R. 0.039 (1.00) (4X)
0.069 (1.75) MIN EPOXY
FREE AREA (TYP.)
0.270 (6.86) MAX.
0.420 0.002
(10.67 0.05)
A
A
0.008 0.001
(0.20 0.03)
0.210 0.002
(5.33 0.05)
0.233 0.002
(5.92 0.05)
DIE
0.0235 (0.60) MAX.
SECTION A-A
GLOB SIZE
0.015 (0.38) MAX.
0.008 (0.20) MAX.
FR4 TAPE
COPPER, NICKEL PLATED, GOLD FLASH
0.174 0.002
(4.42 0.05)
0.146 0.002
(3.71 0.05)
R. 0.013 (0.33) (8x)
0.105 0.002
(2.67 0.05)
TYP.
(8x)
0.105 0.002
(2.67 0.05)
(8x)
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3003 ILL 03.1
15
X76F640
SMART CARD TYPE Y
3.369 0.002
(85.57 0.05)
3° MAX.
DRAFT ANGLE
(ALL AROUND)
0.593 0.002
(15.06 0.05)
0.430 0.002
(10.92 0.05)
R. 0.125
(3.18) (4x)
A
0.475 0.010
(12.07 0.25)
2.125 0.002
(53.98 0.05)
A
R. 0.030 (0.76) (4x)
0.31 0.0005
(.079 0.0127)
0.478 0.002
(12.14 0.05)
MOLD GATE DETAIL
SECTION A-A
SCALE: 5x
NOTES:
1. ALL DIMENSIONS ARE IN INCHES AND (MILLIMETERS).
2. MATERIAL: WHITE PVC MOLDED PLASTIC WITH ANTI-STATIC ADDITIVE. 3.
SURFACE FINISH SUITABLE FOR OFFSET PRINTING.
3003 ILL 02.1
16
X76F640
ORDERING INFORMATION
X76F640
P
T
G –V
VCC Limits
Blank = 5V 10% 2.7
= 2.7V to 3.6V
Device
G=RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
Package
A = 8-Lead SOIC (EIAJ)
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Y = Smart Card
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no
warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without
notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402;
4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec- tion and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
2.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup- port device
or system, or to affect its safety or effectiveness.
17
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